JPH0254694B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a delay device used in a control circuit of an induction heating cooker.

Conventional configurations and their problems For example, when controlling the oscillation stop of an inverter in the control circuit of an induction cooking device, a startup delay and a zero-volt switch are used. Start-up is delayed in protection against power supply abnormalities, but stopping must be done without delay regardless of the zero-volt switch. In such a case, there is a normal input, and for the normal input, the rising edge is delayed by a zero-volt switch, the falling edge is delayed by a delay circuit,
For priority inputs, a delay device is used that delays only the falling edge. Conventionally, this type of delay device has a first delay circuit 1 connected to a second delay circuit 2 such as a zero-volt switch, and further includes a third delay circuit 3, as shown in FIG. Generally, a gate circuit 20 comprised of a circuit 3 and an OR circuit connected to the delay circuit 2 was used. FIG. 2 is a waveform diagram showing the operation of the conventional example in FIG. 1, where a, b, c, d, e, and f are the normal input a, priority input b, output c of the delay circuit 1, Output d of delay circuit 2, output e of delay circuit 3,
The delay device output f is shown. Also, t ₂ is the delay circuit 2
_t1 is the fall delay time caused by the delay circuit 1, and _t3 is the fall delay time caused by the delay circuit 3. As is clear from FIG. 2, the delay output f normally rises at t ₂ with respect to the input a.
The falling edge is delayed by _t1 , and for priority input b, only the falling edge is delayed by _t3 . However, in this configuration, an extra time constant circuit composed of a capacitor etc. that determines the delay time is required for the delay circuit 3.
Furthermore, there is a problem in that the difference between the fall delay times t ₁ and t ₃ becomes large due to variations in the two time constant circuits, differences in temperature characteristics, and the like.

Purpose of the Invention The present invention provides a delay device that solves these conventional problems, reduces the number of parts, eliminates the difference in fall time, reduces costs, and improves reliability and accuracy. be.

Configuration of the Invention The configuration of the present invention includes a first delay circuit configured with a monostable multivibrator connected to the normal input, a second delay circuit connected to the delay circuit, and a second delay circuit connected to the priority input. the latch circuit,
a gate circuit connected to the latch circuit output and the second delay circuit, and the first delay circuit includes a capacitor charged with a constant current through a resistor;
a discharge circuit that discharges the capacitor via the resistor, a first comparator that detects the voltage of the capacitor, a second comparator that detects the series voltage of the resistor and the capacitor, and a first RS.
Consists of a flip-flop and a first OR circuit,
The first comparator output is connected to the reset input of the first RS flip-flop, the output of the first OR circuit is connected to the set input of the first RS flip-flop, and the output of the RS flip-flop is connected to the discharge input. the normal input to a first input of the first OR circuit, and the priority input or the output of the latch circuit to a second input of the first OR circuit; ,
The output of the second comparator is connected to the input of the second delay circuit, and the latch circuit connects the output of the third comparator to a third comparator connected to the capacitor and detecting the voltage of the capacitor. The set input latch circuit connects a reset input to the priority input and connects a third comparator connected to the capacitor to detect the voltage of the capacitor, and connects the reset input to the output of the third comparator and sets the reset input to the priority input. a second RS flip-flop having its input connected to it, or a second RS flip-flop having its reset input connected to the output of said first comparator and its set input connected to said priority input;
The output of the second flip-flop is the output of the latch circuit, the output of the latch circuit is the first input of the gate circuit, and the output of the second delay circuit is the first input of the gate circuit. 2, the gate circuit is composed of an OR circuit, and the second delay circuit has a delay function only at the rising edge.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. In Figure 3, 5 is a monostable multivibrator with an OR circuit 7, an RS flip-flop 8, a transistor 9, a constant current source 10, and a resistor 1.
1, capacitor 12, comparator 13, 16,
It is composed of constant voltage sources 14 and 15. The monostable multivibrator 5 is triggered by either of the two inputs of the OR circuit. Reference numeral 6 denotes a latch circuit, which is composed of a constant voltage source 17, a comparator 18, and an RS flip-flop 19, and is reset when the input g becomes less than the voltage _V17 of the constant voltage source 17. The normal input a is connected to the trigger input of the monostable multivibrator 5, and the priority input b is connected to the trigger input of the monostable multivibrator 5 and the set input of the latch circuit 6. The output i of the monostable multivibrator 5 is connected to the input of a rise delay circuit 2, and the output j of this delay circuit 2
is connected to the input of a gate circuit 20 constituted by an OR circuit 4. The output k of the latch circuit 6 is connected to the input of the gate circuit 20. f
is the output of the gate circuit 20. g is the voltage of the capacitor 12 and is connected to the reset input of the latch circuit 6.

The operation of the above configuration will be explained using the waveform diagram of FIG. 4. In Figure 4, a, b, g, h, i, j,
k and f are signals with the same symbols in FIG. Further, dash-dotted lines V ₁₄ , V ₁₅ , and V ₁₇ are the voltages of the constant voltage sources 14, 15, and 17 in FIG. 3, respectively. Normally, the fall of the output i of the monostable multivibrator 5 is delayed by _t5 with respect to the fall of the input a, and the rise of the output j of the delay circuit 2 is delayed by _t1 with respect to the rise of i. Therefore, the rise and fall of the delay device output f are delayed by t ₁ and t ₅ , respectively, with respect to the normal input f. Similarly, with respect to the priority input b, the rise of j is delayed by t ₁ and the fall is delayed by t ₅ , but the delay device output f, which is the logical sum with the latch circuit output k, is delayed by t ₅ only in the fall.
That is, for the priority input, there is no delay in rising, and the delay time in falling is determined by the monostable multivibrator 5 as in the case of the normal input a, and is therefore equal to that in the case of the normal input a. Furthermore, when the priority input b is a pulse with a very short width, the reset of the latch circuit 6 is delayed from the signal b by the time T until the signal g reaches _V17 , as shown in the waveform diagram of FIG. Therefore, the minimum value of the H level time of signal k is guaranteed to be T. In the absence of said delay T, the signal k
has the same width as signal b, as shown by the broken line in FIG. 5, so an abnormality appears in signal f, as shown by the broken line in FIG. Therefore, by providing the delay T, a stable output can be obtained even when the priority input b is a pulse with a very short width.

FIG. 6 shows another embodiment of the present invention, in which one input of the OR circuit 7 constituting the monostable multivibrator 5 is connected to the output k of the latch circuit 6, and as can be easily inferred, the third It has the same effect as the embodiment shown.

FIG. 7 shows still another embodiment in which the comparator 18 and constant voltage source 18 of the embodiment in FIG. 3 are shared with the comparator 13 and constant voltage source 14, respectively. It has the same effect as the example and has the advantage of fewer parts.

FIG. 8 shows yet another embodiment, which constitutes the monostable multivibrator 22 of the other embodiment of FIG.
One input of the OR circuit 7 is connected to the output k of the latch circuit 21, and as can be easily inferred, the same effect as the other embodiment shown in FIG. 7 can be obtained.

Effects of the Invention As is clear from the above embodiments, the delay device of the present invention can reduce the number of parts, eliminate variations in fall time, reduce costs, and improve reliability.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional delay device, Fig. 2 is a waveform diagram showing the operation of the conventional example shown in Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the present invention, Figs.
3 is a waveform diagram showing the operation of the embodiment of FIG. 3, FIG. 6 is a block diagram showing another embodiment of the present invention, FIG. 7 is a circuit diagram showing still another embodiment, and FIG. 8 is a further embodiment of the present invention. FIG. 3 is a block diagram showing another embodiment. 2... Delay circuit, 5... Monostable multivibrator, 6... Latch circuit, 20... Gate circuit.

Claims (1)

[Claims] 1 A first delay circuit configured of a monostable multivibrator having a normal input and a priority input and connected to the normal input, a second delay circuit connected to this delay circuit, and the priority input. a latch circuit connected to this latch circuit output and said second latch circuit;
The first delay circuit includes a capacitor that is charged with a constant current through a resistor, a discharge circuit that discharges the capacitor through the resistor, and a gate circuit that is connected to the output of the delay circuit of the capacitor. a first comparator that detects the series voltage of the resistor and the capacitor, a second comparator that detects the series voltage of the resistor and the capacitor, a first RS flip-flop, and a first OR circuit. the output of the first OR circuit is connected to the set input of the first RS flip-flop; the output of the RS flip-flop is connected to the input of the discharge circuit; The normal input is connected to the first input of the OR circuit, and the first
The priority input or the output of the latch circuit is connected to a second input of the OR circuit, the output of the second comparator is connected to the input of the second delay circuit, and the latch circuit is connected to the capacitor. a third comparator for detecting the voltage of the capacitor; and a second RS flip-flop having a reset input connected to the output of the third comparator and a set input connected to the priority input, or the output of the first comparator. and a second input with a reset input connected to the priority input and a set input connected to the priority input.
The output of the second flip-flop is the output of the latch circuit, the output of the latch circuit is the first input of the gate circuit, and the output of the second delay circuit is the first input of the gate circuit. 2, the gate circuit is composed of an OR circuit, and the second delay circuit has a rising-only delay function.