JPH0277797A - Ringing sound generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a ringing sound generating circuit, and relates to a technique that is effective when used in, for example, a circuit built into a telephone terminal kneader/decoder.

[Conventional technology]

The variable pull counter can be constructed, for example, by combining the bit comparator described in "Practical Electronic Circuit Handbook 2J, page 53," published by CQ Publishing Co., Ltd., and the f/n frequency divider, described in page 100.

[Problem to be solved by the invention]

In button telephones, etc., a ringing sound (
is generating a ringing tone). In conventional ringing sound generation circuits, the frequency is semi-fixed, and the output waveform is fixed to one of a pulse waveform, an envelope, or a sine wave. For this reason, if a selection function for a plurality of frequencies and different waveforms is added, the circuit scale increases accordingly. The ability to set various tones of ringing sounds is an additional function for digital button telephones, and it is an additional function for digital button telephones, and it is an additional function of the main functions of analog/digital conversion circuits and digital/analog conversion circuits (so-called codec functions). In semiconductor integrated circuits with
It is not a good idea to incorporate the above-mentioned additional functions even if it increases the chip area.

An object of the present invention is to provide a ringing sound generation circuit that can select multiple tones with a small-scale circuit configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the output signal of the variable frequency divider circuit that receives the clock pulse is counted by a counter circuit, and the output signal is supplied to a staircase wave generation circuit and an envelope generation circuit that output a staircase wave. An output circuit is provided to selectively output the output signals of the output pulse and envelope generation circuits.

[For production]

” - The fundamental frequency can be selected by the distributed variable frequency divider circuit, and one tone can be selected from a staircase wave, envelope, or pulse waveform.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a ringing generating circuit according to the present invention.

Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Although not particularly limited, the ringing sound generation circuit of this embodiment is an A/R for digitizing and transmitting audio signals.
Codec (CO) including D conversion circuit and D/A conversion circuit, etc.
It is built into the semiconductor integrated circuit that makes up the DEC.

The pulse φ is, for example, a 128 KHz clock pulse used in a swissotide capacitor filter. This clock pulse φ is formed by a PLL (phase locked loop) circuit that receives an 8 KHz basic clock supplied from the outside. Lock pulse φ
By using this, a special oscillation circuit for the ringing sound generation circuit can be made unnecessary.

The clock pulse φ is supplied to a first counter circuit C0UNTI having a 5-bit configuration. This first counter circuit C0UNTI constitutes a variable frequency dividing circuit together with a comparator including a register REG and exclusive OR circuits EXI to EX4, which will be described next.

The output signal Q of each bit of the counter circuit C0UNTI except for the first stage circuit is supplied to one input of the exclusive OR circuits EX1 to EX4. These exclusive OR circuits EX
The output signal Q of each bit of the register REG is supplied to the other inputs of I to EX4. The output signals of the exclusive OR circuits EXI to EX4 are inverted and supplied to the input of the AND gate circuit G2. That is, register RE
Each bit set to G and the counter circuit C0UNTI
When each corresponding focus matches, the output of the AND gate circuit G2 is set to logic "1".

The output signal of this gate circuit G2 is the NOR gate circuit G3.
and G4, and its output signal is inverted and supplied to the reset terminal R of the counter circuit C0UNTI via the buffer Bl. As a result, the bit information set in the above register REG @
Since the counter circuit C0UNTI is reset every time (RO~R3) and the count output of the counter circuit C0UNTI match, variable frequency division operation can be performed by inputting the information to be counted into the register REG. Can be done. The launch circuits (G3 and G4) are reset by the output signal Q of the first stage circuit of the counter circuit C0UNT1, and the reset state of the counter circuit C0UNTI is released.

When the clock pulse φ is set to 128 KHz as described above, the bit information RO to R supplied to the register REG
By combining 3, it is possible to receive 16 frequency-divided output signals from 8 KHz to 64 KHz.

The output signal of the launch circuit is used as the output signal of the variable frequency divider circuit and as a manual pulse of the second counter circuit C0UNT2. That is, the output signal of the buffer B1 is inverted via the inverter circuit N1 and supplied to the input terminal of the second counter circuit C0UNT2.

This counter circuit C0UNT2 has a 4-bit configuration, and the count output Q of each bit is supplied to the staircase wave generation circuit SWG. This staircase wave generation circuit SWG generates a positive/negative triangular staircase wave W2 depending on the low level/high level of the final stage output signal, although this is not particularly limited. In other words, the staircase wave W2 is generated by the counter circuit C0UNT2.
It is a pseudo sine wave with one cycle being one rotation of .

Further, the envelope generating circuit EG has a time constant set by an external capacitor C and a resistor R, although it is not particularly limited, and receives the bit output of the final stage of the second counter circuit COtJN T2 and differentiates it. A waveform signal W3 as shown in FIG.

The above staircase wave generation circuit SWG and envelope generation circuit EC
The respective output signals and the output pulse W1 of the second counter circuit C0UNT2 are output from the output terminal OUT via the multiplexer MPX.

The multiplexer MPX selects and outputs one of the three input signals Wl-W3 from a combination of 2-bit control signals S1 and 82.

The control signals S1 and 82 may be formed by a built-in microcomputer, input from external terminals, or semi-fixed by changing fuse means or wiring.

The AND gate circuits G5 to G7 have a logic "" when the second counter circuit C0UNT2 is in an initial state, the first counter circuit C0UNTI is in a reset state, and the input clock pulse φ is at a low level. It forms an output signal of 1'' and permits presetting of the register REG. Thereby, since the frequency is changed every cycle of the output signal, generation of noise can be prevented. Furthermore, when logic “0” is input to the register REG, the second
The counter circuit C0UNT2 is reset. Therefore, when changing the output waveform using the multiplexer MPX, by clearing the register REG, it is possible to prevent the generation of noise when changing the waveform.

In the above configuration, since there are 16 frequencies and 3 types of waveforms can be selected, it is possible to generate ringing sounds with 16×3=48 tones. Moreover, since the envelope can be set using an external capacitor C and a resistor R, it is possible to substantially obtain a larger number of tones. In addition, the input signals RO to R3 of the register REG are as follows:
If they are generated together with the control signals S1 and S2 by a micro combinator, a huge number of ringing sounds can be generated from the combination of the frequency change, waveform switching, etc.

This example circuit supports three tones by using the output signal of the PLL circuit that constitutes the codec section and passing it through a variable frequency dividing circuit to share the frequency settings for three types of waveforms. By unifying three systems of counter circuits into one system, the circuit can be significantly simplified. This reduces the circuit scale and allows it to be built into the semiconductor integrated circuit constituting the codec.

The effects obtained from the above examples are as follows. That is, (1) the output signal of the variable frequency divider circuit that receives the clock pulse is set high by the counter circuit, and the output signal is supplied to the staircase wave generation circuit and the envelope generation circuit that output the staircase wave, and the above-mentioned staircase wave generation circuit An output circuit is provided for selectively outputting the output pulse of the counter circuit and the output signal of the envelope generation circuit.

In this configuration, the fundamental frequency can be selected by the variable frequency dividing circuit, and one tone can be selected from a staircase wave, an envelope, or a pulse waveform.

(2) In +11 above, by using the output signal of the PLL circuit that constitutes the codec section as the clock pulse and passing it through a variable frequency divider circuit to make the frequency settings common for the three types of waveforms, 3. By unifying three systems of counter circuits corresponding to timbres into one system, it is possible to significantly simplify the circuit, so that it is possible to incorporate the codec into the semiconductor integrated circuit constituting the codec.

(3) Since the frequency is changed using a variable frequency divider circuit and the tone selection is outputted via a multiplexer, 1 tone, 2 tone, and 3 tone can be selected by software using a microcomputer, etc. The effect is that continuous frequency and timbre changes are possible.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. Nor. For example, the clock pulse may be generated by using a PLL circuit for a codec as described above, by using other suitable pulse signals, or by providing an oscillation circuit. The configuration of the variable frequency divider circuit can be modified in various ways. Further, the ringing sound generating circuit may be one built in a semiconductor integrated circuit constituting the codec section or one built in a semiconductor integrated circuit for a telephone.

The present invention can be widely used as a ringing sound generating circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a counter circuit counts the output signal of a variable frequency divider circuit that receives clock pulses, and supplies the output signal to a staircase wave generation circuit and an envelope generation circuit that output a staircase wave. An output circuit is provided for selectively outputting the output pulse and the output signal of the envelope generating circuit. In this configuration, the fundamental frequency can be selected by the variable frequency dividing circuit, and one tone can be selected from a staircase wave, an envelope, or a pulse waveform.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a ringing sound generating circuit according to the present invention. C0UNTI, C0UNT2...Counter circuit, REG
...Register, 01-G7...Gate circuit, N1-N3
・・Inverter circuit, EXI-EX4・・Exclusive OR circuit, SWG・・Staircase wave generation circuit, EG・・Envelope generation circuit, MPX・・Multiplexer

Claims (1)

[Claims] 1. A variable frequency divider circuit that receives clock pulses, a counter circuit that receives the output signal of this variable frequency divider circuit, and one circuit of the counter circuit that receives the output signal of each bit of the counter circuit. a staircase wave generation circuit that outputs a staircase wave with one period of , an envelope generation circuit that receives the output signal of the counter circuit, and an envelope generation circuit that receives the output pulses of the staircase wave generation circuit and the counter circuit and the output signal of the envelope generation circuit. A ringing sound generating circuit comprising: an output circuit for selectively outputting the ringing sound. 2. The ringing generation circuit is built in a telephone terminal semiconductor integrated circuit device including an A/D and D/A conversion circuit, and the clock pulse is a basic clock pulse used therein. A ringing sound generating circuit according to claim 1, characterized in that: 3. The ringing sound generating circuit according to claim 1 or 2, wherein the envelope generating circuit has an output waveform set by a time constant circuit comprising an external resistor and a capacitor. .