JPH0295447U - - Google Patents
Info
- Publication number
- JPH0295447U JPH0295447U JP414789U JP414789U JPH0295447U JP H0295447 U JPH0295447 U JP H0295447U JP 414789 U JP414789 U JP 414789U JP 414789 U JP414789 U JP 414789U JP H0295447 U JPH0295447 U JP H0295447U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- emulation
- state
- supervisor
- executes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013256 coordination polymer Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000002123 temporal effect Effects 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は、本考案の一実施例の逆実行機能付エ
ミユレータの機能構成を示すブロツク図、第２図
は本考案の一実施例の逆実行機能付エミユレータ
の状態の時間的な流れを表した図、第３図は、従
来のエミユレータの機能構成を示すブロツク図、
第４図は、従来のエミユレータの状態の時間的な
流れを表した図である。
１０１……エミユレーシヨンＣＰＵ、１０２…
…スーパーバイザＣＰＵ、１０３……状態変化メ
モリ、１０４……外部入出力手段、２０１……特
定状態Ａ、２０２……特定状態Ｂ、２０３……初
期状態、２０４……特定状態Ｃ、２０５……外部
条件、３０１……エミユレーシヨンＣＰＵ、３０
２……スーパーバイザＣＰＵ、３０３……外部入
出力手段、４０１……特定状態Ａ、４０２……特
定状態Ｂ、４０３……初期状態、４０４……再実
行開始状態、４０５……外部条件。
Fig. 1 is a block diagram showing the functional configuration of an emulator with a reverse execution function according to an embodiment of the present invention, and Fig. 2 shows a temporal flow of states of the emulator with a reverse execution function according to an embodiment of the present invention. Figure 3 is a block diagram showing the functional configuration of a conventional emulator.
FIG. 4 is a diagram showing the chronological flow of states of a conventional emulator. 101... Emulation CPU, 102...
...Supervisor CPU, 103...State change memory, 104...External input/output means, 201...Specific state A, 202...Specific state B, 203...Initial state, 204...Specific state C, 205...External Condition, 301... Emulation CPU, 30
2... Supervisor CPU, 303... External input/output means, 401... Specific state A, 402... Specific state B, 403... Initial state, 404... Re-execution start state, 405... External condition.
Claims (1)
レーシヨンＣＰＵと、前記エミユレーシヨンＣＰ
Ｕの実行・停止などの動作を管理するスーパーバ
イザＣＰＵと、前記スーパーバイザＣＰＵに対し
て指示を行う外部入出力手段と、前記スーパーバ
イザＣＰＵの管理化でエミユレーシヨンＣＰＵの
逆実行を行うために前記スーパーバイザＣＰＵの
管理下における前記エミユレーシヨンＣＰＵがあ
るインストラクシヨンを実行した際に前記エミユ
レーシヨンＣＰＵの状態の変化に対して前記エミ
ユレーシヨンＣＰＵの状態が変化することにより
失われた情報を記憶する状態変化メモリとを備え
る事を特徴とするエミユレータ。 an emulation CPU that executes a target instruction, and the emulation CP
a supervisor CPU that manages operations such as execution and stopping of U; an external input/output means that gives instructions to the supervisor CPU; and a state change memory for storing information lost due to a change in the state of the emulation CPU when the emulation CPU under management executes a certain instruction. An emulator featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP414789U JPH0295447U (en) | 1989-01-17 | 1989-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP414789U JPH0295447U (en) | 1989-01-17 | 1989-01-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0295447U true JPH0295447U (en) | 1990-07-30 |
Family
ID=31206400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP414789U Pending JPH0295447U (en) | 1989-01-17 | 1989-01-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0295447U (en) |
-
1989
- 1989-01-17 JP JP414789U patent/JPH0295447U/ja active Pending