JPH0314827Y2 - - Google Patents

Description

[Detailed description of the invention] [Field of industrial application] This invention is applicable to devices that reproduce and process two-channel digital signals to restore two-channel analog signals, such as a two-channel digital audio disc player, a digital audio disc player, etc. The present invention relates to a digital/analog conversion device used in a digital/analog conversion processing unit of a tape recorder or the like.

[Conventional technology]

Conventionally, digital audio disc players and digital audio tapes have been used as devices for reproducing and processing two-channel (stereo) digital audio signals (PCM signals) to restore stereo analog audio signals. Various devices have been devised, such as a recorder, a compact disk player with a digital stereo audio playback function, a videotape recorder with a digital stereo audio playback function, and a digital stereo broadcast receiver.

Each of the above-mentioned devices has two channels obtained by playback or reception, that is, stereo left,
In order to convert the right channel digital signal into analog, a digital/analog conversion processing unit is provided, and the conversion processing unit converts the digital signals of the two channels from digital to analog, respectively, and performs low-pass filter processing to convert the digital signals of the left and right channels. To restore a two-channel analog signal such as an analog audio signal.

Therefore, the digital/analog conversion processing section is formed by a digital/analog conversion device having a digital/analog conversion circuit, a low-pass filter, and the like.

By the way, for example, as described on pages 145 to 17 of "Digital Audio" co-authored by Doi and Iga, published by Radio Gijutsusha (reprinted on June 5, 1981), a digital/analog conversion circuit (D/A converter) ) is the period from when the digital signal is input until the output voltage or output current becomes less than the specified error.
A certain amount of time specified by settling time and conversion speed is required, and
A large overshoot may occur in the voltage of the converter output within the predetermined time. Note that a large error occurring during the settling time is called a glitch.

In addition, in the case of an integral type digital/analog conversion circuit, the integral current of the digital signal that forms the output current changes at a constant value during the conversion period, regardless of the digital input; High-order harmonics exist together with the fundamental wave, and these high-order harmonics cannot be removed by a subsequent low-pass filter, that is, a low-pass filter for restoring the analog signal.

In order to prevent the above-mentioned overshoot and high-order harmonics from being mixed into the restored analog signal, the output current or voltage of the digital/analog conversion circuit is converted into a complete amplitude-modulated pulse wave using a deglitch circuit. (PAM wave) and then output to a low-pass filter.For example, a digital/analog conversion device equipped with an integral type digital/analog conversion circuit is a 16-bit D model number CX-20017 manufactured by Sony Corporation. As described in catalogs of /A converter integrated circuits, etc., a deglitch circuit formed by an analog switch integrated circuit is provided after the digital/analog conversion circuit formed by the D/A converter integrated circuit. There is.

By the way, the conventional digital/analog converter described in the above-mentioned catalog etc. is formed as shown in Fig. 2, and in the same figure, 1 is the above-mentioned model number.
This is a digital/analog conversion circuit formed by the CX-20017 integrated circuit, and pins 18 and 17
8 and 17 form output terminals Oa and Ob for integral current signals of two channels of digital signals, and pins 23 and 15 form discharge control terminals Da and Db for two channels, respectively.

2 is a first current/voltage conversion circuit that converts the integrated current signal of one channel of the output terminal Oa into a voltage signal, and includes an operational amplifier Aa and an integrating capacitor Ca.
The inverting input terminal (-) of the amplifier Aa is connected to the output terminal Oa, and a capacitor is connected between the inverting input terminal (-) of the amplifier Aa and the output terminal.
Ca and the source and drain of the transistor Qa are connected in parallel, and the non-inverting input terminal (+) of the amplifier Aa is grounded.
The gate of Qa is connected to the control terminal Da.

3 is a second current/voltage conversion circuit that converts the integrated current signal of the other channel of the output terminal Ob into a voltage signal, and includes an operational amplifier Ab and an integrating capacitor Cb.
With the integration circuit of and discharge transistor Qb,
It is formed similarly to the conversion circuit 2. Note that the gate of transistor Qb is connected to control terminal Db.

4 is a first level shift circuit that level-shifts the output voltage of the conversion circuit 2, and includes voltage dividing resistors Ra and Rb.
is formed by a series circuit of and a capacitor Cc for preventing crosstalk bypass between channels.
One end of the series circuit of resistors Ra and Rb is connected to the output terminal of the amplifier Aa via the output resistor Rc, and the other end is connected to the negative power supply terminal Vn, and the resistors Ra,
A capacitor Cc is provided between the ground point of Rb and the ground.

5 is a second level shift circuit that level-shifts the output voltage of the conversion circuit 3, and includes voltage dividing resistors Rd and Re.
It is formed by a series circuit of , and a capacitor Cd for preventing crosstalk bypass between channels.
One end of the series circuit of the resistors Rd and Re is connected to the output terminal of the amplifier Ab via the output resistor Rf, and the other end is connected to the negative power supply terminal Vn.
A capacitor Cd is provided between the connection point and ground.

6 and 7 are first and second deglitch analog switches each formed by two analog switches of a 4053 type 4-circuit analog switch integrated circuit such as a model number 14053B analog switch integrated circuit, and each has a common terminal x. , x′, first
It has contact terminals p, p' and second contact terminals q, q', and the common terminals x, x' are connected to the output terminals of amplifiers Aa, Ab via resistors Rc, Rf, respectively, and the second contact terminal q and the first contact terminal p' are grounded, and by the deglitch control signal of the control signal terminal K, the common terminals x, x' of both switches 6, 7 are interlocked, and the first contact terminals p, p' and the It is alternately switched to two contact terminals q and q'.

Ac is an operational amplifier forming an inverting amplifier for one channel, and its non-inverting input terminal (+) is grounded, its inverting input terminal (-) is connected to the first contact terminal p, and its non-inverting input terminal ( −)
A parallel circuit of a resistor Rg and a capacitor Ce is provided between the output terminal and the output terminal, and the output terminal is connected to a low-pass filter (not shown) for one channel.

Ad is an operational amplifier forming an inverting amplifier for the other channel, and its non-inverting input terminal (+) is grounded, its inverting input terminal (-) is connected to the second contact terminal q', and its inverting input terminal ( A parallel circuit of a resistor Rh and a capacitor Cf is provided between the output terminal and the output terminal, and the output terminal is connected to a low-pass filter (not shown) for the other channel.

Then, the conversion circuit 1 converts the two channels of digital signals obtained by reproduction or reception into digital signals of one channel based on a clock signal having the same frequency and the same phase as the degritch control signal. At the same time as taking in the signal, when the clock signal is at a low level, the digital signal of the other channel is taken in, and by repeating this operation, the digital signals of both channels are taken in alternately.

Furthermore, the conversion circuit 1 forms an integral current signal with a time proportional to the digital signal taken in, and when the clock signal is at low level, the integrated current signal of the digital signal taken in when the clock signal was at the previous high level is generated. The signal is output from the output terminal Oa, and when the clock signal is at high level, the integrated current signal of the digital signal taken in when it was at the previous low level is output from the output terminal Ob. Integrated current signals of two channels of digital signals are outputted alternately from terminals Oa and Ob in a time-division manner.

Further, the conversion circuit 1 outputs a discharge control signal from the control terminal Da to turn on the transistor Qa when the clock signal is at a low level, and outputs a discharge control signal from the control terminal Db when the clock signal is at a high level. output and turn on transistor Qb.

Therefore, the integrated current signal of one channel outputted from the output terminal Oa of the conversion circuit 1 is converted into a voltage signal by the conversion circuit 2, and the integrated signal of the other channel outputted from the output terminal Ob is converted by the conversion circuit 3. converted into a voltage signal.

By the way, the voltage signals of both conversion circuits 2 and 3 change in a positive voltage range based on the level of the input integral current signal. For example, the voltage signal of conversion circuit 2, that is, the voltage signal of the output terminal of amplifier Aa, is as follows.
When there is no digital signal, that is, when there is no integrated current signal, the clock signal, as shown in FIG. 3a, is held at the reference level Vd during each low level of the deglitch control signal in FIG. , when there is a digital signal, that is, when there is an integral current signal, a positive voltage is generated depending on the level of the integral current signal between each low level of the deglitch control signal shown in FIG. Varies in range. Note that the voltage signal at the output terminal of amplifier Ab also changes in the same way as the voltage signal at the output terminal of amplifier Aa.

The voltage signals of both conversion circuits 2 and 3 are applied to a first deglitch circuit 8 for one channel formed by a switch 6 and an amplifier Ac, and a second deglitch circuit 8 for the other channel formed by a switch 7 and an amplifier Ad. The circuit 9 deglitches each circuit, but if the voltage signals input to both deglitch circuits 8 and 9 change only within the positive voltage range, a power supply circuit (not shown) that supplies power to each circuit is activated. ) must output a high positive power supply voltage as the power supply voltage, and in this case the power supply efficiency decreases. Note that the power supply circuit is a power supply terminal.
It also outputs the negative power supply voltage that is supplied to Vn, etc.

Therefore, level shift circuits 4 and 5 are provided, and both amplifiers Aa and Ab are connected by both level shift circuits 4 and 5.
The voltage signals outputted from the deglitch circuits 8 and 9 are shifted in level, and the voltage signals input to both deglitch circuits 8 and 9, for example, are shifted so that the reference level Vd mentioned above becomes O volts, which is the ground level, and changes to positive or negative. The positive power supply voltage outputted from the power supply circuit is converted into a signal to reduce the positive power supply voltage outputted from the power supply circuit, thereby improving power supply efficiency.

Note that when the voltage signals of the reference level Vd are output from the amplifiers Aa and Ab, the levels of the voltage signals input to both deglitch circuits 8 and 9 are Vo ₁ ,
When Vo ₂ is set, the resistance values Ra′, Rb′, of the resistors Ra to Rf are
Rc′, Rd′, Re′, Rf′ are Vo ₁ /Rc′, Vo ₂ /Rf′ are |−Vc|/(Ra′+Rb′), |−Vc|/(Rd′+
Re′), and −Vc is the negative power supply terminal.
It is the voltage of Vn.

Then, the voltage signal of the amplifier Aa, which has been level-shifted by the level shift circuit 4, is supplied to the common terminal A voltage signal is supplied to the common terminal x' of the analog switch 7 during the high level of the degritch control signal, and both switches 6, 7 are interlocked and close the first contact during the low level of the degritch control signal. At the same time, the second contacts q and q' are switched to the second contacts q and q' while the deglitch control signal is at a high level.

On the other hand, the degritch control signal becomes low level during the stable period excluding the settling time period of the voltage signal of one channel, and
It is set to be at a high level during a stable period excluding the settling time period of the voltage signal of the other channel.

Therefore, for the voltage signal of one channel inputted to the common terminal x of the switch 6, only the stable period portion of the voltage signal is outputted from the first contact terminal p, and is inputted to the common terminal x' of the switch 7. Also, only the stable period portion of the voltage signal of the other channel is outputted from the second contact terminal q'.

Furthermore, an aperture circuit for waveform shaping of one channel is formed by the inverting amplifier consisting of the amplifier Ac, resistors Rc, Rg, and capacitor Ce, and the amplifier Ad, resistors Rf, Rh, and capacitor
Cf forms an aperture circuit for waveform shaping of the other channel, and both aperture circuits shape the voltage signal at the first contact p of the switch 6, and the voltage signal at the second contact q' of the switch 7. is waveform shaped.

That is, the settling time portion of each voltage signal of both channels is removed by the switches 6 and 7, but at this time, the pulse output from both switches 6 and 7 is The Takajo frequency characteristics of the waves deteriorate.

Therefore, both aperture circuits correct the duty of each pulse wave output from the switches 6 and 7, that is, aperture correction is performed.

Then, by the level shift of the level shift circuit 4, the deglitch of the switch 6, and the aperture correction described above, a pulse signal of one channel of a complete PAM wave based on the digital signal of one channel is output to the output terminal of the amplifier Ac. At the same time, by the level shift of the level shift circuit 5, the degrit of the switch 7, and the above-mentioned aperture correction, a complete PAM signal based on the digital signal of the other channel is sent to the output terminal of the amplifier Ad.
The pulse signal of the other channel of the wave is output,
At this time, both pulse signals are held at O volts as shown in Figure 3c when there is no digital signal, and positive or negative depending on the digital signal as shown in Figure 4c when there is a digital signal. Changes to

Then, the pulse signal of the amplifier Ac is input to a low-pass filter for one channel, and the pulse signal of the amplifier Ac is smoothed by the filter.
The restored analog signal of one channel is output from the low-pass filter.

Further, the pulse signal of the amplifier Ad is input to a low-pass filter for the other channel, and the pulse signal of the amplifier Ad is smoothed by the filter,
The restored analog signal of the other channel is output from the low-pass filter.

[Problem that the invention attempts to solve]

However, in the case of FIG. 2, it is necessary to provide two level shift circuits, which poses a problem that the configuration becomes complicated and expensive.

In the case of Fig. 2, switches 6 and 7 are formed using analog switches for two circuits of a four-circuit analog switch integrated circuit, so the remaining two analog switches are not used. ,
It is extremely uneconomical.

[Means for solving problems]

This invention consists of an integral type digital/analog conversion circuit that alternately captures digital signals of two channels and outputs integrated current signals of the digital signals of both channels in a time-division manner, and converts the integrated current signals of both channels into voltage signals. A pair of current/voltage conversion circuits to be converted, respectively, and a level shift circuit are connected to the output terminals of both current/voltage conversion circuits, and the voltage signals of both current/voltage conversion circuits are connected to the ground level. a level-shifting analog switch for shifting to a reference level; and two level-shifting analog switches for outputting only the stable period portion of the voltage signal of each of the level-shifted current/voltage conversion circuits, which is controlled by a degritch control signal. The digital/analog conversion device is provided with a deglitch analog switch, and the level shift analog switch is switched by the degritch control signal.

[Effect]

Therefore, by switching the level shift analog switch using the degritch control signal, one level shift circuit is shared for level shifting the voltage signals of both channels, and a device is formed by providing one level shift circuit. Ru.

〔Example〕

Next, this invention will be explained in detail with reference to FIG. 1 showing one embodiment thereof.

(Configuration) In FIG. 1, the same symbols as in FIG. 2 indicate the same things, and the difference is that one level shift circuit 10 is provided instead of the two level shift circuits 4 and 5 in FIG. In addition, a level shift analog switch 11 consisting of one of the two analog switches is provided in the remainder of the four-circuit analog switch integrated circuit in which two analog switches are used for switches 6 and 7. .

Note that the level shift circuit 10 includes voltage dividing resistors.
It is formed by a series circuit of Ri and Rj and a capacitor Ci for preventing crosstalk bypass between channels, and one end of the series circuit of resistors Ri and Rj is connected to the negative power supply terminal Vn, and the connection point of resistors Ri and Rj is connected to the negative power supply terminal Vn. A capacitor Ci is provided between the ground and the ground.

In addition, the switch 11 has a common terminal x'' connected to a resistor Ri,
Rj is connected to the other end of the series circuit, and the first and second contact terminals p'' and q'' are connected to the common terminals x and x' of switches 6 and 7, respectively, and the control signal terminal K is deglitted. It is switched in conjunction with switches 6 and 7 by a control signal.

(Operation) When the degritch control signal is at low level, each switch 6, 7, 11 is switched to the first contact terminal p, p', p'', and the integrated current of one channel from the conversion circuit 1 is switched to the first contact terminal p, p', p''. Since the voltage signal of one channel is output from the amplifier Aa based on the signal, the voltage signal of the one channel is level-shifted by the level shift circuit 10, and at this time, the resistance values of the resistors Ri and Rj are For example, the resistances Rb and Ra of level shift circuit 4
The voltage signal of one channel is level-shifted as in the case of FIG. 2.

Conversely, when the degritch control signal is at a high level, each switch 6, 7, 11 is switched to the second contact terminal q, q', q'', and the integrated current signal of the other channel from the conversion circuit 1 is switched to the second contact terminal q, q', q''. Based on this, since the voltage signal of the other channel is output from the amplifier Ab, the voltage signal of the other channel is outputted to the second channel by the level shift circuit 10.
The level is shifted as in the case shown in the figure.

Furthermore, the level-shifted voltage signals of both channels are subjected to deglitching and aperture correction by switches 6 and 7 in the same manner as in the case of FIG. A complete PAM wave pulse signal is output respectively.

In order to level shift the voltage signals of both channels using one level shift circuit 10 and switch 11, one level shift circuit 1 is used.
0 is commonly used for level shifting the voltage signals of both channels, simplifying the configuration and reducing the cost.

In the case of FIG. 1, the switch 11 is formed by an unused analog switch of the analog switch integrated circuit for four circuits.
It can be formed by omitting either one of the level shift circuits 4 and 5 from FIG. 2, resulting in a significant reduction in cost.

[Effect of idea]

As described above, according to the digital/analog converter of this invention, one level shift circuit 10
can be used for level shifting of the voltage signals of both channels output from the first and second current/voltage conversion circuits 2 and 3, and the configuration can be simplified and the cost can be reduced.

[Brief explanation of the drawing]

Figure 1 is a block diagram of one embodiment of the digital/analog converter of this invention, Figure 2 is a block diagram of a conventional digital/analog converter, and Figure 3a.
-c and FIGS. 4a to 4c are waveform diagrams for explaining the operation of FIG. 2. 1...Digital/analog conversion circuit, 2, 3,
...First and second current/voltage conversion circuits, 6, 7...
Analog switch for 1st and 2nd degrit, K...
...Control signal output terminal, 10...Level shift circuit, 11...Analog switch for level shift.

Claims (1)

[Claims for Utility Model Registration] Two channels of digital signals are taken in alternately,
an integral type digital/analog conversion circuit that time-divisionally outputs integrated current signals of the digital signals of both channels; a pair of current/voltage conversion circuits that converts the integrated current signals of both channels into voltage signals, respectively; a level shift analog switch that switches and connects one level shift circuit to the output terminals of both current/voltage conversion circuits, and shifts the voltage signals of both current/voltage conversion circuits to a level based on an earth level; two deglitch analog switches that are controlled by a degritch control signal and output only a stable period portion of the voltage signal of each of the level-shifted current/voltage conversion circuits, and the degritch control A digital/analog conversion device in which the level shifting analog switch is switched by a signal.