JPH0316136A - Integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital integrated circuit, and more particularly to an integrated circuit that selects and uses one of a plurality of oscillation circuits for an internal clock.

[Conventional technology]

Conventionally, in an integrated circuit incorporating an oscillation circuit for a system clock, an oscillator is connected to a terminal drawn out from the oscillation circuit to cause oscillation, and the oscillation signal is used as an internal system clock. In addition, when performing synchronized operation with multiple integrated circuits or in order to reduce the number of oscillators used, the clock output of other integrated circuits can be transmitted through the terminal to which the oscillator is connected without using the oscillation circuit of that integrated circuit. It can also be used to supply.

[Problem to be solved by the invention]

The conventional integrated circuits described above must be adaptable to either usage. However, in an integrated circuit having a plurality of oscillation circuits, which selects one of the oscillation circuits depending on its internal state and uses the selected oscillation circuit as the system clock, it is not possible to perform synchronized operation with other integrated circuits. In particular, it is difficult to operate other chips using a common clock depending on the selection of the oscillation circuit of the integrated circuit.

An object of the present invention is to eliminate such drawbacks and provide an integrated circuit that can synchronize an external clock from an oscillation terminal and use it as a system clock, and also allows the oscillation circuit used to be monitored externally. .

[Means to solve the problem]

The structure of the present invention includes a plurality of oscillation circuits, a selection register that holds which of the output signals of these oscillation circuits is to be selected, and one of the oscillation signals according to the contents of the selection register.
and a first gate means for selecting one of the first oscillation circuits as a system clock, the output signal of the first oscillation circuit of the oscillation circuits is controlled according to the switching signal regardless of the contents of the selection register. A second gate means for selecting a system clock, and a third gate means for outputting the contents of the selection register from an oscillator connection terminal of an oscillation circuit other than the first oscillation circuit in accordance with the switching signal. Features.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram illustrating an embodiment of the present invention. The integrated circuit of this embodiment includes a first oscillation circuit 10, a second oscillation circuit 20, oscillator connection terminals 1, 2, 3, 4 of these oscillation circuits 10 and 20, and transmission gates 1, 2.
1.80, AND gate 51.52, OR gate 53,
It consists of a NAND gate 60, an inverter 70, and a latch 40.

An oscillator connection terminal 2 is connected to the first oscillation circuit 10 via an oscillator connection terminal 1 and a transmission gate 11 , and the oscillator connection terminal 2 simultaneously serves as one input of an AND gate 51 . The other input is NAN
The output of D gate 6o is input. Second oscillation circuit 2o
The oscillator connection terminal 3 and transmission gate 21 are connected to
The oscillator connecting terminal 4 is connected through the oscillator connecting terminal 4, and the oscillator connecting terminal 4 simultaneously serves as one input of the AND gate 52, and serves as another input of the AND gate 52 through the transmission gate 80, and also serves as the other input of the AND gate 52 through the transmission gate 80.
The signal passing through 0 becomes the input of the NAND gate 60 and is connected to the output of the latch 40. The remaining inputs of the AND gate 52 receive a switching signal between the normal state and the external clock input state from the switching terminal 8. The outputs of the AND gates 52, 51 are respectively input to the OR gate 53, and the output of the OR gate 53 is the system clock within the integrated circuit.

In the normal state, the latch 40 holds the content for selecting which signal of the oscillation circuit 10 or 20 is used as the system clock, but the rewriting part for this content is not shown.
performed by other parts of the integrated circuit.

The switching signal between the normal state and the external clock is generated in other parts (not shown) of the integrated circuit, and includes the gate inputs of the transmission gates 11 and 21 and the AND gates 52 and N
The signal is input to an AND gate 60 and an inverter 70, and the output of the inverter 70 is input to the gate of a transmission gate 80.

In this circuit, in a normal state, the switching signal is at a high level, and the transmission gates 11 and 21 are in a conductive state. Further, the switching signal is inverted by the inverter 70, and the transmission gate 80 is in a disconnected state.

When an oscillator is connected between the oscillator connection terminals 1 and 2 and between the terminals 3 and 4 in this state, each oscillation circuit 10.21 starts oscillating at a frequency corresponding to the oscillator. Now latch 4
When the output of 0 is at high level, both inputs of NAND60 are at high level, the output of NAND60 is at low level, one output of AND51 is at low level, and the signal of oscillation circuit 10 is not input to OR gate 52.

Further, since the other input of AND52 is at a high level, the oscillation signal of the oscillation circuit 20 is ORed from the output of AND52.
53 serves as the system clock. Also, latch 4
When the output of 0 is low level, the output of AND52 is fixed to low level and the output of NAND60 is fixed to high level, so the signal of oscillation circuit 10 is ORed with AND51.
53 as the system clock.

Furthermore, the switching timing of the latch 40 is determined by both oscillators 10 and 2.
0 signal rise. Although it is necessary to perform this in synchronization with the falling switching, the explanation will be omitted since it is not directly related.

Now, when using an external signal as a system clock, the switching signal becomes low level. As a result, transmission gates 11 and 21 become disconnected and the NAN
The output of the D gate 60 is fixed at high level, and the output of AND52 is fixed at low level. Therefore, the oscillator connection terminal 2
The external clock from the system passes through the OR gate 53 and becomes the system clock. Further, since the output of the inverter 70 becomes high level, the output of the latch 40 is outputted from the oscillator connection terminal 4 through the transmission gate 80.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. This embodiment differs from the first embodiment in that the third oscillator circuit 30
, the oscillator connection terminals 5, 6, transmission gates 31, 81, latch 41, decoder 90, and AND gate 53 are added, and the OR gate 54 becomes a three-person gate, and the output of the AND gate 53 is inserted. The outputs of the latch 40 and the latch 41 are decoded by the decoder 90, and the decoded output is used to perform AND51.52.5.
The point is that any one of 3 is selectively valid.

In this embodiment, a 2-bit latch is required to select the oscillation circuits 10 to 30, and the information can be output from the oscillator connection terminals 4 and 6, respectively. [Effects of the Invention] As explained above, the present invention provides means for forcibly prohibiting internal clock switching in an integrated circuit that uses one of a plurality of oscillation circuits as a system clock depending on the internal operating state;
By adding a means to output the clock switching state to the outside, it is possible to perform synchronized operation with other chips using an externally supplied clock without using the built-in oscillation circuit, and also to output the internal clock switching state. Since it is outputted to the outside, it has the advantage that it is also possible to use this to change the frequency of the clock supplied from the outside.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of first and second embodiments of the present invention. 1 to 6... Oscillator connection terminal, 7... Clock terminal,
8...Switching terminal, 10,20.30...Oscillation circuit,
11, 21, 31, 80.81...Transmission gate, 40.41...Latch, 51-53...
AND gate, 54...NOR gate, 60...N
AND gate, 70...inverter, 90...decoder.

Claims (1)

[Claims] a plurality of oscillation circuits, a selection register that holds which of the output signals of these oscillation circuits is to be selected, and a first gate that selects one of the oscillation signals and uses it as a system clock based on the contents of the selection register. a second gate means for selecting an output signal of a first oscillation circuit of the oscillation circuits as a system clock in accordance with a switching signal regardless of the contents of the selection register; and third gate means for outputting the contents of the selection register from an oscillator connection terminal of an oscillation circuit other than the first oscillation circuit in accordance with a signal.