JPH0329350B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a versatile audible signal tone generation system for systems using digital exchanges.

[Prior art] In a digital switching system, dial tones and
It is known to generate audible signals, such as ring tones, using read-only memory, as shown in FIG. In FIG. 6, 1 is a data ROM (read-only memory), 2 is an intermittent pattern ROM, 3 is a silent pattern data memory, 4 is a frame counter,
5 is a time slot counter, 6 is a synchronization detector,
7 indicates a selector, and 8 indicates a damping pad. The data ROM 1 stores in advance sampling data of required signal frequencies for each frequency and for several cycles. The number of periods is determined by the greatest common divisor of the generated signal frequencies. Data of a desired frequency is generated for a time determined by a time slot counter 5, and audible signal interruptions are created according to a predetermined intermittent pattern, and the silent pattern data memory 3 is controlled to be read. Further, a pad 8 provided on the output side provides desired attenuation. At this time, all data corresponding to each frequency and operating time are prepared, so it can be used without malfunction.

[Problems to be solved by the invention] However, it is natural that the initial preparations will be complicated. In particular, attenuation pads 8 must be provided in large quantities to provide a predetermined amount of attenuation for a predetermined style of audible signal. Therefore, if the specifications of the audible signal tone (frequency, level, repetition period) are even slightly different, there is no flexibility to change the specifications, so data ROM 1 and intermittent pattern are changed each time.
It becomes necessary to change the design of ROM2. There were some drawbacks that would be troublesome due to regulatory revisions or when exporting to neighboring countries.

[Means for Solving the Problems] The means adopted by the present invention to solve the above-mentioned problems is a frequency/level method in which amplitude data of two consecutive sample points and frequency data for audible signals are stored in advance. a specified data memory; a digital signal processor that calculates the amplitude data of the next sample point by calculating the data read from the memory; an intermittent cycle specification data memory that stores in advance data specifying a predetermined intermittent cycle; and the signal processor. and a data storage memory for storing output/silence data, and the data storage memory output is controlled by the intermittent period designated data memory output to generate an audible signal tone.

[Function] Rather than reading data stored in memory and directly outputting it, the arithmetic unit constantly performs high-speed calculation processing and generates an audible signal sound, so even if specifications need to be changed. Since the output is affected only by correcting the original data using a typewriter or the like, a versatile device can be easily obtained.

[Embodiment] FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, numeral 9 generally indicates a digital signal processor that performs arithmetic processing. 10 is a typewriter for data setting, 11 is a data memory for specifying frequency and level, 12 is a data memory for specifying intermittent period, 13 is a first signal delay buffer, 14 is a second signal delay buffer, 15 is a first signal Adder, 16 is a second signal adder, 17 is a third signal adder, 18 is a timing time counting RAM, 1
9 is a time slot designation data RAM, 20 is an output data storage RAM, 21 is a multiplier, and 22 is a first
Buffer for addition, 23 is second buffer for addition, 2
4 indicates a PCM conversion circuit, and 25 indicates a comparison circuit. The typewriter 10 sets the frequency and level for the data memory 11 as shown in FIG. 2, and sets the intermittent time for the data memory 12. In FIG. 2, three pieces of data, that is, frequency data, first and second initial amplitude data for level setting, are prepared for one time slot, and the output is a mixed wave of the three data.

Frequency data 2 cosωT where ω is the output angular frequency T = 1/8000 seconds First initial amplitude data 0 or A Second initial amplitude data A sinωT or A
cosωT Here, A is amplitude binary data. For each amplitude data when it is a sine function, use the combination of 0, A sinωT, and when it is a cosine function, use the combination of A, A cosωT. Prepare three data for one time slot. This is to obtain a two-frequency mixed output and an amplitude modulated output. Therefore, when outputting a single frequency, predetermined data is written into the data memory 11 only at the first address, and "0" is written into the second and third addresses.

When obtaining a two-frequency mixed output, Insert the specified data into the first and second addresses. Write “0” to the third address.

Generally, an amplitude modulated signal can be expressed as a sum of three frequency signals.

A (1 + η sinω _n nT) sinω _c nT = A sinω _c nT + A/2η cos (ω _c − ω _n ) nT − A/2η cos (ω _c + ω _n ) nT Therefore, the frequency data is 2 in the first address. cosω _c T The first initial amplitude data is 0 The second initial amplitude data is A sinω _c T The second address has the frequency data 2 cos(ω _c −ω _n )T The first initial amplitude data is ηA/2 The second initial The amplitude data is A/2η cos (ω _c −ω _n )T The third address has frequency data 2 cos (ω _c +ω _n )T The first initial amplitude data is −ηA/2 The second initial amplitude data is −A /2η・cos(ω _c +ω _n )
It becomes T.

In general, the amplitude value of a sine function can be calculated when two pieces of data from a previous sampling period are known. The calculation formula is A(n)=A(n-1)・2cosω T-A(n-2)... (1) where A(n): Amplitude data at sampling time n ω: Output sine/cosine wave angle Frequency T: Sampling period 1/8000 seconds Next, since the method for calculating the amplitude value of the cosine function is the same as the method for calculating the amplitude value of the sine function, it will be explained below. In other words, the amplitude value of the cosine function is the amplitude value obtained by delaying the phase of the sine function of the same frequency by 90 degrees. For example, the amplitude value of the second address is (A/2)η・cos(ω _c −ω _n )nT= (A/2) η・sin [(ω _c − ω _n )nT+90°]… (2) Therefore, the amplitude value of the above cosine function is obtained by converting the sine function converted into equation (2) using equation (1). All you have to do is calculate the amplitude value.

For example, the first and second initial amplitude data at the second address are calculated as follows.

The data for the first amplitude value is when n=0 in the above equation, and the data for the second amplitude value is when n=1 in the above equation. Yes (A/2) η sin [ω _c − ω _n ) T + 90°] = (A/2) η cos [ω _c − ω _n ) T] Similarly, the cosine function at the third address is converted to the form of a sine function. calculated.

−(A/2)ηcos( _ωc − _ωn )nT =−(A/2)ηsin[( _ωc + _ωn )nT+90°] The data of the first amplitude value is when n=0, −( A/2) η sin (0 + 90°) = - (A/2) η The data of the second amplitude value is when n = 1, - (A/2) η sin [(ω _c + ω _n ) T + 90°] = −(A/2)η cos [(ω _c +ω _n )T] At the start of the operation shown in FIG. The buffer 13 and the second delay buffer 14 are written.

As shown in FIG. 3, for example, first address signal amplitude data, second address signal amplitude data, and third address signal amplitude data for time slot 0 are written into each delay buffer at addresses 0 to 2 of the buffer, respectively. The content corresponding to each time slot of the buffer is the sampling period.
Updated every 125 microseconds.

The output A(n-1) of the second delay buffer 14 is multiplied by the frequency data (2 cosωT) read from the designated data memory 11 in the multiplier 21,
Next, in the first adder 15, the first delay buffer 1
The output data A(n-2) of 3 is subtracted. Since this value becomes A(n) and is the amplitude data at the time of sampling, it is output to the next stage and simultaneously stored at the corresponding address of the second delay buffer 14.
Data A(n-1) at the write address of the second delay buffer 14 is stored in the corresponding address of the first delay buffer 13 (the data at the write address of the first delay buffer 13 has disappeared).

Next, data of amplitude A(n) is applied to a stage for obtaining a mixed output/modulated output. The stage includes a first addition buffer 22, a second addition buffer 23, and an adder 16.
It inputs the output amplitude data of the first adder 15. When the third corresponding data is output to the second adder 15, the first address corresponding data is output to the second addition buffer 23, the second address corresponding data is output to the first addition buffer 22, and the third corresponding data is output to the first adder 15. 16 to obtain a three-frequency mixed output. Next, the signal is applied to the PCM conversion circuit 24 in order to obtain non-linear code data for PCM encoding as required.

On the other hand, the output frequency and intermittent cycle signal for each time slot of output data are written in advance in the intermittent cycle designation data memory 12 using a typewriter 10 or the like. Fig. 4 shows an example of its accommodation. In FIG. 4, the number of multiplexed output data is 32, and the number of signal interruptions per time slot is up to eight. That is, 16 consecutive addresses in the memory 12 correspond to control data for one time slot, and there are three control data contents, one of which is the designation of the frequency and level signal to be output, that is, the designation of the signal generation time slot number. I do. However, when specifying silence, a fixed address different from the generator is specified. For other data contents, set the intermittent time (signal on time or intermittent time setting), and set the intermittent time to 1mS.
The value of n at time indicated by xn is written. Regarding the content of the remaining data, the address containing the data to be output next is set when the above-mentioned setting time ends. In the example in Figure 4, the output time slot is 0.
is a continuous signal output, but in this case, the address where the data is stored is written in the data section. In the case of intermittent time slot 5, the number of the next address is written. In the last address data of the cycle, the number of the first address of this time slot is written. These data are read at the start address of each output time slot at the time of initial setting and written into the timing time counting memory 18 and the time slot designation data memory 19 in the digital signal processor 9. FIG. 5 shows a data storage diagram in each memory. Each memory 18, 19 is updated, for example, every 1 msec.
Periodic time data every 1 msec and next pattern address data are read from the timing time counting memory 18, and the former data is subjected to a calculation of -1 in the third adder 17, and the comparison circuit 25 determines whether the output is zero.
Judge by. If it is not zero, the subtracted output data is written to the address of the corresponding time slot in the memory 18 again. If zero is detected, the intermittent cycle specification data memory 12 is accessed using the next pattern address data, the data of the next pattern is read out, and the two memories 18 and 1 on the signal processor 9 side are accessed.
Rewrite the corresponding address in 9.

On the other hand, the data of the time slot designation data 19 is read periodically every 125 microseconds and is used as a read address of the data storage memory 20 (accommodating the silent pattern). The data storage memory 20 is
The output data of the PCM conversion circuit 24 is written in the order of the generation time slot numbers at a cycle of 125μ.
The output address designation information of the time slot designation data memory 19 enables the output of digital audible signal tone data.

[Effect of the invention] In this way, according to the present invention, amplitude data and
Since the signal processor starts operation after the signal frequency data and intermittent period are set in advance, the generated signal frequency and intermittent period can be easily set at the beginning. Therefore, there is flexibility in generating an audible signal, and there is an effect that the use of a pad for adjusting the output level can be omitted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing data setting to the frequency/level designation data memory in FIG. 1, and FIG.
Diagram 4 showing data setting to the delay buffer in the figure.
Figure 1 shows the data setting to the interrupted period data memory, Figure 5 shows the data setting to the timing time counting memory and time slot designation memory, and Figure 6 shows the conventional audible signal generation method. FIG. 9...Signal processor for performing arithmetic processing, 10...Typewriter, 11...Frequency/level setting data memory, 12...Intermittent cycle setting data memory, 18...
Tamming time counting memory, 19...time slot designation data memory, 20...output data storage memory.

Claims (1)

[Scope of Claims] 1. A frequency converter in which amplitude data of two consecutive sample points and frequency data for an audible signal are stored in advance.
a level designation data memory; a digital signal processor that calculates the amplitude data of the next sample point by calculating the data read from the memory; an intermittent cycle designation data memory that stores in advance data designating a predetermined continuation cycle; and the signal A digital audible signal sound generation method, comprising: a data storage memory for storing processor output/silent data, and generating an audible signal sound by controlling the data storage memory output by the intermittent period specified data memory output. .