JPH0334309B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital servo device that controls the rotation system of a magnetic recording and reproducing device.

Generally, in a magnetic recording/reproducing device such as a VTR, automatic frequency control means, automatic phase control means, etc. are provided in order to smoothly and stably rotate a rotating system such as an electric motor. Servo devices that control the rotation system of magnetic recording and reproducing devices, including these means, are increasingly becoming digital, and digital quantities such as pulse width modulation signals are used for control output.

The applicant previously filed the patent application No. 55-89227.
An application was filed for a digital servo device as shown in FIG. In FIG. 1, 1 is a controlled object such as a rotating body, 2 is a waveform shaping circuit, 3 is a control signal generation circuit that generates gate signals and latch signals, 4 is an AND gate, 5 is a detection counter, 6 is a latch circuit, 7 is a pulse width modulation circuit, 8 is a reference counter, 11 is a low-pass filter, 12 is a drive circuit 14 is a trigger signal generation circuit that generates a trigger signal at a predetermined count value of the detection counter 5, and 17 is synchronized with the trigger signal. This is a switch signal generation circuit that generates a switch signal.

Next, the operation of the conventional device having the above configuration will be described in the first section.
This will be explained with reference to FIG. 2, which shows the waveforms of the main parts of the figure. First, the controlled signal a obtained from the controlled object 1
passes through the waveform shaping circuit 2 and becomes the comparison signal b,
The signal is input to the transfer signal generation circuit 3. The transfer signal generation circuit 3 detects the phase difference between the reference signal c as shown in FIG. 1 and the comparison signal b as shown in FIG. A corresponding clock gate signal d and latch signal f are output.

This clock gate signal d is input to the AND gate 4, which gates the clock signal e input to the detection counter 5. As a result, the detection counter 5
counts the clock signal e only during the period of the clock gate signal d whose pulse width corresponds to the phase difference between the signal c and the signal b. After that, when the clock gate signal d becomes low level and the AND gate 4 closes,
Latch signal f output from control signal generation circuit 3
As a result, the count information of the detection counter 5 is transferred to the latch circuit 6 and held there.

When the latch signal f is output, the clock gate signal d is again turned on, as shown in FIG.
Open the AND gate 4 and input the clock signal e to the detection counter 5. For example, when the count value reaches a predetermined value, the detection counter 5
When the most significant digit and the next digit become "1", "1" and the two inputs of AND gate 4' become "1", "1", AND gate 4 is automatically closed and clock signal e is turned off. Prohibit input.

Here, the information held in the latch circuit 6 is stored in the pulse width modulation circuit 7 along with the information in the reference counter 8.
is input. The pulse width modulation circuit 7 generates a pulse width modulation signal (hereinafter abbreviated as PWM signal) as shown in FIG. Output g. This PWM signal g controls and drives the controlled object 1 which is input to the drive circuit 12 via the next-stage low-pass filter 11.

Here, as shown in FIG. 2A, when the comparison signal b is at a predetermined phase with respect to the reference phase signal c, the duty of the PWM signal g is set to 50%.

Next, the operation when the phase of the controlled object 1 differs from a predetermined phase will be explained. Assume now that the phase of the controlled object 1, that is, the phase of the comparison signal b, has advanced as shown in FIG. 2B. Then, the gate width of the clock gate signal d becomes smaller, and the number of clocks input to the detection counter 5 becomes smaller. Therefore, the count value of the detection counter 5 becomes smaller than the predetermined value, and the information held in the latch circuit 6 also becomes smaller than the predetermined count value.

Therefore, the output of the pulse width modulation circuit 7 is
The PWM signal g becomes a signal with a small duty, like the signal g in state B in FIG. For this reason, the DC voltage output from the low-pass filter 11 becomes lower than a predetermined value, and the phase of the controlled object 1 is delayed so that it becomes the predetermined phase.

Similarly, if the phase of the controlled object 1 lags behind the predetermined phase, the operations of the above-mentioned parts will be in the opposite direction. As a result, the duty of the PWM signal g increases, and the phase of the controlled object 1 is advanced.

Here, the configurations and operations of the control signal generation circuit 3, pulse width modulation circuit 7, and switch signal generation circuit 17 will be sequentially explained.

First, the control signal generation circuit 3 will be explained.
A comparison signal b, a reference signal c, and a clock signal j are inputted to the control signal generation circuit 3.

The control signal generating circuit 3 generates a clock gate signal d having a pulse width proportional to the phase difference between the comparison signal b and the reference signal c, and inputs the clock signal e to the detection counter 5 via the AND gate 4. When the AND gate 4 closes after the clock signal e has been input for a period of pulse width proportional to the phase difference, the clock input to the detection counter 5 is stopped and the information is maintained. The setting of this stop period is determined by the clock signal j. During this stop period, the latch signal f is output, and the information of the detection counter 5 is transferred to the latch circuit 6 and held there.

After the latch signal f is output, the clock gate signal d becomes "H" again, and the clock signal e is input to the detection counter 5. In other words, the detection counter 5 temporarily stops counting after counting the phase difference information between the comparison signal b and the reference signal c, and after the latch signal f is generated,
Start counting again. The reason why the operation of the detection counter 5 is temporarily stopped when the latch signal f is generated is that the information of the detection counter 5 is accurately transferred to the latch circuit 6 by the latch signal f.

Note that the detailed configuration of the transfer signal generation circuit will be described in the description of the embodiments of the present invention, so the description will be omitted here.

Next, the pulse width modulation circuit 7 will be explained.
The information of the latch circuit 6 and the information of the reference counter 8 are respectively input to the pulse width modulation circuit 7, and exclusive OR gates 9a ₁ to 9 are input for each corresponding bit.
The exclusive disjunction group consisting of a _o (hereinafter Ex−
(abbreviated as OR group) 9 or a detection circuit with a similar logical configuration. The outputs of these Ex-OR groups 9 are all input to a NOR gate 10, and the output thereof is input as a coincidence signal h to a reset terminal R of a T-type flip-flop (hereinafter abbreviated as T-FF) 13. On the other hand, bit Qn of the reference counter 8 is used as the T input signal i of the T-FF 13.

In the pulse width modulation circuit 7 having the above configuration, the output of the T-FF 13, that is, the PWM signal g
is inverted to "H" at the falling edge of the output Qn of the reference counter 8, and becomes "L" at the coincidence signal h from the NOR gate 10.

As described above, the pulse width modulation circuit 7 compares the information of the latch circuit 6 with each bit output of the reference counter 8, and determines the pulse width corresponding to the frequency of the reference counter 8 and according to the latch information.
PWM signal g is output. In addition, PWM signal g
The frequency of is determined by the frequency of bit Qn of the reference counter 8.

Finally, the switch signal generation circuit 17 will be explained. Generally, after a predetermined period of time has elapsed after the detection counter 5 has started, or after a predetermined number of clock signals e.
After inputting the switch signal p, it is necessary to invert the switch signal p. For example, in VTR drum motor control, this switch signal p is required as a video head switching signal.

Now, in the switch signal generation circuit 17, each bit output of the detection counter 5 is input to the trigger signal generation circuit 14, and a group of gates inside the circuit causes the trigger signal k to be generated at a predetermined timing after the input of the clock signal e. occurs in Usually, the signal k is
It is generated shortly after the input of the clock signal e, and the second
As is clear from comparing signals k and d in FIGS. 5 and 3, they are generated at a timing sufficiently earlier than the time at which the detection counter 5 stops.

However, when a large load fluctuation is applied, the phase difference between signal b and signal c changes, and the period during which the detection counter 5 is stopped in order to transfer the contents of the detection counter 5 to the latch circuit 6 becomes as shown in FIG. As shown in c, the timing may be earlier than the generation timing of the trigger signal k. In this case, the trigger signal k will be generated with a delay of this stop period (period T ₁ in FIG. 3). Normally, this stop period T ₁ is much longer than the period after the detection counter 5 starts counting until the signal k is output (period T ₂ in FIG. 3). For this reason, the signal k is generated much later than the normal timing, and when the switch signal p is generated by the signal k, the phase of the switch signal p will vary greatly by that amount.

In particular, if the stop timing of the detection counter 5 for generating the latch signal f fluctuates by a slight difference from the original generation timing of the signal k, the timing of the inversion of the switch signal p may be different from the normal timing. The timing may be delayed by the period during which the detection counter 5 is stopped. Therefore, when this switch signal p is used as a video head switching signal, the head switching timing is determined by the above-mentioned signal k.
The problem was that the screen fluctuated greatly depending on the timing of occurrence of the problem, resulting in a screen that was very hard to see.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital servo device that eliminates the above-mentioned drawbacks of the prior art and can supply stable switch signals.

In a digital servo device, the present invention provides a trigger signal that is output when the count of a digital detector that outputs a digital signal corresponding to an error from a target value of a controlled object reaches a predetermined value as an input of a switch signal generation circuit. and a logical sum signal of the digital detector stop signal when the latch signal is generated, and in the state where the stop signal is output earlier than the trigger signal obtained from the information of the digital detector, the switch signal generating circuit The present invention is characterized in that the stop signal is used instead of the trigger signal as an input.

An embodiment of the present invention will be described below with reference to FIG. In Figure 4, 15 is an OR gate, 16 is
RS type flip-flop (hereinafter abbreviated as RS-FF)
, and the other symbols are the same as those in FIG. 1 or have the same functions. Further, FIG. 5 shows the main waveforms of FIG. 4.

Before explaining the operation of this embodiment, the control signal generating circuit 3 will first be explained with reference to FIGS. 6 and 7. FIG. 6 shows a specific example of the control signal generation circuit 3, and FIG. 7 shows waveforms of its main parts. In Figure 6, 21, 22, 23 and 24 are T-FF
These T-FFs are triggered by the falling edge of the signal input to the trigger terminal T.

Now, if comparison signal b and reference signal c as shown in FIG. 4 1 and 2 are input to the AND gate 25, the output v of the AND gate 25 corresponds to the phase difference between the two as shown in FIG. 7 3. The result is a signal with a pulse width. On the other hand, when the clock signal j shown in FIG. 4 is input to one input terminal of the AND gate 26, the T-FFs 21 to 23 are triggered by the falling edge of the T input signal, and the respective Q terminal outputs are , 6, and 7.

Therefore, from the control signal generation circuit 3, as shown in FIG.
The clock gate signal d output to the AND gate 4 has a waveform as shown in FIG. 7. That is, after a signal having a pulse width corresponding to the phase difference between the comparison signal b and the reference signal c is output, the detection counter 5 is clocked for a certain period of time in order to latch the contents of the detection counter 5 in the latch circuit 6. Signal e is prevented from being captured. After this fixed stop period has passed, the clock gate signal d becomes "H" again, and the detection counter 5 begins to receive the clock signal e.

Further, the stop signal l outputted from the control signal generation circuit 3 to the OR gate 15 in FIG. 4 has a waveform as shown in FIG. 7, and corresponds to the "L" period of the clock gate signal d, that is, This signal is at the "H" level only during the stop period in which the detection counter 5 stops receiving the clock signal e. Furthermore, the latch signal f used to latch the contents of the detection counter 5 to the latch circuit 6 is as follows:
The waveform becomes as shown in FIG. 7 and 11. Since the latch circuit 6 is latched at the falling edge of the latch signal f, the contents of the detection counter 5 are latched into the latch circuit 6 exactly during the "L" period of the signal d, that is, during the stop period. .

Next, the operation of this embodiment will be explained with reference to FIGS. 4 and 5. In this embodiment, except for the switch signal generation circuit 17, both the configuration and the operation are the same as those of the conventional example shown in FIG. I will explain.

As shown in FIG. 5, the trigger signal generating circuit 14 immediately outputs the trigger signal k when the clock gate signal d becomes "H" level and the clock signal e starts to be input to the detection counter 5. do. Furthermore, as described above, the transfer signal generating circuit 3 outputs the stop signal l which is at the "H" level only during the period when the detection counter 5 is stopped. These signals k and l are input to the OR gate 15, and the output m of the OR gate 15 shown in FIG.
Input to the R (reset) terminal of 6. On the other hand, RS−
The S (set) terminal of the FF16 receives a signal n having a predetermined phase difference from the signal b output from the waveform shaping circuit 2.
enters.

Therefore, under normal conditions, that is, when the timing of the generation of the trigger signal k is earlier than the start of the stop period of the detection counter 5, as shown in FIG.
The RS-FF 16 operates as follows. First of all,
When the trigger signal k passed through the OR gate 15 is input to the R terminal of the RS-FF 16, the RS-FF 16 is reset. Next, the stop signal l is sent to the OR gate 15.
It is input to the R terminal of RS-FF16 through
Since RS-FF16 has already been reset,
It remains reset. Then, the comparison signal b
A signal n with a predetermined phase delay is input to the reset terminal of the RS-FF 16. By this, RS−FF
16 is set. The above steps are repeated. Therefore, the RS-FF 16 outputs a switch signal p controlled by the trigger signal k and signal n as shown in FIG.

Next, the latch phase changes due to changes in the load, etc., and as shown in E in FIG. , the case where the rise of the stop signal l is earlier than the rise of the trigger signal k will be explained. In this case, RS-FF1 is set by inputting the signal n to the S terminal.
6 is reset by the rise of the stop signal l input to the R terminal at a timing earlier than the trigger signal k. Trigger signal k is later than stop signal l RS
Since it is input to the R terminal of the -FF 16, when the trigger signal k is input to the R terminal, the RS-FF 16 has already been reset by the rise of the stop signal l.

Therefore, the switch signal p, which is the Q output of the RS-FF 16, is controlled by the stop signal l and the signal n.

Incidentally, when transitioning from state D to state E in FIG. 5, the rise of signal m as the R terminal input of the RS-FF 16 smoothly transitions from trigger signal k to stop signal l. That is, in normal state D, the RS-FF 16 is reset at the rising edge of trigger signal k, and in abnormal state E, RS-FF16 is reset.
The reset of the FF 16 is performed at the rising edge of the stop signal 1, but the switching from the signal k to 1 is performed immediately after the rising edge of the trigger signal k and the rising edge of the stop signal 1 coincide with each other, so that it is performed smoothly.

Therefore, according to this embodiment, even if the start of stopping of the detection counter 5 is slightly before or after the generation timing of the trigger signal k, the switch signal p
A stable switch signal p can be supplied to the video head as a head switching signal, for example, since the rising edge of the switch signal p does not fluctuate greatly.

As described above, according to the present invention, even if the timing at which the detection counter stops when a latch signal is generated is earlier than the trigger signal output based on the information of the detection counter, there is no large fluctuation in the switch signal. This has the great effect of providing a stable digital servo device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital servo device in the prior art, FIGS. 2 and 3 are waveform diagrams of main parts for explaining the operation of FIG. 1, and FIG. 4 is an embodiment of the present invention. 5 is a waveform diagram of the main part of FIG. 4, FIG. 6 is a block diagram showing a specific example of the control signal generation circuit, and FIG. 7 is a waveform diagram of the main part of FIG. 3... Control signal generation circuit, 5... Detection counter, 6
... Latch circuit, 7... Pulse width modulation circuit, 14... Trigger signal generation circuit, 17... Switch signal generation circuit.

Claims (1)

[Claims] 1. A controlled object 1 that generates a comparison signal whose phase fluctuates at a predetermined frequency, and a control system that suppresses phase fluctuations of the controlled object by comparing the phases of the comparison signal and a reference signal. , a switch signal generation circuit that generates a switch signal for the video head, and the control system includes a reference counter 8 that counts clocks whose frequency is sufficiently higher than the reference signal, and a gate that is opened and closed in response to a gate signal. circuit 4
and a detection counter 5 that counts the clocks supplied via a gate circuit; the gate circuit is opened when the reference signal arrives, closed when the comparison signal arrives, and after a predetermined period of time has elapsed. a gate signal generating circuit 3 that generates a gate signal that opens the gate again and closes the gate again until the next reference signal arrives when the detection counter counts up to the maximum value; and the predetermined period of time during which the gate circuit remains closed. During this period, a latch circuit 6 latches the count value of the detection counter when the comparison signal arrives, and compares the count value latched in the latch circuit with the count value of the reference counter, and determines that the two count values match. It consists of a pulse width modulation circuit 7 that generates a pulse width modulation signal having a predetermined pulse width, and a drive circuit 12 that drives the controlled object according to the pulse width modulation signal, and the switch signal generation circuit generates the comparison signal. The pulse l generated in response to the occurrence of
and a pulse k generated when the detection counter counts a predetermined value smaller than the maximum value thereof; a first terminal to which the output m of the OR circuit is supplied; and a second terminal to which a signal n with a phase delay of A digital servo device comprising a flip-flop 16.