JPH0347731B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing electrodes of semiconductor devices, particularly high frequency transistors.

Recently, the characteristics of high-frequency transistors are
There is a growing demand for higher frequency bands and higher outputs. In order to satisfy this requirement, the shape and spacing of each impurity region and each electrode layer of the emitter and base of a high frequency transistor must be formed precisely and minutely. Therefore, if a self-alignment method is used to form each impurity region and each electrode layer, the problem of deviation from design dimensions due to mask alignment and processing in each photo-etching process will be eliminated, which is advantageous. Furthermore, if the spacing between each electrode layer is determined in the vertical direction with respect to the semiconductor surface, the spacing between each impurity region can be designed to be very small, resulting in good high frequency characteristics. As a conventional technology having such a structure, as a stepped electrode transistor,
For example, it is disclosed in Japanese Patent Application Laid-Open No. 50-34485. This is a structure that has an inverted trapezoidal polycrystalline silicon layer on the emitter region.The emitter region is determined from the position and size of the bottom of this inverted trapezoid, and The distance between the emitter region and the base electrode is determined from the relative relationship with the position projected in the direction. However, because of the structure in which the formation of each region depends on the shape of such inverted trapezoidal polycrystalline silicon, the technique for forming the emitter and base electrode layers has generally been to deposit electrode metal from the vertical top surface. As a result, multilayer electrodes (Ti-Pt-Au Ti-W-Au, etc.) have been used when extremely high reliability is required; ) is large, electrode metals (Pt and Au) invade the polycrystalline Si layer at high temperatures, resulting in deterioration of electrical characteristics. In this way, it has been difficult to obtain sufficient heat resistance.

The present invention was developed in view of the above points, and uses a dense transition metal nitride layer, for example, a Ti nitride layer as the lower layer, to suppress the penetration of electrode metal into the polycrystalline Si layer. The present invention aims to provide a novel method for manufacturing a stepped electrode transistor.

According to the present invention, a step of forming a base region of another conductivity type in a semiconductor region of one conductivity type, a step of forming a base region of another conductivity type in a semiconductor region of one conductivity type, and a step of forming an impurity exhibiting one conductivity type in a part of the base region and a step of forming a polycrystalline silicon layer having a shape in which the bottom surface is completely within the top surface, that is, an inverted trapezoidal shape; a step of introducing impurities into the base region from this polycrystalline silicon layer to form an emitter region; forming resistive contact metals separated from each other on each surface of the region;
forming a titanium layer on the resistive contact metal; forming a nitride of a transition metal such as titanium, tungsten, molybdenum, or chromium on the titanium layer; and forming a conductive metal on top of the nitride. A method for manufacturing a semiconductor device is obtained.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to better understand the present invention, an example of a method for manufacturing a transistor to which the present invention is applied will be described below with reference to the accompanying drawings, while comparing it with a conventional method.

FIG. 1 is a cross-sectional view of a stepped electrode transistor when a conventional manufacturing method is applied. In the figure, a semiconductor substrate 1 has a base contact region 7 and an active base region 3 having a conductivity type opposite to that of the semiconductor substrate 1 . The emitter region 5 of the same conductivity type as the semiconductor substrate 1 formed in the active base region 3 contains impurities of the same conductivity type as the semiconductor substrate 1,
It is formed by diffusing impurities from a polycrystalline silicon layer 4 processed into an inverted trapezoidal shape. Further, the side surface of the inverted trapezoidal polycrystalline silicon layer 4 and the surface of the base region 3 near the side surface are protected by an insulating layer 6. An ohmic contact 8 made of Pt silicide or the like is formed on the surface of the contact region 7 and the polycrystalline silicon layer 4, and an electrode metal (Ti9
−Pt10−Au11) is evaporated from the vertical upper surface direction,
An emitter 12 and a base electrode 13 having a multilayer structure are provided. Note that 2 is a silicon oxide film for surface protection.

Although such a transistor has a fine electrode structure, it has the disadvantage that Au11 and Pt10 tend to diffuse into the polycrystalline silicon layer 4 through Ti9 in a high-temperature environment, so that the electrical characteristics tend to change.

On the other hand, FIGS. 2 and 3 are cross-sectional views showing the case where the present invention is applied to a stepped electrode transistor in the order of manufacturing steps.

First, as shown in FIG. 2, a P-type active base region 3 is formed in an n-type semiconductor substrate 1 by impurity diffusion or the like in the same manner as in the conventional manufacturing method. A P ⁺ type base contact region 7 is formed around the active base region 3 . Further, in the center of the active base region 3, a polycrystalline silicon layer 4 containing n-type impurities is formed in the shape of an inverted trapezoid. The side surfaces of this inverted trapezoidal polycrystalline silicon layer 4 are oxidized together with the surface of active base region 3 to form an insulating layer 6 made of oxide. This insulating layer 6 is removed from the upper surface of the polycrystalline silicon layer 4 and from the surface of the base contact region 7. Thereafter, platinum silicide 8 is formed in resistive contact with the upper surface of polycrystalline silicon layer 4 and the surface of base contact region 7 through the steps of depositing platinum, alloying it, and removing remaining platinum. Thereafter, Ti layer 9 is formed by depositing Ti almost vertically from the upper surface. Due to the inverted trapezoidal shape of the polycrystalline silicon layer 4, this Ti layer 9 has
The regions on polycrystalline silicon layer 4 and other regions are separated. Next, a Ti nitride layer 14 is formed by reactive sputtering in an atmosphere containing nitrogen. The sputtering conditions may be, for example, sputtering in a pressure atmosphere of a 30 mm tool containing nitrogen and argon in a ratio of 1:5. after that,
Again, Pt10 and Au11 are continuously deposited almost vertically from the top surface. This connected vapor deposition also separates Pt10 and Au11 on the polycrystalline silicon layer 4 from other parts.

Next, as shown in FIG.
Remove by etching with a hydrogen peroxide mixture. In this way, the emitter electrode 12 and base electrode 13 having a multilayer structure are separated.

As can be seen from the above manufacturing method examples, unlike the conventional manufacturing method, the transistor to which the present invention is applied,
Since the Ti nitride layer 14 is reactively sputtered between the Ti layer 9 and the Pt layer 10 as a diffusion barrier, even if the silicon crystal grains of the inverted trapezoidal polycrystalline silicon layer 4 are large, It has become possible to prevent the electrode metals (Pt9 and Au10) from penetrating into the polycrystalline silicon layer 4, and it has become possible to obtain the required sufficient reliability, especially in terms of heat resistance. This is due to the dense composition of Ti nitride.

In the above embodiments, a single transistor is used, but it goes without saying that the present invention can be similarly applied to diodes, integrated circuits, and the like.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional stepped electrode transistor having a polycrystalline silicon layer with an inverted trapezoidal structure formed on the emitter region, and FIG. 2 is a cross-sectional view of a stepped electrode transistor to which the present invention is applied. and
FIG. 3 is a cross-sectional view showing the manufacturing process before etching the Ti nitride, and FIG. 3 is a cross-sectional view showing the manufacturing process after etching the Ti nitride. 1...Semiconductor substrate, 2...Field oxide film,
3... Active base region, 4... High concentration polycrystalline silicon layer, 5... Emitter region, 6... Insulating layer, 7
... Base contact region, 8 ... Pt silicide layer, 9 ... Ti layer, 10 ... Pt layer, 11 ... Au
Layer 12... Emitter electrode, 13... Base electrode, 14... Ti nitride layer.

Claims (1)

[Claims] 1. Forming a first semiconductor region having a conductivity type opposite to that of the semiconductor substrate on one principal surface of the semiconductor substrate, and forming a part of the first semiconductor region having the same conductivity type as the semiconductor substrate. a step of forming a polycrystalline silicon layer containing impurities and having a bottom surface completely within the top surface when viewed from above; and introducing an impurity from the polycrystalline silicon layer into the first semiconductor region. forming a second semiconductor region within a first semiconductor region; first and second resistive contact metals separated from each other on respective surfaces of a predetermined portion of the first semiconductor region and an upper portion of the polycrystalline silicon layer; forming first and second titanium layers on the first and second resistive contact metals by depositing titanium substantially vertically from above, and an atmosphere containing nitrogen; a step of forming titanium nitride on the first and second titanium layers and between the first and second titanium layers by reactive sputtering in a wafer, and coating a conductive metal substantially vertically from above; forming first and second conductive metal layers on the titanium nitride on the first and second titanium layers, respectively; using the first layer as a mask.
and a step of selectively removing the titanium nitride formed between the second titanium layers.