JPH0356069Y2 - - Google Patents
Info
- Publication number
- JPH0356069Y2 JPH0356069Y2 JP17947685U JP17947685U JPH0356069Y2 JP H0356069 Y2 JPH0356069 Y2 JP H0356069Y2 JP 17947685 U JP17947685 U JP 17947685U JP 17947685 U JP17947685 U JP 17947685U JP H0356069 Y2 JPH0356069 Y2 JP H0356069Y2
- Authority
- JP
- Japan
- Prior art keywords
- alignment mark
- film carrier
- chip
- present
- hereinafter referred
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005476 soldering Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
(産業上の利用分野)
本考案はフイルムキヤリヤ(テープキヤリヤと
も呼ばれる)を用いた高密度多端子の表示パネル
駆動用のIC実装に関し、薄形化した表示パネル
を提供するものである。[Detailed description of the invention] (Field of industrial application) This invention relates to IC mounting for driving high-density multi-terminal display panels using a film carrier (also called a tape carrier), and provides a thinner display panel. It is something to do.
(従来の技術)
従来はプリント配線基板(以下PCDと呼ぶ)
とよばれる銅貼り積層板上にデユアル イン ラ
イン パツケージ(以下DIPと呼ぶ)やフラツト
パツク パツケージ(以下FPと呼ぶ)を全面
でハンダ付けしていた。このパツケージの中に
ICチツプが設けられていた。また、液晶デイス
プレイ(以下LCDと呼ぶ)、エレクトロ ルミネ
ツセンス デイスプレイ(以下ELと呼ぶ)、プラ
ズマ デイスプレイ(以下PDPと呼ぶ)等の表
示パネルとはフレキシブル プリント サーキツ
ト(以下EPCと呼ぶ)を用いてヒートシールや
ハンダ付けにより接合部を組み付けを行つてい
た。(Conventional technology) Conventionally, printed wiring boards (hereinafter referred to as PCD)
Dual-in-line packages (hereinafter referred to as DIP) and flat package packages (hereinafter referred to as FP) were soldered on the entire surface of copper-clad laminates called ``DIP''. inside this package
An IC chip was installed. In addition, display panels such as liquid crystal displays (hereinafter referred to as LCD), electroluminescent displays (hereinafter referred to as EL), and plasma displays (hereinafter referred to as PDP) are manufactured using flexible printed circuits (hereinafter referred to as EPC) such as heat seals or The joints were assembled by soldering.
(考案が解決しようとする問題点)
PCBは1〜2mmの比較的厚い樹脂板であり、
またDIPやEPもかなりの容積があるため表示パ
ネルの薄形化には限界があつた。フイルムキヤリ
ヤ方式が集積度が高く自動化にも有利ではある
が、保護膜を施したICチツプ自身の表示パネル
への固定が不完全であつた。また、ICチツプと
パネル基板間を接着剤にて固定する方法は、フイ
ルムキヤリヤとパネル基板の正確なアライメント
をすることが困難であつた。(Problem that the invention attempts to solve) PCB is a relatively thick resin board of 1 to 2 mm.
Furthermore, since DIP and EP have a considerable volume, there is a limit to how thin the display panel can be made. Although the film carrier method has a high degree of integration and is advantageous for automation, the IC chip itself, which has a protective film, is not fully fixed to the display panel. Further, in the method of fixing the IC chip and the panel substrate using adhesive, it is difficult to accurately align the film carrier and the panel substrate.
(問題を解決するための手段)
本考案は、ICチツプをインナーボンデイング
したフイルムキヤリヤのハンダを施したアライメ
ントマークと、メタライズされたパネル基板のア
ライメントマークとをハンダ付けすることによ
り、該フイルムキヤリヤをパネル基板に固定させ
た表示パネルである。(Means for Solving the Problem) The present invention solves the problem by soldering the soldered alignment marks of the film carrier on which the IC chip is inner-bonded and the alignment marks of the metalized panel board. This is a display panel with the rear fixed to the panel substrate.
(作用)
本考案は、表示パネルの製造において3本/mm
以上の集積化を可能とし、かつ、各電極からのリ
ード端子とアライメントマークとが同時にギヤン
グボンデイングできる点及びアライメントマーク
を含む点で接合している点やフイルムテープを使
用できる点等の有利な点も多く、これにより自動
化をきわめて容易とした。(Function) The present invention provides 3 lines/mm in the manufacturing of display panels.
The above integration is possible, and the lead terminals from each electrode and the alignment mark can be bonded together at the same time, they are joined at a point including the alignment mark, and film tape can be used. There are many features that make it extremely easy to automate.
(考案の詳述) 本考案を実施例とともに詳細に説明する。(Details of the idea) The present invention will be described in detail along with examples.
第1図はポリイミドのフイルム4に制御信号線
に相当する外部リード8、選択すべき画素電極に
接続される電極リード7及び前記外部リード8の
端子部6を斜めの並びで、またアラインメントマ
ーク10を2か所、さらにドライバーのICチツ
プ5を中央部にインナーボンデイングせしめた本
考案の一部を示すフイルムキヤリヤの模式図であ
る。本図では説明の為数を少なく描いているが実
際のリード線数は100本で、ギヤングボンデイン
グによりICチツプ5を積層した。また、ICチツ
プ5はエポキシ樹脂で保護した。さらに端子部
6、電極リード7の端部およびアライメントマー
ク10にはハンダメツキを施した。 FIG. 1 shows an external lead 8 corresponding to a control signal line, an electrode lead 7 connected to a pixel electrode to be selected, and a terminal portion 6 of the external lead 8 arranged diagonally on a polyimide film 4, and alignment marks 10. 2 is a schematic diagram showing a part of the present invention in which the IC chip 5 of the driver is inner bonded in two places and the driver's IC chip 5 is bonded in the center. In this figure, the number of lead wires is small for the sake of explanation, but the actual number of lead wires is 100, and IC chips 5 are stacked using giant bonding. Moreover, IC chip 5 was protected with epoxy resin. Further, the terminal portion 6, the end portion of the electrode lead 7, and the alignment mark 10 were solder-plated.
第2図は、本考案の実施状態を示した液晶の表
示パネルの片側半面の模式図である。表示電極板
2にはコモン電極を形成し、対向電極板1には有
効表示面3において透明電極にて各画素電極をパ
タニングし、該画素電極の端部9と制御信号線に
相当する共通信号線11,12,13,14,1
5,16,17,18、及び前記アライメントマ
ークと同様パターンにてアライメントマーク10
をAlとNiの2層構成にてメタライズした。第1
図にて説明したフイルムキヤリヤをアライメント
マークにて位置合わせし、端子部6、電極リード
7の端部9及びアライメントマーク10を同時に
ギヤングボンデイングした。これによりフイルム
キヤリヤのハンダでパネル基板とが接合し、本考
案の表示パネルを作成する事が出来た。 FIG. 2 is a schematic diagram of one half of a liquid crystal display panel showing an implementation state of the present invention. A common electrode is formed on the display electrode plate 2, and each pixel electrode is patterned with a transparent electrode on the effective display surface 3 on the counter electrode plate 1, and a common electrode corresponding to the end 9 of the pixel electrode and a control signal line is formed. Lines 11, 12, 13, 14, 1
5, 16, 17, 18, and alignment marks 10 in the same pattern as the above alignment marks.
was metalized with a two-layer structure of Al and Ni. 1st
The film carrier explained in the figure was aligned using alignment marks, and the terminal portion 6, the end portion 9 of the electrode lead 7, and the alignment mark 10 were simultaneously subjected to gang bonding. As a result, the film carrier was bonded to the panel substrate using solder, and the display panel of the present invention could be created.
(考案の効果)
本考案はフイルムキヤリヤの両端部を端子部等
で、中央部をアライメントマークにてハンダ付け
し、固定するためのフイルムキヤリヤが堅固に保
持でき信頼性を高めた。また一度にハンダ付けで
きるため、接着剤等による工程が不必要となり生
産性を向上できた。さらにフイルムキヤリヤ方式
の特長である高密度実装、テープキヤリヤを媒介
とした自動化が可能となつた。(Effects of the invention) In the present invention, both ends of the film carrier are soldered with terminals, etc., and the center part is soldered with an alignment mark, so that the film carrier for fixing can be firmly held and reliability is improved. Additionally, since soldering can be done in one step, processes using adhesives and the like are not required, improving productivity. Furthermore, high-density mounting, which is a feature of the film carrier method, and automation using the tape carrier became possible.
なお、本考案においてハンダ材料はメツキによ
りコーテイングしたがデイツピングや印刷によつ
ても可能である。表示電極板や対向電極板のメタ
ライズはAl/Niの構成の他にCr/Ni、またNiや
Au,Pd,Cu等のメツキを施しても良い。アライ
メントマーク形状は実施例では三角形で示した
が、菱形、円、十字マーク等特に形状を定めるも
のでなく、自動化しやすいパターンあるいは視認
性良く検査しやすいパターン等なんでも良い。マ
ークの数や位置についても限定するものでない。 In the present invention, the solder material is coated by plating, but it can also be coated by dipping or printing. The metallization of the display electrode plate and counter electrode plate is made of Al/Ni, Cr/Ni, or Ni.
Plating with Au, Pd, Cu, etc. may be applied. Although the shape of the alignment mark is shown as a triangle in the embodiment, the shape is not particularly determined, such as a diamond, a circle, or a cross mark, and any pattern such as a pattern that is easy to automate or a pattern that is easy to inspect with good visibility may be used. There are no limitations on the number or position of marks either.
また、片方の電極板にカラーフイルターを形成
してカラー化も可能である。 It is also possible to provide color by forming a color filter on one electrode plate.
また、本考案の様にアライメントマークを用い
て接続に用いると、位置合わせ精度が良好であ
り、短絡等の故障が少なくなる。 Furthermore, when alignment marks are used for connection as in the present invention, alignment accuracy is good and failures such as short circuits are reduced.
第1図、第2図は本考案を示す模式平面図であ
る。
1……対向電極板、2……表示電極板、4……
フイルム、5……ICチツプ、6……端子部、1
0……アライメントマーク。
FIGS. 1 and 2 are schematic plan views showing the present invention. 1... Counter electrode plate, 2... Display electrode plate, 4...
Film, 5...IC chip, 6...Terminal section, 1
0...Alignment mark.
Claims (1)
ムキヤリヤのハンダを施したアライメントマーク
と、メタライズされたパネル基板のアライメント
マークとがハンダ付けで接続している表示パネ
ル。 A display panel in which the soldered alignment mark on a film carrier with an IC chip inner bonded to the alignment mark on a metalized panel board is connected by soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17947685U JPH0356069Y2 (en) | 1985-11-21 | 1985-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17947685U JPH0356069Y2 (en) | 1985-11-21 | 1985-11-21 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6287480U JPS6287480U (en) | 1987-06-04 |
| JPH0356069Y2 true JPH0356069Y2 (en) | 1991-12-16 |
Family
ID=31122572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17947685U Expired JPH0356069Y2 (en) | 1985-11-21 | 1985-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0356069Y2 (en) |
-
1985
- 1985-11-21 JP JP17947685U patent/JPH0356069Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6287480U (en) | 1987-06-04 |
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