JPH0357665B2 - - Google Patents

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Publication number
JPH0357665B2
JPH0357665B2 JP61149615A JP14961586A JPH0357665B2 JP H0357665 B2 JPH0357665 B2 JP H0357665B2 JP 61149615 A JP61149615 A JP 61149615A JP 14961586 A JP14961586 A JP 14961586A JP H0357665 B2 JPH0357665 B2 JP H0357665B2
Authority
JP
Japan
Prior art keywords
signal
output
axis
channel
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61149615A
Other languages
Japanese (ja)
Other versions
JPS637058A (en
Inventor
Takanori Iwamatsu
Yoshitami Aono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61149615A priority Critical patent/JPS637058A/en
Publication of JPS637058A publication Critical patent/JPS637058A/en
Publication of JPH0357665B2 publication Critical patent/JPH0357665B2/ja
Granted legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 〔概要〕 多値直交振幅変調信号の信号点がI軸に近いか
Q軸に近いかにより、I、Qチヤネルの極性信号
と誤差信号との排他的論理和出力を選択して、電
圧制御発振器の出力位相を制御する制御電圧と
し、信号点の位置に関係なく正確な位相の基準搬
送波を再生させるものである。
[Detailed Description of the Invention] [Summary] Depending on whether the signal point of the multilevel quadrature amplitude modulation signal is close to the I axis or the Q axis, the exclusive OR output of the polarity signal of the I and Q channels and the error signal is determined. A control voltage is selected to control the output phase of the voltage controlled oscillator, and a reference carrier wave with an accurate phase is reproduced regardless of the position of the signal point.

〔産業上の利用分野〕[Industrial application field]

本発明は、多値直交振幅変調信号を復調する為
の基準搬送波を再生する基準搬送波再生回路に関
するものである。
The present invention relates to a reference carrier regeneration circuit that regenerates a reference carrier wave for demodulating a multilevel orthogonal amplitude modulation signal.

多値直交振幅変調信号の搬送波成分に位相同期
した基準搬送波を、電圧制御発振器を制御して再
生させ、この基準搬送波を基に90°位相差の搬送
波で、受信した多値直交振幅変調信号を復調する
ものであり、この基準搬送波の位相を正確に制御
することが要望されている。
A reference carrier wave whose phase is synchronized with the carrier wave component of the multilevel quadrature amplitude modulation signal is regenerated by controlling a voltage controlled oscillator, and the received multilevel quadrature amplitude modulation signal is generated using a carrier wave with a 90° phase difference based on this reference carrier wave. It is required to accurately control the phase of this reference carrier wave.

〔従来の技術〕[Conventional technology]

従来の基準搬送波再生回路は、例えば、第5図
に示すように、電圧制御発振器21の出力を基準
搬送波として復調器22に加え、直交位相の搬送
波として受信した多値直交振幅変調信号をIチヤ
ネルとQチヤネルとに復調し、その復調出力信号
をA/D変換器23に加えて複数ビツト構成のデ
イジタル信号に変換する。デイジタル信号に変換
されたIチヤネルの最上位ビツトの極性信号と、
Qチヤネルの下位ビツトの誤差信号とを排他的論
理和回路24に加え、その排他的論理和出力信号
を積分回路25により積分して、電圧制御発振器
21の制御電圧とし、電圧制御発振器21の出力
位相を制御するものである。
For example, as shown in FIG. 5, a conventional reference carrier regeneration circuit applies the output of a voltage-controlled oscillator 21 to a demodulator 22 as a reference carrier, and outputs a multilevel orthogonal amplitude modulation signal received as a carrier in orthogonal phase to an I channel. and Q channel, and the demodulated output signal is applied to the A/D converter 23, where it is converted into a digital signal having a plurality of bits. a polarity signal of the most significant bit of the I channel converted into a digital signal;
The error signal of the lower bit of the Q channel is added to the exclusive OR circuit 24, and the exclusive OR output signal is integrated by the integrating circuit 25 to be the control voltage of the voltage controlled oscillator 21, and the output of the voltage controlled oscillator 21 is It controls the phase.

第6図は動作説明図であり、64値直交振幅変調
信号の第1象限に於ける信号点を×印で示すもの
である。排他的論理和回路24により、Iチヤネ
ルの極性信号と、Qチヤネルの誤差信号との排他
的論理和をとると、例えば、“0”の出力信号と
なるのは斜線を施した領域となり、Q軸の上方と
下方とに於いては、斜線の領域位置が反対とな
る。従つて、誤差信号が0となるように、即ち、
排他的論理和回路24の“1”,“0”の出力信号
を積分回路25により積分して、時間平均をと
り、この積分回路25の出力信号により電圧制御
発振器21を制御すれば、所望の位相の基準搬送
波を再生できることになる。
FIG. 6 is an explanatory diagram of the operation, in which signal points in the first quadrant of the 64-value orthogonal amplitude modulation signal are indicated by x marks. When the exclusive OR circuit 24 takes the exclusive OR of the polarity signal of the I channel and the error signal of the Q channel, for example, the output signal of "0" will be in the shaded area, and the Q Above and below the axis, the positions of the hatched areas are opposite. Therefore, so that the error signal becomes 0, i.e.
If the output signals of "1" and "0" of the exclusive OR circuit 24 are integrated by the integration circuit 25 and time averaged, and the voltage controlled oscillator 21 is controlled by the output signal of the integration circuit 25, the desired result can be obtained. This means that the phase reference carrier wave can be regenerated.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述の従来例に於いては、信号点がI軸に近い
場合に基準搬送波位相を正確に制御できるが、I
軸から離れるに従つて位相の制御が不正確とな
り、多値数が64,256等のように多くなるに
従つて問題となる。即ち、第6図に示すように、
I軸に近くQ軸から遠い信号点aでは、斜線を施
した領域と施さない領域とに対して矢印で示すよ
うにほぼ直角の方向の変化となるが、I軸から遠
くQ軸に近い信号点bでは、矢印で示すように、
ほぼ平行の変化方向となる。従つて、I軸に近い
信号点aによる制御に対してI軸から遠い信号点
bによる制御は不正確となる欠点があつた。
In the conventional example described above, the reference carrier phase can be accurately controlled when the signal point is close to the I axis;
The further away from the axis, the more inaccurate the phase control becomes, and this becomes a problem as the number of multi-values increases, such as 64, 256, etc. That is, as shown in FIG.
At signal point a, which is close to the I-axis and far from the Q-axis, there is a change in the direction almost perpendicular to the shaded area and the non-shaded area, as shown by the arrows, but the signal point a, which is far from the I-axis and close to the Q-axis, changes in the direction shown by the arrows. At point b, as shown by the arrow,
The direction of change is almost parallel. Therefore, there is a drawback that control using signal point b, which is far from the I-axis, is inaccurate compared to control using signal point a, which is close to the I-axis.

本発明は、信号点がI軸から遠い場合に於いて
も正確な制御を可能とすることを目的とするもの
である。
An object of the present invention is to enable accurate control even when the signal point is far from the I-axis.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の基準搬送波再生回路は、信号点がI軸
に近いか遠いかを判定して、制御の切換えを行う
ものであり、第1図を参照して説明する。
The reference carrier regeneration circuit of the present invention switches control by determining whether a signal point is close to or far from the I-axis, and will be described with reference to FIG.

電圧制御発振器1の出力を基準搬送波として復
調器2に加え、この復調器2に於いて受信した多
値直交振幅変調信号を復調し、その復調出力信号
をA/D変換器3によりデイジタル信号に変換す
る。A/D変換器3でデイジタル信号に変換され
たIチヤネルの極性信号とQチヤネルの誤差信号
とを第1のゲート回路4に加えて排他的論理和を
とり、Iチヤネルの誤差信号とQチヤネルの極性
信号とを第2のゲート回路5に加えて排他的論理
和をとり、制御回路6に於いてI,Qチヤネルの
データを基に信号点がI軸に近いかQ軸に近いか
を判定し、I軸に近い信号点については第1のゲ
ート回路4の出力を、又Q軸に近い信号点につい
ては第2のゲート回路5の出力を選択し、互いの
極性を変えて積分し、その積分出力を前記電圧制
御発振器1の制御電圧とするものである。
The output of the voltage controlled oscillator 1 is applied as a reference carrier wave to a demodulator 2, the received multilevel quadrature amplitude modulation signal is demodulated by the demodulator 2, and the demodulated output signal is converted into a digital signal by an A/D converter 3. Convert. The polarity signal of the I channel and the error signal of the Q channel, which have been converted into digital signals by the A/D converter 3, are added to the first gate circuit 4, an exclusive OR is taken, and the error signal of the I channel and the error signal of the Q channel are is added to the second gate circuit 5 and exclusive ORed, and the control circuit 6 determines whether the signal point is close to the I axis or the Q axis based on the data of the I and Q channels. The output of the first gate circuit 4 is selected for signal points close to the I-axis, and the output of the second gate circuit 5 is selected for signal points close to the Q-axis, and the polarities are changed and integrated. , whose integral output is used as the control voltage of the voltage controlled oscillator 1.

〔作用〕[Effect]

信号点がI軸に近いかQ軸に近いかを制御回路
6により判定して、信号点がI軸に近い場合は、
Iチヤネルの極性信号とQチヤネルと誤差信号と
の排他的論理和出力信号を選択して積分すること
により、電圧制御発振器1の制御電圧とし、信号
点がQ軸に近い場合は、Iチヤネルの誤差信号と
Qチヤネルの極性信号との排他的論理和出力信号
を選択して積分することにより、電圧制御発振器
1の制御電圧とし、信号点がI軸に近い場合は勿
論、遠い場合に於いても、正確な位相制御が可能
となる。なお、両排他的論理出力信号は、互いに
反対方向の回転に対して“1”となる為、互いに
極性を変えて積分するものである。
The control circuit 6 determines whether the signal point is close to the I-axis or the Q-axis, and if the signal point is close to the I-axis,
By selecting and integrating the exclusive OR output signal of the polarity signal of the I channel, the Q channel, and the error signal, the control voltage of the voltage controlled oscillator 1 is obtained. By selecting and integrating the exclusive OR output signal of the error signal and the polarity signal of the Q channel, it is used as the control voltage of the voltage controlled oscillator 1. Also, accurate phase control is possible. Note that since both exclusive logic output signals become "1" for rotations in opposite directions, they are integrated while changing their polarities.

〔実施例〕〔Example〕

以下図面を参照して本発明の実施例について詳
細に説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明の実施例のブロツク図であり、
11は電圧制御発振器、12は復調器、13は
A/D変換器、14,15は第1,第2のゲート
回路に相当する排他的論理和回路及び反転出力の
排他的論理和回路、16はセレクタ、17は積分
回路、18はデコーダである。この実施例は、第
1図に於ける制御回路6を、セレクタ16と積分
回路17とデコーダ18とにより構成した場合を
示す。
FIG. 2 is a block diagram of an embodiment of the present invention,
11 is a voltage controlled oscillator, 12 is a demodulator, 13 is an A/D converter, 14 and 15 are exclusive OR circuits corresponding to the first and second gate circuits and an exclusive OR circuit with inverted outputs, 16 1 is a selector, 17 is an integrating circuit, and 18 is a decoder. This embodiment shows a case where the control circuit 6 in FIG.

受信多値直交振幅変調信号は、復調器12に加
えられ、電圧制御発振器11から加えられた基準
搬送波を基に、90°移相器等により直交する搬送
波を形成し、その搬送波により多値直交振幅変調
信号が復調され、復調出力信号はA/D変換器1
3に加えられる。このA/D変換器13により複
数ビツト構成のデイジタル信号に変換され、IA
チヤネルとQチヤネルとのデータが出力される。
The received multilevel quadrature amplitude modulation signal is applied to the demodulator 12, and based on the reference carrier wave added from the voltage controlled oscillator 11, an orthogonal carrier wave is formed by a 90° phase shifter, etc. The amplitude modulated signal is demodulated, and the demodulated output signal is sent to the A/D converter 1.
Added to 3. This A/D converter 13 converts it into a digital signal with multiple bits, and the IA
Channel and Q channel data are output.

排他的論理和回路14には、Iチヤネルの最上
位ビツトの極性信号と、Qチヤネルの下位ビツト
の誤差信号とが加えられ、又反転出力排他的論理
和回路15には、Iチヤネルの下位ビツトの誤差
信号と、Qチヤネルの最上位ビツトの極性信号と
が加えられる。
The exclusive OR circuit 14 is supplied with the polarity signal of the most significant bit of the I channel and the error signal of the lower bit of the Q channel, and the inverted output exclusive OR circuit 15 is supplied with the polarity signal of the most significant bit of the I channel. , and the polarity signal of the most significant bit of the Q channel are added.

デコーダ18は、IチヤネルとQチヤネルとの
デイジタル信号をデコードすることにより、信号
点がI軸に近いかQ軸に近いかを示す信号を出力
してセレクタ16の制御信号とするものであり、
信号点がI軸に近い場合は、セレクタ16により
排他的論路和回路14の出力が選択されて積分回
路17に加えられ、その積分出力が電圧制御発振
器11の位相制御用の制御電圧となる。従つて、
この場合は、従来例について説明した場合と同様
に、基準搬送波の位相が正確に制御される。又信
号点がQ軸に近い場合は、セレクタ16により反
転出力の排他的論理和回路15の出力が選択され
て積分回路17に加えられ、積分出力が電圧制御
発振器11の位相制御用の制御電圧となる。従つ
て、信号点の位置関係が90°回転した場合に相当
し、基準搬送波の位相が正確に制御される。
The decoder 18 decodes the digital signals of the I channel and the Q channel, and outputs a signal indicating whether the signal point is close to the I axis or the Q axis, which is used as a control signal for the selector 16.
When the signal point is close to the I axis, the selector 16 selects the output of the exclusive OR circuit 14 and applies it to the integrating circuit 17, and the integrated output becomes the control voltage for phase control of the voltage controlled oscillator 11. . Therefore,
In this case, the phase of the reference carrier wave is accurately controlled as in the case described for the conventional example. When the signal point is close to the Q axis, the selector 16 selects the output of the exclusive OR circuit 15 with the inverted output and applies it to the integrating circuit 17, and the integrated output is used as the control voltage for phase control of the voltage controlled oscillator 11. becomes. Therefore, this corresponds to a case where the positional relationship of the signal points is rotated by 90°, and the phase of the reference carrier wave is accurately controlled.

第3図は本発明の実施例の動作説明図であり、
第6図に示す従来例と対応して示すものである。
即ち、信号点位置を判定するデコーダ18の出力
で制御されるセレクタ16の選択出力の“0”と
なる領域を斜線で示すものであり、I軸に近い信
号点に於ける位相誤差の検出と、Q軸に近い信号
点に於ける位相誤差の検出とは、90°回転した場
合に相当することになる。例えば、I軸に近い信
号点aでは、斜線を施した領域と施さない領域と
に対して矢印で示すようにほぼ直角の方向の変化
となり、又Q軸に近い信号点bでも、斜線を施し
た領域と施さない領域とに対して矢印で示すよう
にほぼ直角の方向の変化となる。従つて、Q軸に
近い信号点の場合にも、基準搬送波の位相を正確
に制御することができる。
FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention,
This is shown in correspondence with the conventional example shown in FIG.
That is, the region where the selected output of the selector 16, which is controlled by the output of the decoder 18 that determines the signal point position, is "0" is indicated by diagonal lines, and it is used to detect phase errors at signal points near the I-axis. , detection of a phase error at a signal point close to the Q axis corresponds to a case of rotation by 90°. For example, at signal point a near the I-axis, there is a change in the direction almost perpendicular to the shaded area and the non-shaded area, as shown by the arrows, and at signal point b near the Q-axis, the diagonal line is also applied. As shown by the arrows, there is a change in the direction approximately perpendicular to the area where the coating is applied and the area where the coating is not applied. Therefore, even in the case of a signal point close to the Q-axis, the phase of the reference carrier wave can be accurately controlled.

第4図は信号点位置の説明図であり、斜線を施
した領域内の信号点をI軸に近いと判定して、排
他的論理和回路14の出力を選択し、又斜線を施
さない領域内の信号点をQ軸に近いと判定して、
反転出力の排他的論理和回路15の出力を選択
し、選択出力を積分回路17で積分して電圧制御
発振器11の制御電圧とするものである。
FIG. 4 is an explanatory diagram of signal point positions, in which the signal points within the shaded area are determined to be close to the I axis and the output of the exclusive OR circuit 14 is selected, and the signal points within the shaded area are selected. The signal points within are determined to be close to the Q axis, and
The output of the exclusive OR circuit 15 having an inverted output is selected, and the selected output is integrated by an integrating circuit 17 to be used as a control voltage for the voltage controlled oscillator 11.

信号点がI軸に近いかQ軸に近いかを判定する
手段は、各種の論理回路を採用することができる
ものであり、本発明は前述の実施例のみに限定さ
れるものではなく、種々付加変更することができ
るものである。
The means for determining whether a signal point is close to the I-axis or the Q-axis can employ various logic circuits, and the present invention is not limited to the above-described embodiments. It is something that can be added and changed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、多値直交振幅
変調信号を再生した基準搬送波を基に復調し、そ
の復調出力信号をデイジタル信号に変換し、信号
点を判定して、I軸に近い場合は、Iチヤネルの
極性信号とQチヤネルの誤差信号との排他的論理
和出力を選択し、Q軸に近い場合は、Iチヤネル
の誤差信号とQチヤネルの極性信号との排他的論
理和出力を選択し、その選択出力の極性が互いに
反対となるように積分して電圧制御発振器1の制
御電圧とし、基準搬送波の位相を制御するもので
あり、信号点の位置に関係なく正確な位相制御が
可能となる。従つて、多値数の多い直交振幅変調
信号でも、正確に復調することができる利点があ
る。
As explained above, the present invention demodulates a multilevel quadrature amplitude modulation signal based on a reproduced reference carrier wave, converts the demodulated output signal into a digital signal, determines the signal point, selects the exclusive OR output of the I channel polarity signal and the Q channel error signal, and if it is close to the Q axis, selects the exclusive OR output of the I channel error signal and the Q channel polarity signal. The control voltage of the voltage controlled oscillator 1 is obtained by integrating the selected outputs so that their polarities are opposite to each other, and controlling the phase of the reference carrier wave.Accurate phase control is possible regardless of the position of the signal point. It becomes possible. Therefore, there is an advantage that even a quadrature amplitude modulation signal having a large number of values can be accurately demodulated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理ブロツク図、第2図は本
発明の実施例のブロツク図、第3図は本発明の実
施例の動作説明図、第4図は信号点位置の説明
図、第5図は従来の要部ブロツク図、第6図は従
来例の動作説明図である。 1は電圧制御発振器、2は復調器、3はA/D
変換器、4,5は第1,第2のゲート回路、6は
制御回路、11は電圧制御発振器、12は復調
器、13はA/D変換器、14は排他的論理和回
路、15は反転出力排他的論理和回路、16はセ
レクタ、17は積分回路、18はデコーダであ
る。
Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of the embodiment of the invention, Fig. 4 is an explanatory diagram of signal point positions, FIG. 5 is a block diagram of a conventional main part, and FIG. 6 is an explanatory diagram of the operation of the conventional example. 1 is voltage controlled oscillator, 2 is demodulator, 3 is A/D
Converter, 4 and 5 are first and second gate circuits, 6 is a control circuit, 11 is a voltage controlled oscillator, 12 is a demodulator, 13 is an A/D converter, 14 is an exclusive OR circuit, 15 is a 16 is a selector, 17 is an integration circuit, and 18 is a decoder.

Claims (1)

【特許請求の範囲】 1 電圧制御発振器1の出力を基準搬送波として
受信した多値直交振幅変調信号を復調する復調器
2と、 該復調器2の復調出力信号をデイジタル信号に
変換するA/D変換器3と、 該A/D変換器3の出力のIチヤンネルの極性
信号とQチヤンネルの誤差信号との排他的論理和
をとる第1のゲート回路4と、 前記A/D変換器3の出力のIチヤネルの誤差
信号とQチヤネルの極性信号との排他的論理和を
とる第2のゲート回路5と、 前記A/D変換器3の出力のIチヤネルとQチ
ヤネルとのデータを基に、信号点がI軸に近いか
Q軸に近いかを判定して、I軸に近い信号点につ
いては前記第1のゲート回路4の出力を、Q軸に
近い信号点については前記第2のゲート回路5の
出力を互いの極性が反転するように選択して積分
し、積分出力を前記電圧制御発振器1の制御電圧
とする制御回路6とを備えた ことを特徴とする基準搬送波再生回路。
[Scope of Claims] 1. A demodulator 2 that demodulates a multilevel quadrature amplitude modulation signal received using the output of the voltage controlled oscillator 1 as a reference carrier wave, and an A/D that converts the demodulated output signal of the demodulator 2 into a digital signal. a converter 3; a first gate circuit 4 that takes the exclusive OR of the I channel polarity signal and the Q channel error signal of the output of the A/D converter 3; A second gate circuit 5 calculates the exclusive OR of the output I channel error signal and the Q channel polarity signal, and based on the data of the output I channel and Q channel of the A/D converter 3. , determine whether the signal point is close to the I-axis or the Q-axis, and output the output of the first gate circuit 4 for the signal point close to the I-axis, and output the output of the second gate circuit 4 for the signal point close to the Q-axis. 1. A reference carrier regeneration circuit comprising: a control circuit 6 which selects and integrates the outputs of the gate circuits 5 so that their polarities are reversed, and uses the integrated output as a control voltage for the voltage controlled oscillator 1.
JP61149615A 1986-06-27 1986-06-27 Reference carrier recovery circuit Granted JPS637058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61149615A JPS637058A (en) 1986-06-27 1986-06-27 Reference carrier recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61149615A JPS637058A (en) 1986-06-27 1986-06-27 Reference carrier recovery circuit

Publications (2)

Publication Number Publication Date
JPS637058A JPS637058A (en) 1988-01-12
JPH0357665B2 true JPH0357665B2 (en) 1991-09-02

Family

ID=15479081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61149615A Granted JPS637058A (en) 1986-06-27 1986-06-27 Reference carrier recovery circuit

Country Status (1)

Country Link
JP (1) JPS637058A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2787607B2 (en) * 1990-03-13 1998-08-20 富士通株式会社 PSK demodulation circuit

Also Published As

Publication number Publication date
JPS637058A (en) 1988-01-12

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