JPH0377596B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a memory device composed of MOSFETs (insulated gate field effect transistors). The present invention relates to a technique effective for dynamic RAM (Random Access Memory) that performs precharging to Vcc/2 and uses a latch-type CMOS (complementary MOS) inverter as its sense amplifier. [Background Art] Prior to the present invention, the present inventors had already developed a pseudo-static RAM that detects changes in address signals and forms various timing signals necessary for the operation of internal circuits. In other words, a dynamic memory cell is used, which is composed of a capacitor that stores information in the form of charge, and an address selection MOSFET, and its peripheral circuitry is composed of a CMOS static type circuit to detect changes in the address signal. By doing so to obtain the necessary timing signals, it can be treated externally in the same way as a static RAM. The main circuit of this MOS storage device is shown in FIG.
It consists of a storage capacitor Cs and an address selection MOSFET Q15, which are shown as a representative.
1MOS type memory cells are arranged in a matrix. The memory cell includes a pair of complementary data lines D, which are shown as a representative, and which are arranged in parallel.
The input/output nodes are connected to one of the nodes in a so-called two-intersection manner. The precharging of the complementary data lines D, is performed in response to the precharge pulse φpcr.
It is composed of a MOSFET Q14 that short-circuits D and precharges the data line D to Vcc/2.
The sense amplifier is connected to the power supply voltage Vcc and the circuit ground potential.
A power switch consisting of a p-channel MOSFET and an n-channel MOSFET for Vss.
It is composed of a CMOS (complementary MOS) latch circuit provided with MOSFETs Q12 and Q10, and its pair of input/output nodes are coupled to the complementary data line D. The timing pulses φpa and pa are
This is for controlling the power switch MOSFETs Q10 and Q12. power switch
MOSFETQ10 and Q12 are turned off immediately before precharging. This causes the complementary data line D, to follow the previous read or write operation.
Maintain Vcc and Vss levels in a floating state. And the above precharge MOSFETQ14
When turned on, the complementary data line D is short-circuited. As a result, both data lines D are precharged to Vcc/2. In this way, precharging of a pair of complementary data lines is done by simply shorting the pair of complementary data lines to an intermediate level of about Vcc/2, so it is possible to charge up the data lines from 0 volts to the Vcc level. In comparison, the amount of level change is small, and even if the gate voltage of the precharge MOSFET is used at a normal logic level (Vcc), it can be turned on in a sufficiently non-saturated state, so the precharge operation can be performed at high speed and with low power consumption. can be done. As mentioned above, since the precharge level is set to an intermediate level of approximately Vcc/2,
Even when reading a memory cell, the bootstrap voltage can be turned on in a sufficiently unsaturated state even if the normal logic level (Vcc) is used as the gate voltage (word line selection voltage) of the memory cell switch MOSFET. without using
It becomes possible to read out the entire charge of the information storage capacitor. Further, since the read reference voltage utilizes the precharge level of one data line in which no memory cell is selected, there may or may not be a dummy cell forming the read reference voltage. The inventor's research has revealed that the following problems occur in the precharge operation. That is, in the precharge operation, the complementary data line pair is precharged to approximately Vcc/2, thereby supplying an intermediate level to the latch-type CMOS inverter constituting the sense amplifier, and the power switch.
Both voltage terminals of the sense amplifier (common power supply source N1, N
2) holds the voltage Vcc and 0V in the floating state. Therefore, a CMOS latch circuit is configured by supplying the above intermediate level.
MOSFETQ6 to Q9 are all turned on,
The complementary data line pair D and the sense amplifier power supply lines N1 and N2 are also connected. Therefore, in addition to charge dispersion between the pair of complementary data lines, charge dispersion with the parasitic capacitance of the power supply line of the sense amplifier is performed. The parasitic capacitances of the pair of complementary data lines are set to be approximately equal because the same number of memory cells are connected. However, in the power supply line of the sense amplifier, the sources and drains of p-channel MOSFETs Q7, Q9, and Q12 are connected to the power supply voltage side, and the sources and drains of n-channel MOSFETs Q6, Q8, and Q10 are connected to the ground potential side. Therefore, the parasitic capacitance value becomes unbalanced. As a result, the precharge level of the complementary data line pair fluctuates, causing deterioration of the operating margin. [Object of the Invention] An object of the present invention is to provide a MOS memory device with improved operating margin. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows. That is, when a CMOS latch circuit is used as a sense amplifier of a memory array that performs precharging by shorting a pair of complementary data lines,
By short-circuiting the pair of common power supply common lines during the precharge period, the MOSFETs forming the sense amplifier are turned off. This prevents parasitic capacitance in the power supply line from affecting the precharge operation of the complementary data line pair. [Embodiment] FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, each circuit block surrounded by dotted lines is manufactured using known semiconductor integrated circuit manufacturing technology.
Formed on one semiconductor substrate such as silicon, for example, terminals D0 to D7, A0 to A1
4,,,H and Vcc, Vss are external terminals, and power is supplied to the terminals Vcc, Vss from an appropriate external power supply device (not shown). The circuit symbol M-ARY is a memory array, which is composed of 1MOS type memory cells each composed of a storage capacitor and an address selection MOSFET arranged in a matrix.
In this embodiment, although not particularly limited, the memory cells are arranged in a so-called two-intersection system in which their input/output nodes are coupled to either one of a pair of complementary data lines D arranged in parallel. The circuit symbol PC1 is a data line precharge circuit, which receives a precharge pulse φpcr and shorts the complementary data line D.
It consists of a MOSFET that precharges to Vcc/2. The circuit symbol SA indicates a sense amplifier, which is connected to the power supply voltage Vcc and the circuit ground potential Vss by a power switch, although this is not particularly limited.
It is composed of a CMOS (complementary MOS) latch circuit provided with a MOSFET, and its pair of input/output nodes are coupled to the complementary data line D.
As will be explained later using FIG. 3, the power switch MOSFET is commonly used for a plurality of CMOS latch circuits. Timing pulses φpa1, pa1 and φpa2,
φpa2 is for controlling the power switch MOSFET. power switch
The MOSFET is turned off just before precharging. As a result, the complementary data lines D maintain the Vcc and Vss levels in a floating state. When the precharge MOSFET is turned on, the complementary data lines D and D are short-circuited and precharged to Vcc/2. By simply short-circuiting a pair of complementary data lines (the same applies to a common complementary data line to be described later) in the precharge operation of the memory array as in this embodiment, various effects similar to those described above can be obtained. In addition, the above power switch
A reset MOSFET that is turned on during the precharge period is connected between the power supply lines N1 and N2 that supply the power supply voltage Vcc and the circuit ground potential to each of the plurality of CMOS latch circuits by turning on the MOSFET. provided. Note that the timing signals φpa1 and pa1 are mutually complementary signals, and the timing signal φpa
2, and pa2 are also mutually complementary signals. In order to simplify the drawing, in the figure, the timing signals φpa1 and pa1 are collectively expressed as φpa1 , and the timing signals φpa2 and pa2 are collectively expressed as φpa2. A column switch, designated by the circuit symbol C-SW, couples a selected complementary data line to a common complementary data line in accordance with a column selection signal. The circuit symbol R-ADB is a row address buffer, which receives external address signals from external terminals A0-A8 and forms internal complementary address signals a0-a8, 0-8. In the following description and drawings, a pair of internal complementary address signals, for example a0,0, will be expressed as internal complementary address signal a0 . Therefore, the internal complementary address signals a0 to a8, 0 to 8
is expressed as a0 to a8 . The circuit symbol C-ADB is a column address buffer, which connects external terminals A9 to A1.
4, and form internal complementary address signals a9-a14, 9-14. In accordance with the above-mentioned representation of the internal complementary address signals, the internal complementary address signals a9 to a14 and 9 to a14 are expressed as a9 to a14 in the drawings and the following description. The circuit symbol R-DCR is a row address decoder, which receives an internal complementary address signal a0 - a via a multiplexer MPX, which will be described later.
8 and forms the M-ARY word line selection signal. This word line selection signal is transmitted to M-ARY in synchronization with the word line selection timing signal φx. The circuit symbol C-DCR indicates a column address decoder, which receives internal complementary address signals a9 to a14 and forms a data line selection signal for M-ARY. This data line selection signal is
It is transmitted to column switch C-SW in synchronization with data line selection timing signal φy. What is indicated by the circuit symbol PC2 is a precharge circuit for the common complementary data line. Although not particularly limited, the above precharge circuit short-circuits the common complementary data line in response to a precharge pulse φpcd.
It is composed of MOSFETs similar to PC1. The circuit symbol MA indicates the main amplifier, which has the same circuit configuration as the sense amplifier SA described above. Although not particularly limited, a reset MOSFET similar to the sense amplifier SA is provided between the pair of power supply lines. Timing pulses φma1,ma1 and φma2,2
is for controlling the power switch MOSFET. Note that the timing signals φma1 and φma1 are mutually complementary signals, and the timing signals φma2 and ma2 are also mutually complementary signals. In the figure, the timing signals φma1 and ma1 are collectively expressed as φma 1,
Timing signals φma2 and ma2 are combined to φma
It is expressed as 2. The circuit symbol DOB is the data output buffer and the read timing pulse
rw, the read data from main amplifier MA is sent to external terminals D0 to D7, respectively.
Note that during writing, this DOB is brought into a non-operating state (output high impedance) by the read timing pulse φrw. The circuit symbol DIB is a data input buffer, which transmits write data from external terminals D0 to D7 to a common complementary data line in response to a write timing pulse φrw. Note that when reading, this DIB is set by the write timing pulse φrw.
is rendered inactive. The various timing signals mentioned above are formed by the following circuit blocks. The circuit symbol REG indicates address signals a0 to a8 (or 0
8) and detects the rising or falling edge of the signal. Although not particularly limited, the circuit symbol CEG is an edge trigger circuit that receives address signals a9 to a14 (or 9 to 14) and detects their rising or falling edges. The edge trigger circuit REG includes, but is not particularly limited to, an exclusive OR circuit that receives each of the address signals a0 to a8 and their delayed signals, and an OR circuit that receives the output signals of these exclusive OR circuits. It is composed of That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of these nine exclusive OR circuits are input to the OR circuit. When one of the address signals a0 to a8 changes, this edge trigger circuit REG forms an edge detection pulse φr synchronized with the timing of the change. The edge trigger circuit CEG has the same configuration as the edge trigger circuit REG. That is, it is constituted by exclusive OR circuits that receive address signals a9 to a14 and their delayed signals, respectively, and an OR circuit that receives output signals from these exclusive OR circuits. This edge trigger circuit CEG, like the edge trigger circuit REG described above, forms an edge detection pulse φc synchronized with the change timing when any one of the address signals a9 to a14 changes. The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as a representative above. That is, this timing generation circuit TG generates edge detection pulses φr,
In addition to φc, it receives a write enable signal and a chip selection signal supplied from an external terminal to form the above series of timing pulses. The circuit symbol MPX is a multiplexer, which is an automatic refresh circuit described later.
According to the control signal φref from REF, the internal complementary address signals a0 to a8 formed by the address buffer R-ADB and the internal complementary address signal a0 formed by the automatic refresh circuit REF are
to a8 are selectively transmitted to the decoder R-DCR. The circuit symbol Vbb-G indicates a substrate bias voltage generation circuit. The circuit symbol REF is an automatic refresh circuit, which includes a refresh address counter, a timer, etc., and is activated by setting a refresh signal from an external terminal to a low level. That is, when the refresh signal is set to low level while the chip selection signal is high level, the automatic refresh circuit REF switches the multiplexer MPX by the control signal φref,
An internal address signal from a built-in refresh address counter is transmitted to the row decoder R-DCR to perform a refresh operation (auto refresh) by selecting one word line. Further, when the refresh signal is kept at a low level, a timer is activated, and the refresh address counter is incremented at regular intervals, and a continuous refresh operation (self-refresh) is performed during this time. FIG. 3 shows a circuit diagram of a specific embodiment of the main circuits shown in FIG. 2 above. In the following explanation, unless otherwise specified, MOSFET
is an n-channel MOSFET. In the memory array M-ARY, a pair of rows thereof are shown as a representative, and a switch MOSFET Q1 is connected to a pair of complementary data lines D arranged in parallel.
The input/output nodes of each of the plurality of memory cells constituted by MOS capacitors and MOS capacitors are distributed and coupled with a predetermined regularity as shown in the figure. The precharge circuit PC1, like MOSFETQ14 shown as a representative, has complementary data lines D,
It is composed of a switch MOSFET Q14 provided between D and D. The sense amplifier SA consists of the representative p-channel MOSFETs Q7 and Q9 and the n-channel MOSFETs.
CMOS (complementary type) consisting of MOSFETQ6 and Q8
(MOS) latch circuit, and its pair of input/output nodes are coupled to the complementary data line D. In addition, the above latch circuit may include, but is not limited to, a parallel p-channel MOSFET Q1.
2. Power supply voltage Vcc is supplied through Q13, and parallel n-channel MOSFETs Q10 and Q11
The circuit ground voltage Vss is supplied through. These power switch MOSFETs Q10, Q11 and MOSFETs Q12, Q13 are commonly used for sense amplifiers SA provided in other similar rows. A reset MOSFET Q45 that is turned on during the precharge period is provided between the pair of power supply lines N1 and N2 configured as described above. The gates of the MOSFETs Q10 and Q12 are as follows:
Complementary timing pulses φpa1 and pa1 that activate the sense amplifier SA are applied, and MOSFETQ
Complementary timing pulses φpa2, pa2 delayed from the above-mentioned timing pulses φpa1, pa1 are applied to the gates of Q11 and Q13. The reason for this is
When the sense amplifier SA is operated with a minute read voltage from the memory cell, the drop in the level of the data line is suppressed by a relatively small conductance.
This can be prevented by limiting radio waves using MOSFETs Q10 and Q12. After increasing the potential difference between the complementary data lines by the amplification operation in the SA, MOSFETs Q11 and Q13 having relatively large conductance are turned on to speed up the amplification operation. By performing the amplification operation of the sense amplifier SA in two stages in this way, high-speed reading can be performed while preventing the complementary data image from falling on the high level side. One circuit (four word lines) of the row decoder R-DCR is shown as a representative, and for example, an n-channel receiving address signals 2 to 6.
MOSFETQ32~Q36 and p channel
The word line selection signals for the four lines are formed by a NAND circuit using a CMOS circuit composed of MOSFETs Q37 to Q41. The output of this NAND circuit is a CMOS inverter.
Inverted by IV1, cut MOSFETQ28~Q3
1 to the gates of MOSFETs Q24 to Q27. Furthermore, four word line selection timing signals φx00 to φx11 formed by the combination of the decode signal formed by the complementary address signals a0 and a1 and the timing pulse φx are applied to the MOSFET Q2.
It is transmitted to each word line via Q4 to Q27. Also, between each word line and the ground potential,
MOSFETs Q20 to Q23 are provided, and by applying the output of the NAND circuit to their gates, the word line is fixed at the ground potential when not selected. The above word line has MOSFETQ for reset.
MOSFETs Q1 to Q4 are provided, and when these MOSFETs Q1 to Q4 are turned on in response to a reset pulse φpw, a selected word line is reset to the ground level. The column switch C-SW selectively couples the complementary data line D and the common complementary data line CD, like MOSFETs Q42 and Q43 shown as representatives. These MOSFETQ42,
The gate of Q43 has a column decoder C-DCR.
A selection signal is supplied from. A precharge MOSFET Q44 constituting a precharge circuit PC2 similar to the above is provided between the common complementary data lines CD. This common complementary data line CD is connected to a main amplifier with a circuit configuration similar to that of the sense amplifier SA mentioned above.
A pair of MA input/output nodes are connected. Although the block diagram of FIG. 2 shows a ×8 bit configuration, this embodiment shows a memory array for one bit. [Effect] In precharging the complementary data line pair, the pair of power supply lines of the sense amplifier SA are short-circuited to reset the complementary data line pair to substantially the same intermediate level. Therefore, even if the complementary data line pair becomes an intermediate level due to the precharge operation of the complementary data line pair, the amplification MOSFET constituting the sense amplifier SA will not be turned on. In other words, the amplification occurs during the precharge period.
Since the complementary data line to which the gate side of the MOSFET is connected and the power supply line to which the source side of the amplification MOSFET is connected are at almost the same potential, their amplification
The MOSFET is in the off state. As a result, the precharge potential of the complementary data line pair used as a reference voltage during the read operation can be set to a stable level of approximately Vcc/2 with high accuracy, resulting in the effect of expanding the operating margin. can get. Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the specific circuit configuration of each circuit block constituting the dynamic RAM can be modified in various ways. Further, the memory bet can be modified in various ways such as x1. Also, short-circuit the power supply line
A plurality of MOSFETs may be provided. [Field of Application] The present invention can be widely used in MOS storage devices that precharge a pair of complementary data lines to Vcc/2 and use a sense amplifier constituted by a CMOS latch circuit.

[Brief explanation of drawings]

Figure 1 shows a model developed prior to this invention.
FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing a specific embodiment of the main circuits of the MOS storage device. M-ARY...Memory array, PC1...Precharge circuit, SA...Sense amplifier, R-ADB...
...Row address buffer, C-SW...Column switch, C-ADB...Alumn address buffer,
R-DCR……Row address decoder, C-DCR
...Column address decoder, PC2...Precharge circuit, MA...Main amplifier, REG,
CEG...Edge trigger circuit, TG...Timing generation circuit, REF...Auto refresh circuit, DOB
...Data output buffer, DIB...Data input buffer, MPX...Multiplexer, Vbb-G...
...Substrate bias circuit.

Claims (1)

[Claims] 1. A precharge circuit that performs precharging by short-circuiting a pair of complementary data lines arranged in parallel, and a pair of input/output terminals connected to the pair of complementary data lines. Latch form
A sense amplifier composed of a CMOS inverter,
A power switch MOSFET is provided between the pair of voltage terminals of the sense amplifier, a power supply voltage terminal, and a ground potential terminal, and a reset MOSFET that is turned on during the precharge period to short-circuit the pair of voltage terminals of the sense amplifier. A MOS storage device characterized by comprising a MOSFET for use in 2. A memory cell for storing information whose input/output terminals are connected to the data line is composed of a capacitor for storing information and a MOSFET for selecting an address, and a peripheral circuit for writing and reading the memory cell. Claim 1 is characterized in that it is constituted by a CMOS circuit.
MOS storage device described in section. 3 The above power switch MOSFET consists of a p-channel MOSFET on the power supply voltage side that turns the sense amplifier into an operating state at a relatively early timing, an n-channel MOSFET on the ground potential side, and a p-channel MOSFET on the power supply voltage side that turns on the sense amplifier later than the above timing. Channel MOSFET and n-channel on the ground potential side
Claim 1 or 2, characterized in that the device is composed of MOSFETs.
MOS storage device.