JPH0380346B2 - - Google Patents
Info
- Publication number
- JPH0380346B2 JPH0380346B2 JP57226321A JP22632182A JPH0380346B2 JP H0380346 B2 JPH0380346 B2 JP H0380346B2 JP 57226321 A JP57226321 A JP 57226321A JP 22632182 A JP22632182 A JP 22632182A JP H0380346 B2 JPH0380346 B2 JP H0380346B2
- Authority
- JP
- Japan
- Prior art keywords
- patterns
- chip
- pattern
- face
- alignment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07178—Means for aligning
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 本発明はフエイスダウンボンダに関する。[Detailed description of the invention] The present invention relates to a face down bonder.
半導体装置において、チツプ(回路素子)の電
極と外部リードとの接続を図る構造の1つとして
第1図で示すように、チツプ1の電極を盛り上げ
てパンプ電極2とし、このパンプ電極2を直接配
線基板3の配線層4に重ね合せるようにして接続
するいわゆるフエイスダウンボンデイングが知ら
れている。このボンデイングにあたつてフエイス
ダウンボンダが用いられている。 In a semiconductor device, one of the structures for connecting the electrodes of a chip (circuit element) and external leads is as shown in FIG. So-called face-down bonding is known, which connects the wiring layer 4 of the wiring board 3 in an overlapping manner. A face down bonder is used for this bonding.
このフエイスダウンボンダにあつては、基板パ
ターンとチツプパターンの位置合せが必要とな
る。この場合、位置合せ機構としては、ハーフミ
ラーを用いた光学系を利用する方法(図示せず)、
また、第2図a,bで示すような、2つの工業用
テレビカメラ(ITV)を用いて画像処理を利用
する方法がある。すなわち、基板3をテーブル5
上に載置するとともに、透明ガラス板6上にチツ
プ1をそのパンプ電極部分を下面にして載置し、
第1のITV7により基板3のパターンを、また
第2のITV8によりチツプ1のパターンをそれ
ぞれ写し、画像処理により、第2図bのようにモ
ニタテレビ10で両パターン12,13を目視認
識する。 In the case of this face-down bonder, it is necessary to align the substrate pattern and the chip pattern. In this case, the alignment mechanism includes a method using an optical system using a half mirror (not shown);
There is also a method that utilizes image processing using two industrial television cameras (ITV), as shown in FIGS. 2a and 2b. In other words, the substrate 3 is placed on the table 5
At the same time, the chip 1 is placed on the transparent glass plate 6 with its pump electrode portion facing downward,
The pattern of the board 3 is photographed by the first ITV 7, and the pattern of the chip 1 is photographed by the second ITV 8, and through image processing, both patterns 12 and 13 are visually recognized on the monitor television 10 as shown in FIG. 2B.
そして、チツプ1を下端に真空吸着保持する支
持ツール9の降下地点11の位置に、チツプパタ
ーン13あるいは、基板パターン12を位置(重
ね)合せした後、支持ツール9によつてチツプ1
を真空吸着しテーブル5上に支持ツール9を移動
させ基板3にチツプ1を重ね合せかつ熱を利用し
てそれぞれの接続物の接続を図る。また、位置合
せ(アライメント)は支持ツール9あるいは、透
明ガラス板6、およびテーブル5をXY方向に移
動させたり、回転させたりして行なう。 After the chip pattern 13 or the substrate pattern 12 is positioned (overlaid) at the position of the drop point 11 of the support tool 9 which holds the chip 1 at the lower end by vacuum suction, the chip 1 is
The supporting tool 9 is moved onto the table 5, the chip 1 is superimposed on the substrate 3, and the respective connections are connected using heat. Further, alignment is performed by moving or rotating the support tool 9, the transparent glass plate 6, and the table 5 in the XY directions.
ところで、従来、この位置合せ手順としては、
まず、第3図aに示すように支持ツール9を移動
させて透明ガラス板6上に臨ませ、第2のITV
8によつて支持ツール先端像11をモニタテレビ
10の画面中央に写し出す。その後テーブル5を
移動制御して支持ツール先端像11に、第1の
ITV7によつて同モニタテレビ10に写し出さ
れる基板パターン12を重ね合せて位置合せす
る。つぎに第3図bで示すように支持ツール9を
移動させた後基板パターン12と第2のITV8
によつて写し出されるチツプパターン13とを透
明ガラス板6を移動制御して、両パターンを重ね
合せて位置合せする。 By the way, conventionally, this alignment procedure is as follows:
First, as shown in FIG. 3a, the support tool 9 is moved to face the transparent glass plate 6, and the second ITV is
8, the supporting tool tip image 11 is projected at the center of the screen of the monitor television 10. After that, the table 5 is controlled to move so that the first support tool tip image 11 is
The substrate patterns 12 projected on the monitor television 10 by the ITV 7 are superimposed and aligned. Next, as shown in FIG. 3b, after moving the support tool 9, the substrate pattern 12 and the second ITV 8 are removed.
The transparent glass plate 6 is moved and controlled to overlap and align the chip pattern 13 and the chip pattern 13 projected by the .
このように、従来は、基準となるパターンを順
次かえて位置合せを行なうという方法がとられて
いた。しかし、この方法では、一工程で少なくと
も2回位置合せを行なうことになり、作業の能率
向上、自動化を図るうえで大きな障害となつてい
た。 In this way, conventionally, a method has been used in which alignment is performed by sequentially changing the reference pattern. However, in this method, alignment is performed at least twice in one process, which is a major obstacle to improving efficiency and automating the work.
したがつて、本発明の目的は、作業の能率向上
を図ることができるとともに、自動化にも適する
構造のフエイスダウンボンダを提供することにあ
る。 Therefore, an object of the present invention is to provide a face-down bonder having a structure that can improve work efficiency and is also suitable for automation.
このような目的を達成する為に、本発明は、目
視確識する像または画面上に、基準となるマーク
を配し、この基準マークにそれぞれの接続物、被
接続物画像を重ね合せる構造の位置合せ機構を有
するボンダとするものであつて以下実施例により
本発明を説明する。 In order to achieve such an object, the present invention has a structure in which a reference mark is arranged on an image or screen that can be visually confirmed, and images of each connected object and connected object are superimposed on this reference mark. The present invention, which is a bonder having a positioning mechanism, will be explained below with reference to Examples.
第4図は、本発明の一実施例によるフエイスダ
ウンボンダの位置合せ機構を示す。同図に示すよ
うに、モニタテレビ10の画面上に、それぞれ相
互に平行となる縦2本横2本の電子ライン14を
引き、画面中央に四角枠からなるマークを設け
る。この四角枠のマークは、支持ツール先端像の
位置に設定し基準マーク15とする。この位置合
せ機構における、位置合せは、基準マーク15に
基板パターン12およびチツプパターン13を移
動させ、両パターンを重ね合せるだけで行なえ
る。 FIG. 4 shows a face-down bonder alignment mechanism according to an embodiment of the present invention. As shown in the figure, two parallel electronic lines 14 and two horizontal lines 14 are drawn on the screen of a monitor television 10, and a mark consisting of a rectangular frame is provided at the center of the screen. This square frame mark is set at the position of the supporting tool tip image and is used as a reference mark 15. In this alignment mechanism, alignment can be performed simply by moving the substrate pattern 12 and chip pattern 13 to the reference mark 15 and overlapping both patterns.
このような実施例によれば、位置合せ時におけ
る支持ツールの移動という動作(操作)が不用と
なり、1回で、位置合せ作業を完了することがで
きる。したがつて、作業性が向上するとともに、
操作が簡素であることから自動化も可能である。
なお、本発明は、前記実施例に限定されない。例
えば、接眼ミクロを基準マークとしてもよい。ま
た、基準マークは他の形状でもよい。さらに、接
続物および被接続物は基板、チツプ以外のもので
よいことは勿論である。 According to such an embodiment, the operation (operation) of moving the support tool during alignment is unnecessary, and the alignment work can be completed in one time. Therefore, workability is improved, and
Since the operation is simple, automation is also possible.
Note that the present invention is not limited to the above embodiments. For example, the eyepiece micro may be used as the reference mark. Further, the reference mark may have other shapes. Furthermore, it goes without saying that the connecting object and the connected object may be other than the substrate and the chip.
以上のように本発明によれば、対向する対象物
の位置合せが1回ですみ、作業能率の向上を図る
ことができる。また自動化が容易になる。 As described above, according to the present invention, opposing objects only need to be aligned once, and work efficiency can be improved. It also makes automation easier.
第1図はフエイスダウン構造を示す正面図、第
2図a,bは従来のフエイスダウンボンダにおけ
る位置合せ機構を示す概略図、第3図a,bは、
従来の位置合せ方法を示す概略図、第4図は、本
発明の一実施例によるフエイスダウンボンダの位
置合せ方法を示す概略図。
1……チツプ、2……バンプ電極、3……基
板、4……配線層、5……テーブル、6……透明
ガラス、7……第1のITV(1)、8……第2の
ITV(2)、9……支持ツール、10……モニタテ
レビ、11……支持ツール先端像、13……チツ
プパターン、12……基板パターン、14……電
子ライン、15……基準マーク。
Figure 1 is a front view showing the face down structure, Figures 2 a and b are schematic diagrams showing the alignment mechanism in a conventional face down bonder, and Figures 3 a and b are
FIG. 4 is a schematic diagram showing a conventional alignment method. FIG. 4 is a schematic diagram showing a face down bonder alignment method according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Chip, 2... Bump electrode, 3... Substrate, 4... Wiring layer, 5... Table, 6... Transparent glass, 7... First ITV (1), 8... Second
ITV (2), 9... Support tool, 10... Monitor TV, 11... Support tool tip image, 13... Chip pattern, 12... Board pattern, 14... Electronic line, 15... Reference mark.
Claims (1)
時に認識して接続物と被接続物の位置合わせを行
なつた後、両パターンを重ね合わせ、その後接続
物と被接続物との接続を図るフエイスダウンボン
ダにおいて、前記両パターンが同時に認識できる
モニタテレビが設けられ、そのモニタテレビの画
面上にそれぞれ相互に平行となる縦2本横2本の
電子ラインを引くことによつて画面中央に四角枠
からなる基準マークを設置し、この基準マークに
それぞれ両パターンを位置合わせすることによつ
て接続物と被接続物のとの位置合わせを行なうこ
とを特徴とするフエイスダウンボンダ。1. Simultaneously recognize the quantity patterns of the opposing connecting object and the connected object, aligning the connecting object and the connected object, and then superimposing both patterns, and then attempting to connect the connecting object and the connected object. In the face-down bonder, a monitor television is provided that can recognize both patterns at the same time, and by drawing two vertical and two horizontal electronic lines parallel to each other on the screen of the monitor television, a square is created in the center of the screen. A face-down bonder characterized in that a reference mark consisting of a frame is installed, and a connecting object and a connected object are aligned by aligning both patterns to the reference mark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226321A JPS59117225A (en) | 1982-12-24 | 1982-12-24 | Face down bonding device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226321A JPS59117225A (en) | 1982-12-24 | 1982-12-24 | Face down bonding device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59117225A JPS59117225A (en) | 1984-07-06 |
| JPH0380346B2 true JPH0380346B2 (en) | 1991-12-24 |
Family
ID=16843355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57226321A Granted JPS59117225A (en) | 1982-12-24 | 1982-12-24 | Face down bonding device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117225A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10338809B4 (en) * | 2003-08-21 | 2008-05-21 | Hesse & Knipps Gmbh | Method and device for adjusting bonding head elements |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574131A (en) * | 1980-06-10 | 1982-01-09 | Nippon Abionikusu Kk | Device for mounting of semiconductor chips |
-
1982
- 1982-12-24 JP JP57226321A patent/JPS59117225A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59117225A (en) | 1984-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6273639A (en) | Method of mounting semiconductor chip | |
| JPH0380346B2 (en) | ||
| KR102354344B1 (en) | Semiconductor component bonding equipment | |
| JP2828503B2 (en) | Flip chip bonder device and alignment method for the device | |
| JP3163717B2 (en) | Bonding method and apparatus | |
| JP2001217387A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JP3094639B2 (en) | Circuit board bonding method for liquid crystal display module | |
| JPH0587949U (en) | Semiconductor chip | |
| JPH0212024B2 (en) | ||
| JP3370419B2 (en) | Positioning method for mounting electronic components on circuit boards | |
| JPH05152794A (en) | Ic chip mounting apparatus | |
| JPH0131296B2 (en) | ||
| JPS6257098B2 (en) | ||
| JPS6239537B2 (en) | ||
| JP2701174B2 (en) | Bumping method | |
| JP2907246B2 (en) | Component mounting equipment | |
| JPH09232363A (en) | Positioning method of semiconductor chip and bonding apparatus | |
| JPH06310569A (en) | Face-down bonding method of semiconductor element | |
| JP3209250B2 (en) | Optoelectronic integrated circuit mounting device | |
| JPH08264588A (en) | Bonding method | |
| JPS5826664B2 (en) | automatic wire bonding method | |
| JPH05190553A (en) | Semiconductor component mounting structure and method for manufacturing solder bumps thereof | |
| JPH0139216B2 (en) | ||
| JP2018006510A (en) | Component mounting device | |
| TW202425198A (en) | Substrate processing apparatus and substrate processing method |