JPH0385751A - Semiconductor device and its mounting method - Google Patents
Semiconductor device and its mounting methodInfo
- Publication number
- JPH0385751A JPH0385751A JP1223993A JP22399389A JPH0385751A JP H0385751 A JPH0385751 A JP H0385751A JP 1223993 A JP1223993 A JP 1223993A JP 22399389 A JP22399389 A JP 22399389A JP H0385751 A JPH0385751 A JP H0385751A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- leads
- lead
- semiconductor device
- bridge layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3465—Application of solder
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明は、クワッドフラットパッケージ(QFP)、
スモールアウトラインパッケージ(SOP)等の多ビン
ICなどの半導体装置およびこの半導体装置の基板への
実装方法に関し、リードの補強、実装工程での作業の簡
略化、半導体装置の接合強度の改善等を計ったものであ
る。[Detailed Description of the Invention] "Industrial Application Field" This invention relates to quad flat packages (QFP),
Regarding semiconductor devices such as multi-bin ICs such as small outline packages (SOPs) and methods for mounting these semiconductor devices on substrates, we have taken measures such as reinforcing leads, simplifying work in the mounting process, and improving the bonding strength of semiconductor devices. It is something that
「従来の技術」
従来、QFPなどの表面実装タイプのICパッケージの
リードは、ICの集積度の向上に応じて細くなる傾向に
ある。そして、ザブミクロンルールにより集積度が更に
高くなると、リード自体が極めて細くなり、その強度も
低下するために、搬送や取り扱い時のわずかな負荷によ
って、例えば、ICパッケージの包装紙とのわずかな接
触、あるいは、半田付けの際の半田ゴテとの接触などに
上ッて、リードが容易に変形してしまう程に軟弱になつ
てきている。"Prior Art" Conventionally, the leads of surface mount type IC packages such as QFP have tended to become thinner as the degree of integration of the IC improves. As the degree of integration increases further according to the Zabumicron rule, the leads themselves become extremely thin and their strength decreases. Or, the leads have become so weak that they are easily deformed by contact with a soldering iron during soldering.
「発明が解決しようとする課題」
従ってこのようなICパッケージを実装基板に実装する
場合、従来のように半田ゴテを使用しての人為的作業に
よる接合方法は全く適用できない状況にある。即ち、糸
半田の供給、あるいは、半田ゴテの当接などによりリー
ドが変形してしまうおそれが高く、歩留り、作業効率が
向上しないばかりか、各リードの基板に対する均一な実
装剥離強度を得ることができない問題がある。``Problem to be Solved by the Invention'' Therefore, when mounting such an IC package on a mounting board, the conventional manual joining method using a soldering iron is not applicable at all. In other words, there is a high risk that the leads will be deformed due to the supply of solder thread or contact with a soldering iron, which not only does not improve yield and work efficiency, but also makes it difficult to obtain uniform mounting peel strength of each lead to the board. There is a problem that cannot be done.
また、QFPなどの多ピンでリード(ピン)の間隔が狭
いICにおいては、リード間隔が065mm以下になる
ものもあるので、接合時に供給する半田量か僅かでも過
剰であると、リフロー(溶融)後にリード間の半田によ
るブリツノが発生して隣接するり一ドどうしが短絡する
おそれがあるとともに、少しでも半田の供給量か不足す
ると、接合強度の不足が生じるために、適正な量の半田
を供給することが極めて困難であった。In addition, in ICs with many pins and narrow lead (pin) spacing such as QFP, the lead spacing may be 0.65 mm or less, so if the amount of solder supplied during bonding is even slightly excessive, reflow (melting) may occur. Later, there is a risk that blister may occur due to the solder between the leads, causing short circuits between adjacent leads, and if even a small amount of solder is insufficient, the bonding strength will be insufficient, so make sure to use an appropriate amount of solder. It was extremely difficult to supply.
この発明は前記課題を解決するためになされたもので、
搬送や取り扱いの段階においてリードの変形防止ができ
るとともに、従来の外部からの半田供給法によらずとも
半導体装置を基板に十分な接合強度で半田接合し、実装
することができ、実装工程を簡略化できる半導体装置お
よびその実装方法の提出を目的とする。This invention was made to solve the above problems,
In addition to preventing deformation of the leads during transportation and handling, the semiconductor device can be soldered to the board with sufficient bonding strength and mounted without using the conventional external solder supply method, simplifying the mounting process. The purpose of this research is to present semiconductor devices that can be used as standard devices and their mounting methods.
「課題を解決するための手段」
請求項Iに記載した発明は前記課題を解決するために、
複数のリードを備え、基板の導体に前記リートを半田付
けして実装される半導体装置において、隣接する複数の
リートを連続して覆う半IJ−]のブリッジ層によって
前記リードを覆ってなるものである。"Means for solving the problem" In order to solve the problem, the invention stated in claim I,
In a semiconductor device that is equipped with a plurality of leads and is mounted by soldering the leads to a conductor of a substrate, the leads are covered with a semi-IJ-] bridge layer that continuously covers a plurality of adjacent leads. be.
請求項2に記載した発明は前記課題を解決するために、
複数のり−トを備え、基板の導体にi7j記リートの端
末部を半田付けして実装される半導体装置において、前
記リードの端末部に、基板の導体表面への当接状態で導
体との間に半田溜間隙を形成する折曲部が形成されてな
り、隣接する複数のリードを連続して覆う半田のブリツ
ノ層によって前記リードを覆ってなるものである。In order to solve the above problem, the invention described in claim 2 has the following features:
In a semiconductor device that includes a plurality of leads and is mounted by soldering the terminal part of the lead to the conductor of the board, the terminal part of the lead is in contact with the conductor surface of the board. A bent portion is formed to form a solder reservoir gap, and a plurality of adjacent leads are covered with a solid layer of solder that continuously covers the leads.
請求項3に記載した発明は前記課題を解決するために、
請求項1記載の半導体装置を実装するに際し、そのリー
ドに付着されている厚膜半田メツキを溶融させてリード
を基板の導体に接合するものである。In order to solve the above problem, the invention described in claim 3 has the following features:
When mounting the semiconductor device according to the first aspect, the thick film solder plating attached to the leads is melted and the leads are bonded to the conductor of the substrate.
「作用 」
隣接するり−ドを半田のブリッジ層で連結した状態で覆
うので、リードをブリッジ層が補強し、リードの変形を
ブリッジ層が阻止する。``Function'' Adjacent leads are connected and covered with a bridge layer of solder, so the bridge layer reinforces the leads and prevents deformation of the leads.
また、リードの周囲に半田のブリッジ層を形成したので
、実装時に、リードを基板の導体に接触させた状態でこ
のブリッジ層を加熱して溶融させることで、溶融したブ
リッジ層の半田がリードの先端部と導体との接触部を覆
い、これによりリードと導体が接合する。従って、実装
時に新たに外部から半田を供給する必要がなくなるとと
もに、溶融した半田によって十分な強度でリードと基板
の導体とが接合される。In addition, since a bridge layer of solder is formed around the leads, during mounting, by heating and melting this bridge layer while the leads are in contact with the conductor of the board, the melted solder in the bridge layer is transferred to the leads. The contact portion between the tip and the conductor is covered, thereby joining the lead and the conductor. Therefore, there is no need to newly supply solder from the outside at the time of mounting, and the leads and the conductor of the board are bonded with sufficient strength by the molten solder.
以下、この発明を更に詳細に説明する。This invention will be explained in more detail below.
第1図と第2図は請求項1に記載した発明の一実施例を
説明するためのもので、この実施例の半導体装置11は
、多ピンパツケージICの本体部5の外周部に、多数の
リード(端子ピン)6 ・が延設されて構成されている
。これらのり−ト6は本体部5の内部の回路や素子に接
続されてなるもので、リード6は本体部5の側面から斜
め下方に延設されるとともに、その先端部6aは折り曲
げられていて、これらのり一ド6・・・を介して多ピン
パツケージICの本体部5が基板9の導体IIに接続さ
れるようになっている。1 and 2 are for explaining an embodiment of the invention as claimed in claim 1, and a semiconductor device 11 of this embodiment has a large number of chips on the outer periphery of a main body 5 of a multi-pin package IC. The leads (terminal pins) 6 are extended. These leads 6 are connected to the circuits and elements inside the main body 5, and the leads 6 extend diagonally downward from the side of the main body 5, and their tips 6a are bent. , the main body portion 5 of the multi-pin package IC is connected to the conductor II of the substrate 9 via these glues 6 .
この例の半導体装置Hは、リード6・・・を厚膜半田メ
ツキで覆ったものである。この発明での厚膜半田メツキ
とは、半田メツキの厚さ(第2図に示す厚さT)が十分
に厚く、15μm以」二のものを言う。従ってこの例の
半導体装置1−1のリート6 ・は、厚さ15μm以上
の厚膜半田メツキからなるブリッジ層8で覆われている
。なお、半導体装置Hの種類によってこのブリッジ層8
の厚さの好適範囲は変化するが、通フ;;°はI5〜数
百μmの範囲で実験的に決められ、接合強度の許容値の
下限以上の接合強度が得られれば十分である。In the semiconductor device H of this example, the leads 6 are covered with thick film solder plating. In the present invention, thick film solder plating refers to a solder plating having a sufficiently thick thickness (thickness T shown in FIG. 2) of 15 μm or more. Therefore, the lead 6 of the semiconductor device 1-1 in this example is covered with a bridge layer 8 made of thick film solder plating with a thickness of 15 μm or more. Note that depending on the type of semiconductor device H, this bridge layer 8
Although the preferred range of the thickness varies, the thickness is determined experimentally in the range of I5 to several hundred μm, and it is sufficient that the bonding strength is greater than the lower limit of the allowable bonding strength.
前記リード6・・に厚膜半田メツキを施してブリッジ層
8を形成するには、例えば、通常の電気半田メツキ法に
よって行なわれる。To form the bridge layer 8 by applying thick film solder plating to the leads 6, for example, a normal electric solder plating method is used.
第3図はQFPなどの多ビンパッケージICの多数のり
一ド6に、電気半田メツキを施ずための治具1を示ずも
のである。この治具Iは黄銅などの金属からなる4角形
状の上枠3と非導電体の下枠2とネジ4 ・とから構成
されている。FIG. 3 does not show a jig 1 for applying electrical solder plating to a large number of adhesives 6 of a multi-bin package IC such as a QFP. This jig I is composed of a rectangular upper frame 3 made of metal such as brass, a lower frame 2 made of a non-conductive material, and screws 4.
そして、第4図に示すように、その下枠2と上枠3との
間にQFPなどの多ピンパツケージICの本体部5のリ
ード6 ・を挾み、ネジ4・で固定したのち、この治具
1を半田メツキ浴Aに浸漬し、リード6・・・の大部分
が半田メツキ浴A中に浸されるように配置し、治具1を
陰極に、半田インゴット電極7を陽極として電気メツキ
することによって行なわれる。当然、メツキの府処理と
して脱脂洗浄工程などが行なわれる。Then, as shown in Fig. 4, the leads 6 of the main body 5 of a multi-pin package IC such as QFP are sandwiched between the lower frame 2 and the upper frame 3, and are fixed with screws 4. The jig 1 is immersed in the solder plating bath A, and the leads 6 are arranged so that most of them are immersed in the solder plating bath A, and the jig 1 is used as a cathode and the solder ingot electrode 7 is an anode. It is done by plating. Naturally, a degreasing and cleaning process is carried out as part of the final treatment for the wood.
この電気メツキ処理においては、リード6・・・の周囲
にメツキ層が順次堆積されるが、この堆積される各メツ
キ層の相互に隣接するものが接合一体化するまで電気メ
ツキを行うことで、ブリッジ層8を形成することができ
る。In this electroplating process, plating layers are sequentially deposited around the leads 6. By performing electroplating until adjacent ones of the deposited plating layers are joined and integrated, A bridge layer 8 can be formed.
前記メツキ浴Aの温度は20〜50°C1電流密度は2
〜] 5 A / dm2程度とすることが好ましいが
、これに限定されることはない。半田メツキの膜厚の制
御は、メツキ時間、メツキ浴温度、浴謡度、浴攪拌度合
等を綱部することによって行なわれる。The temperature of the plating bath A is 20 to 50°C, the current density is 2
~] 5 A/dm2 is preferable, but is not limited to this. The thickness of the solder plating film is controlled by controlling the plating time, plating bath temperature, bathing rate, bath agitation level, etc.
また、半田インゴット7、半田メツキ浴Δの合金組成は
、特に限定されることはなく、通常の錫60%、鉛40
%の半田などが用いられ、電気半田メツキで得られる半
田メッキ厚の合金組成も半田インゴットの組成と同一と
なる。Furthermore, the alloy composition of the solder ingot 7 and the solder plating bath Δ is not particularly limited, and is the usual 60% tin and 40% lead.
% solder is used, and the alloy composition of the solder plating thickness obtained by electric solder plating is also the same as the composition of the solder ingot.
以上のようにブリッジ層8により隣接するり一ド6・・
を覆う構成にするならば、リード6・・をブリツノ層8
が補強するので、運搬途中あるいは包装時などにおいて
リート6 ・に負荷がかかってもリード6・・が変形す
ることがない。As described above, the bridge layer 8 allows the adjacent boards 6...
If the structure is to cover the lead 6... with the lead layer 8
Since the lead 6 is reinforced, the lead 6 will not be deformed even if a load is applied to the lead 6 during transportation or packaging.
次に、前記構成のブリッジ層8を有する半導体装置の実
装方法について説明する。Next, a method for mounting a semiconductor device having the bridge layer 8 having the above structure will be described.
上述の半導体装置を基板に実装する場合、そのリード6
・・・に施された厚膜半田メツキのみを用いて半田付け
することができる。When mounting the above semiconductor device on a board, its leads 6
Soldering can be performed using only the thick film solder plating applied to ....
第1図は、この実装方法の一例を模式的に説明するため
のもので、図中符号9は、ICパッケージの本体部5が
実装される基板であり、この基板9は強化合成樹脂板な
どからなる基材10と、この基材10上に貼着された銅
箔などからなる導体11と、この導体II上に貼着され
たカバーフィルム12とからなるもので、リード6が接
合される部分ではカバーフィルム12が部分的に取り除
かれてパッド13となっている。FIG. 1 is for schematically explaining an example of this mounting method, and the reference numeral 9 in the figure is a substrate on which the main body 5 of the IC package is mounted, and this substrate 9 is a reinforced synthetic resin plate or the like. A conductor 11 made of copper foil or the like is pasted on the base material 10, and a cover film 12 is pasted on the conductor II, to which the leads 6 are joined. In some areas, the cover film 12 is partially removed to form a pad 13.
この基板9のパッド13には、第1図に示すように半田
ペーストなどの半田は塗布されておらず、導体11がそ
のまま露出している。As shown in FIG. 1, the pads 13 of the substrate 9 are not coated with solder such as solder paste, and the conductors 11 are exposed as they are.
そして、前記本体部5のリード6・・・が基板9のパッ
ド13の導体Ilに接触するように本体部5を基板9上
で位置合わせして載置し、この状態でリード6・・・に
向けて加熱空気を吹き付ける方法、熱圧着などの方法に
よって、リード6・・表面のブリッジ層8を溶融し、こ
の溶融半田でリード6と導体11とを接合し、実装が行
なわれる。Then, the main body part 5 is aligned and placed on the substrate 9 so that the leads 6... of the main body part 5 come into contact with the conductors Il of the pads 13 of the substrate 9, and in this state, the leads 6... The bridge layer 8 on the surface of the leads 6 is melted by a method such as blowing heated air toward the conductor 11 or by thermocompression bonding, and the leads 6 and the conductor 11 are joined with the molten solder to perform mounting.
このブリッジ層8を溶融した場合、溶融した半田はり一
ド6の表面張力によってリード6の周囲に集合しようと
するので、リード6.6の間をつなぐ部分の半田はとぎ
れて各リード6の周囲側に吸引され、リード6の先端部
6aと導体11との接触部分の周囲に滞留し、各リード
6と各導体11は接合される。従ってこの状態で隣接す
る各リード6・・は各々分離された状態で各々導体I+
に接合される。When this bridge layer 8 is melted, the molten solder tends to gather around the leads 6 due to the surface tension of the leads 6, so the solder at the portion connecting between the leads 6 and 6 breaks off and around each lead 6. It is attracted to the side and stays around the contact portion between the tip 6a of the lead 6 and the conductor 11, and each lead 6 and each conductor 11 are joined. Therefore, in this state, each adjacent lead 6... is separated from the conductor I+.
is joined to.
このような実装方法によれば、半導体装置Hと基板9と
の接合が半導体装置Hのリード6に予め施されたブリッ
ジ層8の半田によってのみ行なわれることになる。この
ため、実装時において、外部から別に半田を接合部分に
供給する必要がなければ、予め基板のパッドに半田ペー
ストを印刷、塗布する必要もない。従って、実装工程が
簡略化され、また自動機を用いた半田接合による半導体
装置の実装が可能になる。According to such a mounting method, the semiconductor device H and the substrate 9 are bonded only by the solder of the bridge layer 8 applied to the leads 6 of the semiconductor device H in advance. Therefore, during mounting, if there is no need to separately supply solder to the joint portion from the outside, there is no need to print or apply solder paste to the pads of the board in advance. Therefore, the mounting process is simplified, and the semiconductor device can be mounted by soldering using an automatic machine.
また、この発明によれば、ブリッジ層8の厚さを綱面す
ることで、個々の半導体装置毎に必要かつ十分な量の半
田を与えることができるので、半田付けによる半導体装
置Hの接合が確実に行える。Further, according to the present invention, by controlling the thickness of the bridge layer 8, it is possible to apply a necessary and sufficient amount of solder to each individual semiconductor device, so that the semiconductor devices H can be joined by soldering. You can definitely do it.
この点において従来の半田ペーストを基板のパッドに印
刷する方法では、基板のパッド毎に半田塗布量を変えて
適切な半田量を付与することは不可能であり、半導体装
置毎に適切な半田量を与えることはできない。In this respect, with the conventional method of printing solder paste onto the pads of a board, it is impossible to apply an appropriate amount of solder by changing the amount of solder applied to each pad of the board, and it is impossible to apply an appropriate amount of solder to each pad of the board. cannot be given.
更に、半導体装置としてQFPなどの多ピンパツケージ
のICの場合には、第2図に示すリード幅Wとリードピ
ッチPに応じた厚さの半田メツキを施すことで、十分な
接合強度が得られ、かつ、リード6.6間に半田による
ブリッジが生じることもなく、リードピッチが0.5m
m以下で0.3mmまでの狭いICでも半田付けによる
実装が可能である。特に、0.5mm未満のリードピッ
チのICを半田付けで実装することは、従来の半田の供
給方法によるものでは不可能であった。Furthermore, in the case of an IC with a multi-pin package such as a QFP as a semiconductor device, sufficient bonding strength can be obtained by applying solder plating to a thickness that corresponds to the lead width W and lead pitch P shown in Figure 2. , and there is no solder bridge between the leads 6 and 6, and the lead pitch is 0.5 m.
Even ICs as narrow as 0.3 mm or less can be mounted by soldering. In particular, it has been impossible to mount an IC with a lead pitch of less than 0.5 mm by soldering using conventional solder supply methods.
第5図は請求項1に記載した発明の第2実施例を示すも
ので、この例ではリード6・・の外周に、厚さが均一で
互いに連続する半田からなるブリッジ層8゛が被覆され
てなるものである。FIG. 5 shows a second embodiment of the invention as set forth in claim 1, in which the outer periphery of the leads 6 is coated with a bridge layer 8' made of solder that is uniform in thickness and continuous with each other. This is what happens.
この例の構造を採用した場合であっても先の例と同等の
効果を得ることができる。Even if the structure of this example is adopted, the same effect as the previous example can be obtained.
第6図は、請求項2に記載した発明の第1実施例を示す
もので、この実施例のり一ド61の先端部側には折曲部
62が形成されている。この折曲部62において、第1
図に示すリード6の先端部6aと異なるところは、その
折り曲げ角度である。FIG. 6 shows a first embodiment of the invention as set forth in claim 2, in which a bent portion 62 is formed on the tip end side of the glue 61 of this embodiment. At this bent portion 62, the first
The difference from the tip 6a of the lead 6 shown in the figure is the bending angle.
即ち、基板IC上の規定位置にICの本体部5を位置決
めして設置し、リード6Iの先端側を導体11の表面側
に設置した状態において、折曲部62と導体11との間
には半田溜間隙りが形成されるように折曲部62が形成
されている。That is, when the main body part 5 of the IC is positioned and installed at a specified position on the substrate IC, and the tip end of the lead 6I is installed on the surface side of the conductor 11, there is no space between the bent part 62 and the conductor 11. A bent portion 62 is formed to form a solder reservoir gap.
この例のり−ド61においては、先に説明した請求項I
に記載の発明の実施例と同等の効果を得ることができる
。In this example, on board 61, the above-described claim I
It is possible to obtain the same effect as the embodiment of the invention described in .
−1,1
また、この例の構造を採用した場合、ブリッジ層8を加
熱して溶融させた場合に生じた溶融半田が、前記半田溜
M隙りに表面張力によって吸引されて滞留し、固化する
。このため、隣接するり一ド61.61の間に存在する
ブリッジ層8は各リード61毎に十分に分離されてリー
ド61の先端部と導体11を完全に接合する。このよう
に半田溜間隙りに表面張力で半田を吸引すると、リード
61.61の間のブリッジ層8を完全に分離できるので
、隣接するリード61.61の間で短絡を起こすことが
ない。-1,1 In addition, when the structure of this example is adopted, the molten solder generated when the bridge layer 8 is heated and melted is attracted to the solder reservoir M gap by surface tension, stays there, and solidifies. do. Therefore, the bridge layer 8 existing between adjacent leads 61, 61 is sufficiently separated for each lead 61, and the tip of the lead 61 and the conductor 11 are completely joined. When the solder is drawn into the solder pool gap by surface tension in this manner, the bridge layer 8 between the leads 61, 61 can be completely separated, so that short circuits do not occur between adjacent leads 61, 61.
第7図は請求項2に記載した発明の第2実施例を示すも
ので、この例では、リード63の先端側にジグザグ型の
折曲部64を形成した構成である。FIG. 7 shows a second embodiment of the invention as set forth in claim 2, and in this example, a zigzag-shaped bent portion 64 is formed on the tip end side of the lead 63.
この例の構造においても先に記載した例と同等の効果を
得ることができる。With the structure of this example, the same effects as those of the previously described example can be obtained.
ところで前記各実施例において用いられるブリッジ層8
.8°を形成する手段はメツキ法に限るものではなく、
リードを変形させるおそれのないような手段であれば、
メツキ法以外の方法を用いても2−
差し支えない。By the way, the bridge layer 8 used in each of the above embodiments
.. The means of forming 8° is not limited to the Metsuki method;
If it is a method that does not cause the lead to become deformed,
2- There is no problem in using methods other than the Metsuki method.
「発明の効果」
以上説明したように本発明によれば、隣接するり−ドを
半田のブリッジ層で連結した状態て覆い、リードをブリ
ッジ層で補強し、リードの変形をブリッジ層が阻止する
ので、運搬や取り扱い時においてリードに多少の負荷が
かかった場合であっても、リードが変形することがない
。"Effects of the Invention" As explained above, according to the present invention, adjacent leads are connected and covered with a bridge layer of solder, the leads are reinforced by the bridge layer, and the bridge layer prevents deformation of the leads. Therefore, even if some load is applied to the reed during transportation or handling, the reed will not be deformed.
また、基板実装時において、ブリッジ層の半田のみで接
合できるので、新たに供給する半田が不要になり、実装
工程を簡略化することができるとともに実装コストを下
げることができる。また、基板実装工程において、半田
量と半田供給方法を考慮しなくとも良いことになるので
、半導体装置を基板上に位置決めし、リードの半田を溶
融することで容易に接合できる。更に、実装時にリード
に負荷をかけることがないので、リードを変形させるこ
ともない。更にまた、リードに形成するブリッジ層は均
一の厚さに形成することが容易にできるので、基板上に
半田を印刷する場合と異なり、各半導体装置ごとに適切
な半田量を容易に設定することができる。Further, when mounting on a board, bonding can be performed using only the solder of the bridge layer, which eliminates the need for newly supplied solder, which simplifies the mounting process and reduces mounting costs. Further, in the board mounting process, there is no need to consider the amount of solder and the solder supply method, so that the semiconductor device can be easily joined by positioning it on the board and melting the solder of the leads. Furthermore, since no load is applied to the leads during mounting, the leads will not be deformed. Furthermore, the bridge layer formed on the leads can be easily formed to have a uniform thickness, so unlike when printing solder on a board, it is easy to set the appropriate amount of solder for each semiconductor device. I can do it.
一方、リードピッチとリード幅の大きさに適合した半田
メツキ層を形成するならば、0 5mm以下の狭ピッチ
で多ピンタイプの半導体装置の半田付けであっても、ブ
リッジを生じることなく、十分な強度で接合できる効果
がある。On the other hand, if a solder plating layer is formed that matches the size of the lead pitch and lead width, even when soldering a multi-pin type semiconductor device with a narrow pitch of 0.5 mm or less, there will be no bridging. This has the effect of making it possible to bond with high strength.
更に、リードの先端部に折曲部を形成したものにあって
は、実装時において、基板の導体表面との間に形成され
る半田溜間隙に表面張力で半田を吸引できるので、隣接
するり−ド間に存在するブリッジ層を各リード毎に完全
に分離することができ、隣接するり一ド間で短絡を起こ
すことなく接合できる。Furthermore, when the lead has a bent part at its tip, surface tension can attract solder into the solder pool gap formed between the conductor surface of the board and the adjacent conductor surface during mounting. The bridge layer existing between the - leads can be completely separated for each lead, and adjacent leads can be joined without causing a short circuit.
第1図は請求項1に記載した発明の半導体装置の一実施
例を基板に設置した状態を示す断面図、第2図は同尖施
例のリードとブリッジ層を示す断面図、
第3図は請求項3に記載した発明の実施に用いる治具の
分解斜視図、
第4図は半導体装置のリードに厚膜メツキを施している
状態を示す断面図、
第5図は請求項Iに記載した発明の第2実施例の断面図
、
第6図は請求項2に記載した発明の第1実施例の断面図
、
第7図は請求項2に記載した発明の第2実施例の断面図
である。
A・・・半田浴、■4・・半導体装置、D・・・半田溜
間隙、■・・治具、5・・・多ピンパツケージICの本
体部、661.63・・・リード(ピン端子)、8,8
′・・・ブリッジ層、7・・・半田インゴット電極、9
・・基板、II・導体、62.64・・・折曲部。FIG. 1 is a cross-sectional view showing an embodiment of the semiconductor device of the invention as set forth in claim 1 installed on a substrate, FIG. 2 is a cross-sectional view showing the lead and bridge layer of the same-point embodiment, and FIG. is an exploded perspective view of a jig used for carrying out the invention set forth in claim 3; FIG. 4 is a sectional view showing a state in which thick film plating is applied to leads of a semiconductor device; and FIG. 5 is set forth in claim I. 6 is a sectional view of the first embodiment of the invention set forth in claim 2. FIG. 7 is a sectional view of the second embodiment of the invention set forth in claim 2. It is. A...Solder bath, ■4...Semiconductor device, D...Solder reservoir gap, ■...Jig, 5...Multi-pin package IC main body, 661.63...Lead (pin terminal) ), 8, 8
'... Bridge layer, 7... Solder ingot electrode, 9
...Substrate, II/Conductor, 62.64...Bending part.
Claims (3)
半田付けされて実装される半導体装置において、前記リ
ードが、隣接する複数のリードを連続して覆う半田のブ
リッジ層によって覆われてなることを特徴とする半導体
装置。(1) In a semiconductor device that includes a plurality of leads and is mounted by soldering the leads to a conductor of a substrate, the leads are covered with a solder bridge layer that continuously covers a plurality of adjacent leads. A semiconductor device characterized by:
端末部が半田付けされて実装される半導体装置において
、前記リードの先端部に、基板への装着状態で導体表面
との間に半田溜間隙を形成する折曲部が形成されてなり
、前記リードが、隣接する複数のリードを連続して覆う
半田のブリッジ層によって覆われてなることを特徴とす
る半導体装置。(2) In a semiconductor device that is equipped with a plurality of leads and is mounted by soldering the terminal ends of the leads to the conductors of the board, the ends of the leads are soldered between the ends of the leads and the surface of the conductor when attached to the board. A semiconductor device characterized in that a bent portion is formed to form a reservoir gap, and the lead is covered with a solder bridge layer that continuously covers a plurality of adjacent leads.
ードに付着されている半田のブリッジ層を溶融させてリ
ードを基板の導体に接合することを特徴とする半導体装
置の実装方法。(3) A method for mounting a semiconductor device, characterized in that when mounting the semiconductor device according to claim 1, a bridge layer of solder attached to the lead is melted to join the lead to a conductor of a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1223993A JPH0385751A (en) | 1989-08-30 | 1989-08-30 | Semiconductor device and its mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1223993A JPH0385751A (en) | 1989-08-30 | 1989-08-30 | Semiconductor device and its mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0385751A true JPH0385751A (en) | 1991-04-10 |
Family
ID=16806907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1223993A Pending JPH0385751A (en) | 1989-08-30 | 1989-08-30 | Semiconductor device and its mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0385751A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4754502B2 (en) * | 2004-02-24 | 2011-08-24 | ルノー・トラックス | Mechanical adapter assembly |
-
1989
- 1989-08-30 JP JP1223993A patent/JPH0385751A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4754502B2 (en) * | 2004-02-24 | 2011-08-24 | ルノー・トラックス | Mechanical adapter assembly |
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