JPH04127783A - Picture processor - Google Patents

Abstract

PURPOSE:To eliminate necessity for considering noise and to obtain the low- priced picture processor by fading in/out the two kinds of pictures respectively using a digital video data, and executing dissolve by a digital processing. CONSTITUTION:First and second memories 1 and 2 alternately write gradually increasing data for each V synchronization according to an address from a microcomputer 9, and third and fourth memories 3 and 4 similarly alternately write data gradually decreasing the other digital video data. These two systems of memories 1-4 are defined as a look-up table, fade-in data and fade-out data are read out corresponding to the digital video data of those pictures, and a data for dissolve is obtained by adding those data. Thus, a satisfactorily dissolved picture can be obtained without being affected by noise and further, the cost can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is used in video editing machines, etc., and gradually increases or decreases the levels of two types of video signals, respectively.
The present invention relates to an image processing device capable of dissolving images based on two types of video signals, each of which fades in one side and fades the other out.

[Conventional Example] Conventionally, in this type of image processing apparatus, a dissolve process in which one of two types of images is faded in and the other is faded out is performed by analog processing.

Fade-in and fade-out by the image processing device uses, for example, a sliding variable resistor, so it can be done at low cost, but since the variable resistance value is changed by sliding operation, for example, manually, [Problem to be Solved by the Invention] Therefore, in the above-mentioned image processing device, when attempting to automate the fade-in and fade-out, it is necessary to digitally control the analog control of the fade-in and fade-out. However, there was a problem in that the design, manufacturing, etc. had to be done with various considerations to noise.

This invention was made in view of the above-mentioned problems, and its purpose is to fade in and fade out two types of video using digital video data instead of analog, enable dissolve by digital processing, and take noise into account. The object of the present invention is to provide an inexpensive image processing device that does not require the above.

[Means for Solving the Problem] In order to achieve the above object, the present invention gradually increases one of two types of digital video data based on a video signal,
An image processing device capable of dissolving images based on two types of digital video data by gradually decreasing the other one, the number of bits of the digital video data corresponding to the number of bits of the digital video data,
First to fourth memories in which gradually increasing or gradually decreasing data can be written alternately, and the gradually increasing data or gradually decreasing data being alternately written to the first to fourth memories, respectively. 1st for
to the fourth buffer, and the data that has been gradually increased or decreased through the first or second buffer is transferred to the first buffer.
and alternately write and read data to and from the second memory, and alternately write and read data that is gradually increased or decreased via the third or fourth buffer to the third and fourth memories. A possible microcomputer, the address from this microcomputer, and the above two types of digital video data as part of the above video signal.
first to fourth selectors that are switched every synchronization and set as addresses of the first to fourth memories, output data of the first memory, output data of the second memory, and output of the third memory; It includes fifth and sixth selectors that switch between the data and the output data of the fourth memory every V synchronization, and an adder that adds the output data of the fifth and sixth selectors to obtain dissolve data. The main points are as follows.

Further, the image processing device of the present invention includes first and second memories capable of writing data that gradually increases or decreases in accordance with the number of bits of the digital video data alternately in different areas. and first and second buffers for alternately writing the gradually increased data or gradually decreased data into different areas of the first and second memories, respectively, and A microcomputer capable of increasing or decreasing the data gradually increased or decreased, and alternately writing and reading this data into different areas of the first and second memories, and a microcomputer capable of reading data from the microcomputer. first and second selectors that switch the address and the two types of digital video data at the rising and falling timings of synchronization of the video signal; and alternately read data from different areas of the first memory It is provided with an adder that adds the data and data alternately read from different areas of the second memory to obtain dissolve data.

[Function] With the above configuration, data that gradually increases every V synchronization is alternately written into the first and second memories according to the address from the microcomputer, and data is written into the third and fourth memories. Similarly, data that gradually decreases the other digital video data is written alternately. When writing that data, two types of digital video data are read from each memory, but
One side of these read data is faded in,
The other one is faded out. Then, the fade-in and fade-out data are added by the adder to obtain dissolve data.

In addition, the memory in which fade-in data and fade-out data are written is divided into two parts by the upper bits of the address from the microcomputer, and each area of one memory is filled with data that is gradually increasing according to the address, alternating during the vertical period. Similarly, the next decreasing data is written to each area of the other memory. Then, data in each area of the first and second memories is read out every V synchronization, and these read data, that is, fade-in data and fade-out data, are added by the adder, and dissolve data is obtained. can get.

[Embodiments] Hereinafter, embodiments of the present invention will be described based on FIGS. 1 to 7.

In FIG. 1, data that corresponds to the number of bits of two types of digital video data A and H and that are gradually increasing or decreasing are alternately written into the image processing device, and data that can be read from the first to The fourth memory (
RAM (look-up table) 1, 2, 3.4, and the gradually increasing or gradually decreasing data of one digital video data A are alternately stored in the first and second R.
A.M.I.

first and second buffer circuits 5 for writing to 2;
6, and third and fourth buffer circuits 7 and 8 for alternately writing gradually increasing or decreasing data of the other digital video data B into the third and fourth RAMs 3.4, respectively; The data that is gradually increasing or decreasing is transferred to the first or second buffer circuit 5.
. 4 RAM 3.4, and the first to fourth RAMI.

2. A microcomputer 9 capable of reading data 3 and 4 switches the address from the microcomputer 9 and the digital video data A every V synchronization, and
Alternatively, the first and second selector circuits 10 and 11 are used as the address of the second RAM 1.2, and the address from the microcomputer 9 and the digital video data B are switched, and the address of the third or fourth RAM 3.4 is switched. The data read out alternately from the first and second RAMI, 2 by the output addresses of the third and fourth selector circuits 12.13 and the first and second selector circuits 10.11 as addresses is A fifth selector circuit 14 that switches every synchronization, and third and fourth selector circuits 12.1
The first and second RAM 3.4 by the output address of 3.
Add the data alternately read out from the sixth selector circuit 15 that switches every synchronization, and the data selected by the fifth and sixth selector circuits 14 and 15;
An adder 16 that outputs dissolve data is provided.

Next, the operation of the image processing apparatus having the above configuration will be explained with reference to the second time chart, FIG. 3, and the fourth schematic diagram of the memory.

First, it is assumed that two types of digital video data A and B are obtained in the same synchronization before input, and one of the video data (digital video data A) is sent to the microcomputer 9.
Fade in L, fade out the other side (digital video data B)
It is assumed that the dissolve instruction for (out) has been issued.

Then, the microcomputer 9 alternately writes the gradually increasing data of the digital video data A into the first and second RAMs 1.2, and writes the gradually decreasing data of the digital video data B into the first and second RAMs 1.2. Control is performed to alternately write data into the third and fourth RAMs 4.5. At this time, the vertical synchronization of the video signal (Fig. 2 (a)
For example, first the first selector circuit 1
0 and the third selector circuit 12 are switched to the A input side, and the second selector circuit 11 and the fourth selector circuit 13 are switched to the B input side (FIG. 2(b)).

(c), (e)=shown in (f)). At the next V synchronization, the first selector circuit 10 and the third selector circuit 1
2 is switched to the B input side, and the second selector circuit 11
And the fourth selector circuit 13 is switched to the A input side.

Therefore, by the first V synchronization, the address of the microcomputer 9 is connected to the first RAMI, so that the gradually increased data obtained by the microcomputer 9 is transferred to the first RAMI via the first buffer circuit 5. RAM of
Written to 1.

Similarly, the address of the microcomputer 9 is the third R.
Since it is connected to AM3, its microcomputer 9
The gradually reduced data obtained in is written to the third RAM 3 via the third buffer circuit 7. In addition, by the next V synchronization, the address of the microcomputer 9 is connected to the second and fourth RAMs 2.4, and the data obtained by the microcomputer 9 and gradually increased is written to the second RAM 2. Then, the further gradually reduced data obtained by the microcomputer 9 is written into the fourth RAM 4 via the fourth buffer circuit N8.

In this way, the first and second RAMIs 2 are updated with alternately faded-in data, that is, data that gradually displays the "video" based on the digital video data A on the screen from "black" (see Figure 3). ), while the third and fourth
The RAM 3.4 is updated with alternately faded-out data, that is, data that gradually displays "black" on the screen from the "video" of digital video data B (as shown in FIG. 4).

In addition, as shown in FIG. 2 (h) to (k),
At that first V synchronization, the first and third buffer circuits 5,
7 is turned on, but during the vertical synchronization period, the second and fourth buffer circuits 6 and 8 are turned off (output 0P).
EN), and the second and fourth buffer circuits 6 and 8 are turned on at the next V synchronization, but during that vertical period, the first and third buffer circuits 5 and 7 are turned off. Ru.

Subsequently, when the gradually increased data is written to the first RAM 1 and the gradually decreased data is written to the third RAM 3, the second and third selector circuits 11 and 12 are connected to the B input side. It has been switched. As a result, digital video data A is set to the address of the second RAM2, and digital video data B is set to the address of the fourth RAM2.
4, and the second gradually increasing data and the gradually decreasing data of the fourth RAM 4 are read respectively. Furthermore, in the opposite case, that is, at the next V synchronization, the digital video data A is set to the address of the first RAMI, and the digital video data B is set to the address of the third RAMI.
3, and the gradually increasing data in the first RAMI and the gradually decreasing data in the third RAM3 are read out, respectively. That is, the first and second RAM
1.2 becomes a lookup table for obtaining gradually increasing data of digital video data A, and the third and fourth RAMs 3.4 become lookup data for obtaining gradually decreasing data of digital video data B. This is because

Subsequently, as shown in FIGS. 2(d) and (g), the fifth and sixth selector circuits 14.15
For example, the first and third
When reading data from RAMI, 3, it is switched to the input side, and when reading data from the second and fourth RAMs 2.4, it is switched to the B input side. Therefore, from the fifth selector circuit 14, digital video data A
The gradually increasing data of the digital video data B, that is, the fade-in data is outputted, and the gradually decreasing data of the digital video data B is outputted from the selector circuit 15 of the power cylinder 6.
In other words, fade-out data is output.

Since these gradually increased data and gradually decreased data are added by the adder 16, dissolve data for fading in the digital video data A and fading out the digital video data B is obtained.

This dissolve data first consists of only the "video" from digital video data B, then gradually overlaps that "video" with the "video" from digital video data A, and finally creates only the "video" from digital video data A. become.

In this way, in this invention, since the dissolve data for the two images is obtained using digital image data instead of analog signals, it is possible to obtain a good dissolve image without being affected by noise. effective.

FIG. 5 is a schematic block diagram of an image processing apparatus showing another embodiment of the present invention. In FIG. 1, the same parts and corresponding parts as in FIG. 1 are given the same reference numerals, and redundant explanation will be omitted.

In this figure, the image processing device is capable of sequentially and alternately writing and reading data corresponding to the number of bits of two types of digital video data A and B, each of which gradually increases or decreases, in different areas. The first
and a second memory (RAM; lookup table) 17, 18, and the gradually increasing or decreasing data of one digital video data A is stored in the first RA.
A first buffer circuit 19 for alternately writing data into different areas of M 17, and a second buffer circuit for writing data that is gradually increasing or gradually decreasing of the other digital video data B.
a first buffer circuit 20 for alternately writing data into different areas of the RAM 18, and a first selector circuit 21 for switching between the address from the microcomputer 9 and the digital video data A and setting it as an address for the first RAM 17; , the address from the microcomputer 9 and the digital video data B are switched, and the second
The second selector circuit 22 takes the address of the RAM 18 as
are provided.

Furthermore, in this embodiment, as shown in FIG.
When the digital video data A and B are 8 bits, the lower address of the microcomputer 9 (for example, OO(H
), . ; 9th bit) is input as is to the first and second RAMs 17 and 18. That is, two areas of 256 bytes (OFF (H)) are secured in each of the first and second RAMs 17.18, and these two different areas (A data section,
The gradually increased or gradually increased data is written and read out alternately in the B data section).

Next, the operation of the image processing apparatus having the above configuration will be explained with reference to the time chart shown in FIG.

First, as in the previous embodiment, it is assumed that two types of digital video data A and B are obtained in the same synchronization before input,
It is also assumed that a dissolve instruction to fade in one side of the video (digital video data A) and fade out the other side (digital video data B) is input to the microcomputer 9.

Then, when the microcomputer 9 detects the falling edge of vertical synchronization (V synchronization; shown in FIG. 2(a)),
The first and second selector circuits @ 21 and 22 are respectively switched to the input side (as shown in (b) and (c) of the figure), and the first and second buffer circuits 19 and 20 are switched to the input side.
It is brought into the N state (shown in (cl) and (e) of the same figure).

As a result, the address of the microcomputer 9 is stored in the first and second RAMs as shown in FIG.
17 and 18, and in the microcomputer 9, gradually increasing data of the digital video data A is alternately written into the A data section and the B data section of the first RAM 17 during a vertical period (approximately 1 m). . Also, gradually decreasing data of the digital video data B is alternately written into the A data section and the B data section of the second RAM 18 during the vertical period.

Subsequently, when the rising edge of the V synchronization is detected, the first
The second selector circuits 21 and 22 are switched to the B input side (shown in (b) and (c) of the figure), and the first and second buffer circuits 19 and 20 are in the OFF state (
In other words, the output is 0PEN) ((d) and (e) in the same figure).
). 29, the input digital video data A is stored in the first RAM 17 as shown in FIG.
address, and the input digital video data B is the second address.
Since the address of the first RAM 18 is
The data in the A data part and the B data part of the first RAM 17 are read out alternately every V synchronization, and the data in the A data part and B data part of the first RAM 17 are read out alternately every V synchronization. At this time, the address of the microcomputer 9 (IXX(H);
9th bit) is used.

Subsequently, the data read from the A data section or B data section of the first RAM 17 (fade-in data) and the data read from the A data section or B data section of the second RAM 18 (fade-out data) are Since the data are added by the adder 16, dissolve data similar to the previous embodiment can be obtained.

In this manner, this embodiment has the advantage that it can be easily put to practical use because the number of parts is smaller than the circuit of the previous embodiment.

[Effects of the Invention] As explained above, according to the image processing device of the present invention, there are two memories, one of which is sequentially updated with data that fades in the video, and the other that is sequentially updated with data that fades out the other video. 1 memory and these two systems of memory are used as lookup tables to read out fade-in data and fade-out data according to the digital video data of those images, and add these data to obtain dissolve data. , it is possible to obtain dissolve data that is not affected by noise, and it is possible to obtain a good dissolve image.

Furthermore, according to the present invention, only one memory is required for writing fade-in data and two memories for writing fade-out data, which reduces the number of circuit parts and facilitates practical application. Become.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an image processing device showing an embodiment of the present invention, and FIGS. 2 to 4 are time charts and schematic diagrams of RAM (memory) for explaining the operation of the image processing device. , FIG. 5 is a schematic block diagram of an image processing device showing another embodiment of the present invention, FIG. 6 is a schematic diagram of a RAM (memory) used in the image processing device of FIG. 5, and FIG. FIG. 6 is a time chart diagram for explaining the operation of the image processing apparatus shown in FIG. 5; In the figure, 1 and 17 are the first RAM section (memory), 2.1
8 is the second RAM section (memory), 3 is the third RAM section (
4 is a fourth RAM (memory), 5 and 19 are first buffer sections, 6 and 20 are second buffer sections, 7 is a third buffer section, 8 is a fourth buffer section, 9 is a microcomputer, 10.21 is a first selector circuit, 11
．． 22 is a second selector circuit, 12 is a third selector circuit, 13 is a fourth selector circuit, 14 is a fifth selector circuit, 15 is a sixth selector circuit, and 16 is an adder. Patent Applicant: Fujitsu General Co., Ltd. Representative, Patent Attorney: Takuya Ohara Fade Out

Claims (2)

[Claims] (1) An image processing device that gradually increases one of two types of digital video data based on a video signal and gradually decreases the other, and is capable of dissolving the image based on the two types of digital video data, wherein the digital video data first to fourth memories that can alternately write data that gradually increases or decreases corresponding to the number of bits; first to fourth buffers for writing to the first to fourth memories, and alternately writing data that is gradually increased or decreased to the first and second memories via the first or second buffer, and a microcomputer capable of reading and alternately writing and reading data that is gradually increased or decreased through the third or fourth buffer into the third and fourth memories; and an address from the microcomputer; and the two types of digital video data are switched every V synchronization of the video signal, and the first to fourth memory addresses are set as the addresses of the first to fourth memories.
to a fourth selector, a fifth selector for switching the output data of the first memory, the output data of the second memory, the output data of the third memory, and the output data of the fourth memory every V synchronization; An image processing device comprising: a sixth selector; and an adder that adds the output data of the fifth and sixth selectors to obtain dissolve data. (2) An image processing device capable of dissolving an image of two types of digital image data by gradually increasing one of two types of digital image data based on a video signal and gradually decreasing the other, wherein the digital image data first and second memories capable of alternately writing data that gradually increases or decreases in different areas corresponding to the number of bits; and first and second buffers for alternately writing to different areas of the first and second memories, respectively outputting gradually increased or decreased data through the first and second buffers, and , a microcomputer capable of alternately writing and reading the data into different areas of the first and second memories; first and second selectors that are switched respectively at the rising and falling timings of synchronization; and data that is alternately read from different areas of the first memory and data that is alternately read from different areas of the second memory. An image processing device comprising: an adder that adds the data to obtain dissolve data.