JPH04130778A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce problems of a leakage in a drain and a disturbance in the drain at the time of writing and to perform the stable writing by a method wherein a step is provided on an oxide film between a floating gate and a substrate. CONSTITUTION:A step is provided on an oxide film between a floating gate 2 of a memory transistor and a substrate. All operations of erase, writing and readout are identical with those in a conventional constitution. However, a capacity between the gate 2 and a drain 3 is reduced by making thick the film thickness of the oxide film between the gate 2 and the drain 3 and a leakage in the drain is reduced. Moreover, even if a potential difference between the potentials of the gate 2 and the drain 3 is the same as that in the conventional constitution, an electric field which is induced by the oxide film is considerably relaxed. As a result, a problem of a disturbance in the drain is also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory cell structure of a flash EEPROM, a nonvolatile semiconductor memory device that can be electrically written and erased.

[Conventional technology]

FIG. 2 is a sectional view of a memory cell of a flash EEPROM, and FIG. 3 is a block diagram of a conventional flash EEPROM. Control gate (1) in memory cell
It consists of a memory transistor consisting of two layers of floating gates (21).

Memory array i51 [Memory cells shown in FIG. 2 are arranged in rows and columns, and the drains (3) of the memory cells are connected to the bit lines (6), and the control gates 111 are connected to the word lines (7). So, source +41 is source? f
iA (connected to Iη. Floating gate i
The oxide film thickness between 2j and the substrate was 1100Aa degrees. This is the output of the word line a row decoder (9). bit line t4
Connected to Y-gate (8). The source line α is connected to the crab sauce line switch (11). The Y gate (8) is controlled by the Nicolumn decoder (lO) and controls the connection between the bit M (6) and the sense amplifier 3 write circuit Oz.

Row decoder (9).

Column decoder (lot ld address buffer (15)
1 output, one word line and one set of Y gates are selected.

Data written to the memory array (5) and data read from the memory array (5) are input and output via the input/output gate 7. Control circuit (+4) H controls the operation of each circuit block according to a control signal applied from outside.

Next, the operation will be explained. Erasing of data stored in the memory array (5) is performed all at once.

A higher voltage than the source line switch (Ill K is applied to the source +41 of all memory cells and grounded to the control gate fi+.A high electric field is applied to the oxide film between the floating gate (21) and the source (4), so the tunnel A current flows and the electrons accumulated in the floating gate (21) are removed.This lowers the threshold value of the memory transistor seen from the control gate (1).In other words, the state is the same as that of the EPROM after being erased by ultraviolet light. Writing is performed in the same way as in EPROM, and a high voltage pulse is applied to the drain (31 control gate) Ill of the memory transistor, and the source +41 is grounded.Electrons generated by avalanche collapse near the drain (3) are transferred to the floating gate (21 The control gate (If) is injected into the control gate (If) and becomes high to the threshold value of the memory transistor.

The high voltage required for erasing and writing is supplied from an external power source. In addition, the current flowing through bit MK during writing is Ico
A~5mA IC means that the current supply capacity is insufficient in high voltage generation circuits such as charge pumps.

Reading is performed by sensing whether current flows through the selected memory cell. At this time,
When a high potential is applied to the bit line, a floating gate (
A problem arises in that a high electric field is applied to the oxide film between 21 and the drain (31), causing friendly electrons accumulated in the floating gate (2) to escape.
) must be kept at a potential of 1 to 2 cm. A current sense amplifier is used to sense the current flowing through the memory cell while suppressing the drain (3) voltage.

[Problem to be solved by the invention]

As mentioned above, the conventional 7-latency EEPROM r H
, the oxide film thickness between the floating gate and the substrate is 100A.
Since it is formed thinly, the capacitance between the drain and the floating gate is larger than that of an EFROM. EPROM
In this case, the film thickness is equal to or larger than this film thickness azsoA. Therefore, during writing, the potential of the floating gate of the unselected cell increases due to capacitive coupling, so that a current flows again. This phenomenon is called drain leak, and the amount of this leak is larger than that of EFROM. This drain leakage occurs in memory cells in an erased state, ie, memory cells in a low red state. On the other hand, in a memory cell with high resistance in the saturated state, the potential difference between the drain and the floating gate becomes large and oxidation occurs.
The electric field induced in becomes stronger. For this reason, electrons tunnel through the oxide film and electrons stored in the floating gate escape to the drain. This is called drain disturb, and since the oxide film is thinner, flash EEFROM has a better EP.
It's tougher than ROM.

Let me explain drain starve in more detail.

FIG. 4 shows an equivalent circuit of a memory transistor.

Capacitance t between control gate and floating gate
ccy, floating gate to drain capacitance kcn
, 7o- The capacitance between the floating gate and the substrate is Cc, the capacitance between the floating gate and the source is C1, the amount of charge stored in the floating gate is QFO, and the potential applied to the control gate 'c Va *Drain, channel , source potential as Vn + Vc *
Vs, the floating gate potential VFG is expressed as o CCForhr, m CCF +
Co + Cc + Cs) Coupling ratio e
Expressed by Kc, let Kc=Ccy/Ctoy+u. Ti,
ΔV in the threshold shift amount seen from the control gate? 11--Qyo/CCF.

During writing, n Va -Vc -Vs m OV, so the potential difference between the floating gate and the drain (1
-Co/Cteoyaz)Vo + Kc ΔV? m
(MV/crn). Oxide film thickness between floating gate and substrate i 100A, long shift amount △V of memory cell in write state? ! If 5V,
Coupling ratio Kcwo 0.6 + CD 7t? o
th* f O,l, drain'i[q VD
If is 7■, an electric field of 9.3 MV/crn will be induced in the oxide film. If such a strong electric field is applied to the oxide film, a considerable tunnel current will flow.

[Means to solve all problems]

In the flash EEFROM according to the present invention, a step between the floating gate of the transistor and the oxide film VC between the substrate is provided by increasing the thickness of the oxide film on the drain side.

[Effect]

By providing the oxide film between the floating gate and the substrate of the flash gEPROM i memory transistor in this invention and making the thickness of the oxide film on the drain side less than Lf, the problems of drain leakage and drain disturb during writing can be completely reduced. [Embodiments of the Invention] FIG. 1 shows embodiments of the invention. A step is provided in the oxide film between the floating gate (21) and the substrate of the memory transistor. All operations of erasing, writing, and reading are the same as in the conventional example. However, the floating gate (21) and the drain ( 3) By thickening the oxide film @4 between the floating gate (21) and the drain (3), the device size between the floating gate (21) and the drain (3) is reduced and drain leakage is reduced.

Even if the potential difference between the floating gate (2) and the drain (31) is the same as in the conventional example, the problem of drain disturb is also alleviated because the blurring of the electric field induced in the oxide film is relaxed.

〔Effect of the invention〕

As described above, according to the present invention, since a step is provided in the oxide film between the floating gate and the substrate, the problems of drain leakage and drain disturb during non-writing are reduced, and stable writing is possible. be.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a memory cell according to an embodiment of the invention, Fig. 2 is a cross-sectional view of a conventional memory cell, and Fig. 3 is a μ-flash EE.
A block diagram of the PROM is shown in FIG. 4, which is a one-page circuit diagram similar to that in FIG. 2. In the figure, tllll''X control gate, f2!
14 floating gate, (31jd drain, [4
1:4 sauce. In addition, the same reference numerals refer to the same or corresponding parts.

Claims (1)

[Claims] Memory transistors each having a floating gate are arranged in an array in the row and column directions, the drain of each memory cell is connected to a bit line, the gate is connected to a word line, and the source is connected to a source line. A nonvolatile semiconductor memory device characterized by having a stepped oxide film.