JPH04174368A - Measuring circuit for delay time difference - Google Patents

Abstract

PURPOSE:To catch 50% of voltage values of two analog signals and thereby measure a delay time accurately by a method wherein the respective outputs of two circuits comparing an amplified signal with a shifted analog signal are subjected to exclusive OR. CONSTITUTION:A level detecting circuit 3 compares a signal (b) amplified 2 with a voltage inputted from a reference voltage input terminal 10 and outputs a signal (c) to a sample hold circuit 4. Besides, the circuit 4 catches correctly a instantaneous value of the voltage of the signal (b) which changes at a high speed and generates a signal (d). This signal is converted into a digital signal by an A/D converter 5 and passed over to a shift register 6. The register 6 shifts the input signal by 1 bit to the right and an output signal thereof is turned to be 50% of the input signal. This output signal is converted into an analog signal (e) by a D/A converter 7 and a level detecting circuit 8 compares the signal (b) with the signal (e) and generates a signal (f). The other circuit generates a signal (g) likewise, and by subjecting the signals to exclusive OR 9 respectively, a delay time is measured accurately.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a delay time difference measuring circuit.

[Conventional technology]

The conventional technique is to amplify two input signals using an amplifier to enlarge the waveforms of an oscilloscope, and capture and directly read 50% of each waveform.

[Problem to be solved by the invention]

Conventional delay time difference measuring circuits use an oscilloscope, so they have the disadvantage of requiring a lot of time for measurement.

[Means to solve the problem]

The delay time difference measurement circuit of the present invention includes a circuit that amplifies an input signal, a first level detection circuit that obtains a steep rising waveform at the point where the amplified signal crosses a reference voltage, and A sample hold circuit that holds values, an A/D converter that converts analog signals to digital signals, a shift register that moves input signals, and a D converter that converts digital signals to analog signals.
/A converter, and a second level detection circuit that compares the amplified signal with the output signal of the D/A converter and generates a pulse, and comprises two circuits of the above circuit configuration,
Exclusive pull Φ for each level detection circuit output
The delay time is measured by ORing.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each circuit section of the embodiment.

The signal a input to the signal input terminal 1 is input to the amplifier circuit 2.

The amplifier circuit 2 amplifies the signal a and generates the signal A. The signal is input to a level detection circuit 3, a level detection circuit 8, and a sample hold circuit 4.

The level detection circuit 3 compares the voltage input from the reference voltage input terminal 10 and generates a signal C.

The sample and hold circuit 4 accurately captures the instantaneous value of the voltage that changes at high speed, and generates the signal d.

The A/D converter 5 converts the signal d into a digital signal and transfers it to the shift register 6.

The shift register 6 shifts the input signal IBit to the right, that is, the data 10002 is now shifted to the right, resulting in data 01002, and the signal output from the shift register 6 is 50% of the signal before input. Become.

D/A converter 7 converts the signal output from shift register 6 into an analog signal and generates signal e.

The level detection circuit 8 compares the signal S and the signal e to generate a signal f.

〔Effect of the invention〕

As described above, the present invention has the advantage of being able to capture 50% of the voltage value of two analog signals that change moment by moment and accurately measure this.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each circuit section of the embodiment. DESCRIPTION OF SYMBOLS 1...Signal input terminal, 2...Amplification circuit, 3...Level detection circuit, 4-...Sample hold circuit, 5...
・A/D converter, 8 aha shift register, 7・
-D/A converter, 8- Level detection circuit, 9
...Exclusion pull ψOR circuit, 10--signal output terminal, ii--signal input terminal.

Claims (1)

[Claims] a circuit that amplifies an input signal; a first level detection circuit that obtains a steep rising waveform at a point where the amplified signal crosses a reference voltage; and a sample hold circuit that holds an instantaneous value of the amplified signal and rising waveform; An A/D converter that converts an analog signal into a digital signal, a shift register that moves an input signal, a D/A converter that converts a digital signal into an analog signal, and the amplified signal and the output signal of the D/A converter. It has a second level detection circuit that generates a pulse by comparing the two levels, and has two circuits with the above circuit configuration, and measures the delay time by exclusive-ORing the outputs of the respective level detection circuits. Delay time difference measurement circuit.