JPH04205154A - Microprocessor system - Google Patents

Abstract

PURPOSE:To make data which are high in use frequency reside at all times by providing a cache memory system with plural storage areas and storing at least part of address information, used to access a main storage, in the respective storage areas. CONSTITUTION:On a 1st cache memory 22, data stored in a tag memory 10 and a 1st data memory 12 are rewritten on condition that data corresponding to address information is not stored in the 1st data memory 12 when the address information is generated. On a 2nd cache memory 23, the stored data are rewritten independently of whether or not the data corresponding to the address information is stored in the tag memory 10 and 1st data memory 12. The 1st and 2nd cache memories 22 and 23 are switched to selectively exclude a data group from objects to be written. Consequently, the data which are used frequently such as instructions of an OS can be stored on the 2nd cache memory at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a cache memory in a microprocessor system.

[Conventional technology]

FIG. 4 is a schematic diagram of the internal blocks of a conventional microprocessor with a built-in cache memory, in which 1 is a microprocessor with a built-in cache memory (MPU);
is a cache memory section, 3 is a data calculation section, 4 is an instruction decoding section, 5 is a calculation section control signal based on the decoding result,
6 is a bus interface section for inputting instructions and data from the main memory etc., 7 is fetched data, and 8 is a data bus.

FIG. 3 is a block diagram showing a four-way set associative type cache memory for explaining the cache memory unit 2 of FIG. 4. In FIG.

In the figure, 9 is an input address to the cache memory, and the cache memory inputs address 9 to the address tag 9-
1, set select 9-2, and word select 9
-Enter in three parts. 10 is a tag memory, 11 is a valid bit, 12 is a data memory consisting of multiple entries and stores 4 words of data in one entry, 13 is an input address tag 9-1 and a tag memo 1/0, and determines whether or not they match. The address tag comparator 14 is based on the word select 9-3 given, based on the word select 9-3 contained in the data block of one entry)
15 is a word selector 1 for each way.
a way selector 16 for selecting one word data of the hit way from among the one word data selected by 4;
is LRU
d) Bit 17 is a way selection signal, and 18 is a hit signal indicating that data exists in the data memory 12 as a result of the comparison of the address tag 9-1.

The configuration of the cache memory in this figure is a 4-unit associative system, so between tag memories, valid bit 11, data memory 12, and address tag comparator 1.
3. There are four sets of word selectors 14 and way selectors 15 for each way.

Next, the operation will be explained. First, in FIG. 4, in a normal MPUI, the hash interface section 6 is connected to the data bus 8.
Instructions, data, etc. are fetched from main memory (not shown here) through the .

The fetched data 7 is sent to a decoding section 4 that decodes the meaning of the data. The decoding section 4 sends data for arithmetic processing and a control signal 5 to the arithmetic section 3 which performs arithmetic processing on the data according to the decoding result. Here, the cache memory section 2 temporarily stores data that is frequently accessed in the main memory by the instruction fetch section 6, and terminates the operation of the main memory when the data corresponding to the data requested by the instruction fetch section exists. , data is provided to the instruction fetch section 6 at a higher speed than when accessing the main memory through the data bus 8. The operation of this cache memory section 2 will be explained with reference to FIG. When a read access is performed from the instruction fetch unit 6 through the data bus 8, the cache memory unit 2 compares the address tag for each way with the data in the tag memory IO of the entry selected by the set select 9-2 of the input address 9. The signal is input to the device 13. Further, the address tag 9-1 of the input address 9 is read out as is to the address tag comparator 13 of each way. The results of the comparison by the address tag comparator 13 are output as a hit signal 18 and a way selection signal 17 indicating in which way the hit occurred. On the other hand, the 4-word data block read out for each way from the data memory 12 corresponding to the selected entry is processed by the word selector 14 for each way.
The word is selected, and finally, the way selector 5 receives the way selection signal 17 from the address tag comparator 13.
A word is determined and output to the data bus 8.

As described above (if there is a hit, the data is immediately read from the cache memory 2 and sent to the bus interface unit 6, or in the case of a cache miss, the main memory is accessed by the input address 9, and the data is Predetermined data is read out and used. At this time, the data is replaced in the cache memory 2, and the address tag 9-1 of the input address 9 and the data block read from the main memory are used. The data is written to the selected entry in the memory IO and the data memory 12. At the time of this data replacement, the LRU memory 16 controls whether to replace the data in the way according to the LRU algorithm that replaces the least frequently used data. ing.

Note that the valid bit 11 provided for each way and each entry indicates the validity of the data of the corresponding entry, and for entries whose valid hit 11 has been reset, even if a match of the address tag is detected. Even if it is, it will not be determined as a hit.

[Problem to be solved by the invention]

In the cache memory system built into conventional microprocessors as described above, if a cache miss occurs multiple times in a row for the same entry, the data of all ways held in that entry is evicted from the cache memory. I end up. Therefore, for example, data of a frequently used subroutine may be evicted from the cache memory while another routine is being executed due to an interrupt or the like. Therefore, when returning to the original subroutine, the data must be read from main memory again and stored in the cache memory (caching), making it impossible to effectively utilize the high-speed access function of the cache memory. There was a problem with not causing a drop in the performance of the entire system.

This invention was made to solve the above-mentioned problems, and aims to provide a microprocessor system with a built-in cache memory that allows frequently used subroutines to reside at all times. .

[Means to solve the problem]

In order to solve the above problems, a cache memory system built into a microprocessor according to the present invention is a cache memory system that temporarily stores data read from main memory, and has a plurality of storage areas. death,
a first address storage means that stores at least a part of address information used to access the main memory in each storage area; a first data storage means that stores data corresponding to the address information; and when address information is generated. a first determining means for determining whether or not data corresponding to the address information is stored in the data storage means; a first cache memory comprising a first rewriting means for rewriting data stored in the address storage means and data storage means; and a plurality of storage areas, each storage area being accessed by the main memory. second address storage means for storing address information used for
a second data storage means for storing data corresponding to address information; and a second determination means for determining whether data corresponding to the address information is stored in the data storage means when address information is generated. and a second cache memory comprising a second rewriting means for rewriting data stored in the address storage means and the data storage means independently of the determination result of the determination means, and when address information is generated, A selection means for selecting the first cache memory and the second cache memory, and a control means for controlling the operations of the first cache memory and the second cache memory by the selection means.

[Effect]

In this invention, the selection means and the control means are provided, and when address information is generated, the first address storage means responds to the fact that the data corresponding to the address information is not stored in the first data storage means. and a first cache memory for rewriting data stored in the first data storage means, and that data corresponding to the address information is not stored in the first address storage means and the first data storage means. By switching the second cache memory that rewrites independently stored data, data groups are selectively excluded from being rewritten, so for example, frequently used OS commands, etc. The data stored in the second cache memory can be stored at all times in the second cache memory.

〔Example〕

A schematic block diagram of the MPUI of the present invention is shown in FIG. In this figure, the following has been added to the block diagram shown in FIG. 4 in order to implement the present invention.

Reference numeral 19 indicates an area control register which is a data discrimination means; 20 indicates a register setting signal for setting conditions from the decoder section 4 to the area control register 19; and 21 indicates an area control register 1.
This is the area control register signal which is the setting content of No.9.

FIG. 1 is a block diagram for explaining a cache memory section 2 according to the present invention in FIG. 2. As shown in FIG.

In the figure, reference numeral 22 denotes a first cache memory section equivalent to the four-way set associative type cache memory shown in FIG. Reference numeral 23 denotes a second cache memory using a fully associative method that can operate independently of the first cache memory section. 9-4 is a full tag address which is part of the input address 9 given from the outside like the first cache memory. 24 stores the full tag address 9-4, and can also compare the stored contents with the input full tag address 9-4 during comparison operation.
This is the second TAG memory configured with DRESABLE MEMORY. 25 consists of multiple entries,
a second data memory storing 4 words of data in one entry; 26 an area control device which receives an area control register signal 21 which is an output signal of the area control register 19;
7 is an area control signal which is the output of the area control device 26; 28
is a data input/output control device that is controlled by an area control signal 27 and selectively outputs l word data output from the first cache memory section 22 and the second cache memory section 23; 29 is an area control signal; 27, and selectively outputs the hit signals output from the first cache memory section 22 and the second cache memory section 23, the hit signal device 30 is controlled by the second cache memory section 27. This is a FIFO control device that controls data replacement in the cache memory section 23 using a FIFO algorithm.

The operation when a read access is made to the cache memory section 2 will be explained using FIG. 1 and FIG. 2. Here, the cache memory section 2 shown in the conventional example is
The basic operation of is omitted.

When the decoding unit 4 detects a write command to the area control register 19 in the application program executed by the MPUI, that is, data to be made resident in the cache memory unit 2, the decoding unit 4 writes a value to the area control register 319 based on the decoding result. Set. This setting causes the area control register signal 21 to be asserted to the area control device 26. A region control signal 27 is asserted as the region control register signal 21 via a region control device 26.

When a read operation is performed in this state, the first cache memory section 22 and the second cache memory section 23 operate independently, and when a hit occurs in the second cache memory section 23,
The data input/output control device 28 is controlled by the area control signal 27.
and the hit signal control device 29 are controlled, and the hit signal 18-2 and data 8- are controlled from the second cache memory section 23.
2 is sent to the bus interface section 6.

When a miss occurs in the second cache memory unit 23, the hit signal 18-2 indicates the miss, and the external memory (not shown) is accessed to read out the necessary data, which is then sent to the bus interface unit 6. The data is stored in the corresponding second data memory 25 of the cache memory section 23. At the same time, the full tag address 9-4, which is part of the corresponding input address 9, is stored in the second TAG memory, regardless of the position of the entry that decoded the set select 9-2. Since the second cache memory section 23 has a fully associative configuration, the data and full tag address 9-4 are stored at F for all entries.
It is determined by the IFO control device 30.

However, if there is a hit in the first cache memory section 22, no access is made to the external memory;
1st. The hit data in the cache memory section 22 of the second cache memory section 22 is returned to the bus interface 6 and simultaneously stored in the second cache memory section 23.
The corresponding data in the cache memory unit 22 is made invalid.

Next, when the area control register 19 is reset, the area control register signal 2I to the area control device 26 is negated, and the area control signal 27 output from the area control device 26 is
is also negated. The data input/output control device 28 and the hit signal control device 29 are controlled by the area control signal 27.

When a read operation is performed in this state and a hit occurs in the first cache memory section 22, the first cache memory section 2
2 to hit signal 18-1. The data 8-1 is sent to the bus interface unit 6. If the first cache memory section 22 misses, the hint signal 18-1 indicates a miss, and the necessary data is read by accessing the memory externally, and the corresponding first cache memory section 22 is accessed by LRU control. The data is stored in the data memory 12. The operation within this first cache memory section 22 is the same as the operation of the cache memory section 2 shown in the conventional example.

At this time, if there is a hit in the second cache memory section 23, the external memory is not accessed and the second cache memory section 23 receives the hit signal 18-2 and the data 8.
-2 is returned to the bus interface 6. In this case, the data in the second cache memory section 23 is not stored again in the first cache memory section 22.

Regarding the above embodiments of the present invention, here we have explained the case where the setting to the area control register 19 or the rewriting instruction is decoded. However, if the addresses match, the data input to the data fetch unit 6 within the matched address range may be stored in the second cache memory unit 23. Alternatively, the setting signal may be received from the outside and stored in the memory section 23. Further, the same effect can be obtained even if the area control register 19 is set in response to a setting signal from the outside. Although a valid hit section is not shown in the second cache memory section 23, it may be provided.

The same effect can be obtained even if a cache memory that is not built into the microprocessor is controlled by writing a value to the area control register of the cache memory using the microprocessor as in the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, frequently used data such as O8 instructions can be kept in the cache memory at all times, and as a result, the high-speed access function of the cache memory can be effectively utilized. It is possible to improve the performance of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a cache memory section 2 according to the present invention, FIG. 2 is a schematic block diagram of an MPU 1 according to the present invention, and FIG. 3 is a conventional cache memory section 2.
Figure 4 is a block diagram for explaining the conventional MPUI.
FIG. In the figure, 19 is an area control register, 20 is a register setting signal, 21 is an area control register signal, 22 is a first cache memory section, and 23 is a second cache memory. 2
6 is an area control device, 27 is an area control signal, 28 is a data input/output control device, 29 is a human signal control device, 30 is an F
It is an IF○ control device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masu Oiwa Engraving of 11ji (no changes in content) Fig. 1 1: 'rYsonovmeF:') 7th page (Mazu7 [17')
Ot')7 (MPLI)

[Figure 3] Figure 41

Claims (1)

[Scope of Claims] 1. A cache memory system that temporarily stores data read from a main memory built into a microprocessor, the cache memory system built into the microprocessor having a plurality of storage areas. first address storage means for storing at least a part of address information used to access the main memory in each storage area; 2 a first memory storing data corresponding to the address information;
a data storage means, a first determination means for determining whether data corresponding to the address information is stored in the data storage means when address information is generated; and the determination means is the data storage means. a first cache memory comprising a first rewriting means for rewriting data stored in the address storage means and the data storage means in response to a result of determining that data corresponding to the data does not exist; a second address storage means having a plurality of storage areas and storing address information used for the main access in each storage area; when the address information is generated, data corresponding to the address information is stored; a second determining means for determining whether the data is stored in the data storing means; and a second determining means for rewriting the data stored in the address storing means and the data storing means independently of the determination result of the determining means. a second cache memory comprising second rewriting means for rewriting, a selection means for selecting the first cache memory and the second cache memory when address information is generated; A microprocessor system comprising a control means for controlling operations of a second cache memory and a second cache memory.