JPH04207233A - Diversity reception circuit - Google Patents

Diversity reception circuit

Info

Publication number
JPH04207233A
JPH04207233A JP2332376A JP33237690A JPH04207233A JP H04207233 A JPH04207233 A JP H04207233A JP 2332376 A JP2332376 A JP 2332376A JP 33237690 A JP33237690 A JP 33237690A JP H04207233 A JPH04207233 A JP H04207233A
Authority
JP
Japan
Prior art keywords
low
control signal
diversity
switching
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2332376A
Other languages
Japanese (ja)
Other versions
JPH07101857B2 (en
Inventor
Morikazu Sagawa
守一 佐川
Giichi Mori
森 義一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2332376A priority Critical patent/JPH07101857B2/en
Publication of JPH04207233A publication Critical patent/JPH04207233A/en
Publication of JPH07101857B2 publication Critical patent/JPH07101857B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To present a diversity reception circuit having a small circuit scale and a low current consumption by operating only one of plural low noise amplifiers in accordance with a diversity switching control signal. CONSTITUTION:The high frequency signal inputted from a high frequency input terminal 1 is demodulated by a double super-heterodyne consisting of a front end, which consists of a low noise amplifier 20 having the switching function and a first mixer 3, and an IF demodulator consisting of a first IF BPF 5 and following elements. The switching control signal inputted to a switching control signal terminal 22 is periodically determined or is determined by comparison with the reception level before the change for the purpose of coping with the quick drop of the reception electric field due to fading. A bias voltage generating circuit 2 generates a bias voltage in accordance with the switching control signal so that one low noise amplifier is operated, and this voltage is applied to the low noise amplifier 20 having the switching function.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、移動体通信に特有なフェージングを克服する
手段であるダイバーシチ受信回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a diversity receiving circuit which is a means for overcoming fading peculiar to mobile communications.

従来の技術 移動体通信に特有なフェージングを克服する手段として
、検波後選択ダイバーソチ受信回路か広く用いられてお
り、例えば、昭和57年電子情報通信学会通信方式研究
会資料C382−7なとに記載されている構成か知られ
ている。
Conventional technology As a means to overcome the fading peculiar to mobile communications, a post-detection selective diversort receiving circuit is widely used, and is described, for example, in the Institute of Electronics, Information and Communication Engineers Communication Systems Study Group Material C382-7 of 1981. The configuration is known.

以下第4図を参照して、従来のグイバーンチ受信回路に
ついて説明する。
A conventional guideline receiving circuit will be described below with reference to FIG.

第4図において、1は高周波入力端子、2は低雑音増幅
器、3は第1混合器、4は第1局部発振器、5は第1I
FBPF、5は第1IF増幅器、7は第2混合器、8は
第2局部発振器、9は第2IFBPF、10は第2IP
増幅器、11はリミッタ、12はディスクリミネータ、
13は切替制御器、14は復調出力端子である。
In FIG. 4, 1 is a high frequency input terminal, 2 is a low noise amplifier, 3 is a first mixer, 4 is a first local oscillator, and 5 is a first I
FBPF, 5 is the first IF amplifier, 7 is the second mixer, 8 is the second local oscillator, 9 is the second IFBPF, 10 is the second IP
amplifier, 11 is a limiter, 12 is a discriminator,
13 is a switching controller, and 14 is a demodulation output terminal.

高周波入力端子1から入力された高周波信号は、低雑音
増幅器2、第1混合器3から構成されるフロントエンド
と第11FBPF5以降のIF・復調部から成る2系統
のダブルス−パーヘテロダイン受信機により復調される
The high frequency signal input from the high frequency input terminal 1 is demodulated by a two-system double superheterodyne receiver consisting of a front end consisting of a low noise amplifier 2 and a first mixer 3, and an IF/demodulation section after the 11th FBPF5. be done.

移動体通信に特有なフェージングにより生しる受信電界
の急激な落ち込みは、受信S/Nの劣化をもたらすか、
この検波後選択ダイバーシチ受信回路では、切替制御器
13に入力される第2IF出力のレベルの大小により、
ブランチ切替を行い、レベルの高い方の復調出力を選択
して、復調端子14より出力することで、受信S/Hの
劣化を救済している。
Will the sudden drop in the received electric field caused by fading, which is unique to mobile communications, lead to deterioration of the received S/N?
In this post-detection selection diversity receiving circuit, depending on the level of the second IF output input to the switching controller 13,
Deterioration of the received S/H is relieved by performing branch switching, selecting the demodulated output with a higher level, and outputting it from the demodulating terminal 14.

発明か解決しようとする課題 しかし、以上のような構成では、フェージングによる受
信電界の急激な落ち込みによる受信S/Nの劣化は軽減
されるが、受信回路か2系統必要で、回路規模が大きく
なるとともに消費電流も倍増する。
Problem to be solved by the invention However, although the above configuration reduces the deterioration of the received S/N due to the sudden drop in the received electric field due to fading, it requires two receiving circuits and increases the circuit scale. At the same time, the current consumption also doubles.

本発明は、従来技術の以上のような課題を解決するもの
で、回路規模が小さく、消費電流も少ないダイバーシチ
受信回路を提供することを目的とするものである。
The present invention solves the above problems of the prior art, and aims to provide a diversity receiving circuit with a small circuit scale and low current consumption.

課題を解決するための手段 本発明は、受信機フロントエンド部に設けた複数の増幅
器群を、ダイバーシチ切替制御信号に応じて、1つの増
幅器のみを動作させるようにスイッチング機能を持たせ
ることで、受信感度、直線性が良好で、回路規模を大幅
に削減し、消費電流の低減を図ったダイバーシチ受信回
路を提供するという目的を達成するものである。
Means for Solving the Problems The present invention provides a switching function for a plurality of amplifier groups provided in a receiver front end section to operate only one amplifier in response to a diversity switching control signal. The object of the present invention is to provide a diversity receiving circuit that has good receiving sensitivity and linearity, has a significantly reduced circuit scale, and reduces current consumption.

作用 本発明は、受信機の性能を制するフロントエンド部の低
雑音増幅器をダイバーシチブランチ数に対応じて複数個
設け、前記複数の低雑音増幅器をグイバーンチ切替制御
信号に応じて、低雑音増幅器群のうち1つの増幅器のみ
を動作させ、他は非動作状態にするように低雑音増幅器
群にバイアス電圧を印加することで、受信感度を落とさ
ず、回路規模を大幅に削減し、消費電流の低減を図った
ダイバーシチ受信回路を実現している。
Effect of the Invention The present invention provides a plurality of low-noise amplifiers in the front-end section that control the performance of the receiver, corresponding to the number of diversity branches, and switches the plurality of low-noise amplifiers into a group of low-noise amplifiers in accordance with a yever branch switching control signal. By applying a bias voltage to a group of low-noise amplifiers so that only one amplifier is activated and the others are inactive, receiving sensitivity is not reduced, the circuit scale is significantly reduced, and current consumption is reduced. A diversity receiving circuit has been realized.

以上本発明は、受信機の低雑音増幅器をダイバーシチブ
ランチ数に対応じて複数個設け、切替制御信号に応じて
、低雑音増幅器群のうち1つのみを動作させるようにス
イッチング機能を持たせることで、受信感度、直線性が
良好で、回路規模を大幅に削減し、消費電流の低減を図
ったダイバーシチ受信回路を実現するものである。
As described above, the present invention provides a receiver with a plurality of low-noise amplifiers corresponding to the number of diversity branches, and has a switching function to operate only one of the low-noise amplifiers in response to a switching control signal. This provides a diversity receiving circuit with good receiving sensitivity and linearity, significantly reduced circuit scale, and reduced current consumption.

実施例 以下、図面を参照しながら本発明の第1の実施例につい
て説明する。
EXAMPLE A first example of the present invention will be described below with reference to the drawings.

第1図は、本発明の第1の実施例におけるダイバーシチ
受信回路を示すブロック図である。第1図において、2
0はスイッチング機能を有する低雑音増幅器、21はバ
イアス電圧発生回路、22は切替制御信号端子である。
FIG. 1 is a block diagram showing a diversity receiving circuit in a first embodiment of the present invention. In Figure 1, 2
0 is a low noise amplifier having a switching function, 21 is a bias voltage generation circuit, and 22 is a switching control signal terminal.

第4図と同一の番号を付したものは、第4図と同様の働
きをするものである。
Components with the same numbers as in FIG. 4 have the same functions as in FIG.

以上のような構成において、以下その動作について説明
する。高周波入力端子1から入力された高周波信号は、
スイッチング機能を有する低雑音増幅器20、第1混合
器3から構成されるフロントエンドと第1IFBPF5
以降のIP・復調部から成るダブルス−パーヘテロゲイ
ン受信機により復調される。
The operation of the above configuration will be explained below. The high frequency signal input from high frequency input terminal 1 is
A front end consisting of a low noise amplifier 20 having a switching function and a first mixer 3 and a first IFBPF 5
The signal is then demodulated by a double super-hetero gain receiver consisting of an IP demodulator.

フェージングにより生じる受信電界の急激な落込みに対
処するため、切替制御信号端子22に入力される切替制
御信号は、周期的あるいは変更前の受信レベルと比較さ
れるなどして決定される。
In order to cope with a sudden drop in the received electric field caused by fading, the switching control signal input to the switching control signal terminal 22 is determined periodically or by comparing it with the receiving level before change.

バイアス電圧発生回路21は、これにともなってとちら
か一方の低雑音増幅器のみが動作するようにバイアス電
圧を発生し、この電圧がスイッチング機能を有する低雑
音増幅器20に印加される。
Accordingly, the bias voltage generation circuit 21 generates a bias voltage so that only one of the low-noise amplifiers operates, and this voltage is applied to the low-noise amplifier 20 having a switching function.

この構成では、ダイバーシチブランチ数に対応じて、ス
イッチング機能を有する低雑音増幅器を複数個設け、そ
れを切替制御信号によって切り替える構成をとることで
、IF・復調部を1系統とすることができ、回路規模、
消費電流の大幅低減を図ることができる。また、低雑音
増幅器にスイッチング機能を持たせることで、低雑音増
幅器の前段にスイッチ回路を挿入する構成に比べ、雑音
指数の劣化が少ないばかりか、低雑音増幅器の後段にス
イッチ回路を挿入する構成に比較しても、低歪な受信機
が実現可能である。
In this configuration, a plurality of low-noise amplifiers with switching functions are provided corresponding to the number of diversity branches, and by switching them using a switching control signal, the IF/demodulator can be made into one system. circuit scale,
It is possible to significantly reduce current consumption. In addition, by providing a switching function to the low-noise amplifier, not only is there less deterioration in the noise figure compared to a configuration in which a switch circuit is inserted before the low-noise amplifier, but also a configuration in which a switch circuit is inserted after the low-noise amplifier. It is possible to realize a receiver with low distortion compared to the above.

以上の説明から明らかなように、本実施例によれば、ダ
イバーシチブランチ数に対応じて、スイッチング機能を
有する低雑音増幅器を複数個設け、それを切替制御信号
によって切り替えるという構成をとることで、IP・復
調部を1系統にすることかでき、回路規模を大幅に削減
し、消費電流の低減を図ることかできる。また、低雑音
増幅器にスイッチング機能を持たせることで、低雑音増
幅器の前段にスイッチ回路を挿入する構成に比較して、
良好な雑音指数が得られるばかりか、低雑音増幅器の後
段にスイッチ回路を挿入する構成に比較しても、少ない
電流で低歪な受信機が実現可能である。
As is clear from the above description, according to this embodiment, a plurality of low-noise amplifiers having a switching function are provided corresponding to the number of diversity branches, and by switching them using a switching control signal, The IP/demodulator can be combined into one system, which can significantly reduce the circuit scale and reduce current consumption. In addition, by providing a switching function to the low-noise amplifier, compared to a configuration in which a switch circuit is inserted before the low-noise amplifier,
Not only can a good noise figure be obtained, but also a receiver with lower distortion can be realized with less current than a configuration in which a switch circuit is inserted after a low-noise amplifier.

なお、以上の実施例では、復調回路にリミッタ・ディス
クリミネータ方式を用いたが、変復調方式には限定され
ないことは言うまでもない。
In the above embodiments, the limiter/discriminator method is used for the demodulation circuit, but it goes without saying that the present invention is not limited to the modulation/demodulation method.

次に本発明の第2の実施例について説明する。Next, a second embodiment of the present invention will be described.

第2図は本発明の第2の実施例においてダイバーシチ受
信回路の主要部であるスイッチング機能を有する低雑音
増幅器を示す図である。第2図(alは、電流制御回路
に3端子能動素子と抵抗からなる回路を用いたもの、同
図fblは電流制御回路を抵抗のみで構成したものであ
る。30は電源端子、31〜34はスイッチング用)く
イアス端子、35〜36は高周波入力端子、37は出力
端子、38は電流制御端子、40〜41は入力整合回路
、42は出力整合回路、Q1〜Q2はスイッチング用ト
ランジスタ、Q3〜Q4は高周波増幅用トランジスタ、
Q5は電流制御用トランジスタ、C1〜C3はバイアス
電圧供給用容量、C4はエミ・ツタ容量、R1は出力負
荷抵抗、R2−R6はバイアス電圧供給抵抗、R7−R
8は回路電流を決定する電流制御抵抗である。
FIG. 2 is a diagram showing a low-noise amplifier having a switching function, which is a main part of a diversity receiving circuit in a second embodiment of the present invention. Figure 2 (al is a current control circuit using a circuit consisting of a 3-terminal active element and a resistor, and fbl in the same figure is a current control circuit composed of only resistors. 30 is a power supply terminal, 31 to 34 (for switching) is a bias terminal, 35 to 36 are high frequency input terminals, 37 is an output terminal, 38 is a current control terminal, 40 to 41 are input matching circuits, 42 is an output matching circuit, Q1 to Q2 are switching transistors, Q3 ~Q4 is a high frequency amplification transistor,
Q5 is a current control transistor, C1 to C3 are capacitors for bias voltage supply, C4 is emitter capacitance, R1 is output load resistance, R2-R6 are bias voltage supply resistors, R7-R
8 is a current control resistor that determines the circuit current.

上記構成において、以下その動作について説明する。回
路電流の制御は、同図falでは電流制御端子38に印
加される電圧、電流制御用トランジスタQ5、電流制御
抵抗R7で、同図(blでは電流制御抵抗R8で行って
いる。同図[b)では電流制御トランジスタでの電圧降
下がなく、同図fa)に示した実施例に比べ、低い電源
電圧まで動作が可能になる。高周波入力端子35〜36
に入力された高周波信号は、入力整合回路40〜41を
経て、切替制御信号にともなって生成されるスイッチン
グ用バイアス電圧により、Ql、Q3のトランジスタ対
あるいはQ2、Q4のトランジスタ対のいずれかが動作
、他方は非動作状態となる。即ち、高周波入力端子35
〜36に入力された高周波信号のうち、どちらかが選択
されて、出力整合回路42を経由して出力端子37から
出力される。バイアス電圧供給用容量01〜C3、エミ
ッタ容量C4は、高周波接地を実現する容量である。
The operation of the above configuration will be explained below. The circuit current is controlled by the voltage applied to the current control terminal 38, the current control transistor Q5, and the current control resistor R7 in the figure fal, and by the current control resistor R8 in the figure (bl). ), there is no voltage drop in the current control transistor, and operation is possible up to a lower power supply voltage than in the embodiment shown in fa) of the same figure. High frequency input terminals 35-36
The high-frequency signal input to the input matching circuits 40 to 41 causes either the transistor pair Ql and Q3 or the transistor pair Q2 and Q4 to operate according to the switching bias voltage generated in conjunction with the switching control signal. , the other becomes inactive. That is, the high frequency input terminal 35
36 is selected and outputted from the output terminal 37 via the output matching circuit 42. The bias voltage supply capacitors 01 to C3 and the emitter capacitor C4 are capacitors that realize high frequency grounding.

以上の説明から明らかなように、本実施例によれば、ト
ランジスタを縦積みにし、切替制御信号により、どちら
か・一方のトランジスタ対のみを動作させるように、バ
イアス電圧を印加することで、IF・復調部を1系統と
することができ、回路規模を大幅に削減し、消費電流の
低減を図ることかできる。また、このように低雑音増幅
器にスイッチング機能を持たせることで、低雑音増幅器
の前段にスイッチ回路を挿入する構成に比へ、良好な雑
音指数が得られるばかりか、低雑音増幅器の後段にスイ
ッチ回路を挿入する構成と比較しても、少ない電流で低
歪な受信機が実現可能である。
As is clear from the above description, according to this embodiment, the transistors are stacked vertically, and the IF - The demodulation section can be reduced to one system, which can significantly reduce the circuit scale and reduce current consumption. In addition, by providing a switching function to the low-noise amplifier in this way, not only can a better noise figure be obtained compared to a configuration in which a switch circuit is inserted before the low-noise amplifier, but also a switch circuit can be inserted after the low-noise amplifier. Even compared to a configuration in which a circuit is inserted, a receiver with low distortion can be realized with less current.

次に本発明の第3の実施例について説明する。Next, a third embodiment of the present invention will be described.

第3図は本発明の第3の実施例においてダイバーシチ受
信回路の主要部であるスイッチング機能を有する低雑音
増幅器を示す図である。第3図において、第2図と異な
る点は3端子能動素子に2ゲートFETを用いた点であ
る。Q6〜Q7は高周波増幅、スイッチング両機能を兼
ねた2ゲートFETである。第2図と同一の番号を付し
たものは、第2図と同様の働きをするものである。
FIG. 3 is a diagram showing a low-noise amplifier having a switching function, which is a main part of a diversity receiving circuit in a third embodiment of the present invention. The difference between FIG. 3 and FIG. 2 is that a 2-gate FET is used as the 3-terminal active element. Q6 to Q7 are two-gate FETs that have both high frequency amplification and switching functions. Components with the same numbers as in FIG. 2 have the same functions as in FIG.

上記構成において、以下その動作について説明する。3
端子能動素子に2ゲートFETを用い、第1ゲートに高
周波入力を、第2ゲートにバイアス電圧を印加すること
で、第2図に示したトランジスタを縦積みした構成と同
じ効果が、少ない素子で得られる。
The operation of the above configuration will be explained below. 3
By using a 2-gate FET as a terminal active element, applying a high frequency input to the first gate and applying a bias voltage to the second gate, the same effect as the configuration of vertically stacking transistors shown in Figure 2 can be achieved with fewer elements. can get.

以上本実施例によれば、少ない素子数で、低雑音増幅器
にスイッチング機能を設けることが可能で、受信感度、
直線性が良好で、回路規模を大幅に削減し、消費電流の
低減を図ったダイバーシチ受信回路を実現できる。
As described above, according to this embodiment, it is possible to provide a switching function to a low-noise amplifier with a small number of elements, and the reception sensitivity and
It is possible to realize a diversity receiving circuit with good linearity, significantly reduced circuit scale, and reduced current consumption.

なお、以上の実施例ではダイバーシチブランチ数が2組
の例について示したか、Nは2以上の任意のN組の場合
にも適用できることは言うまでもない。
Note that although the above embodiments have been described with reference to an example in which the number of diversity branches is two, it goes without saying that the present invention can also be applied to any number of N groups in which N is two or more.

発明の効果 以上のように本発明は、ダイバーシチブランチ数に対応
じて、スイッチング機能を有する低雑音増幅器を複数個
設け、それを切替制御信号によって切替る構成をとるこ
とで、IP・復調部を1系統とすることができ、回路規
模を大幅に削減し、消費電流の低減を図ることかできる
。また、低雑音増幅器にスイッチング機能を持たせるこ
とで、低雑音増幅器の前段にスイッチ回路を挿入する構
成に比較して、良好な雑音指数が得られるばかりか、低
雑音増幅器の後段にスイッチ回路を挿入する構成に比較
しても、少ない電流で低歪な受信機が実現可能であり、
その工業的効果は大きい。
Effects of the Invention As described above, the present invention provides a plurality of low-noise amplifiers each having a switching function according to the number of diversity branches, and is configured to switch between them using a switching control signal, thereby improving the IP/demodulation section. It is possible to use only one system, which greatly reduces the circuit scale and reduces current consumption. Furthermore, by providing a switching function to the low-noise amplifier, not only can a better noise figure be obtained compared to a configuration in which a switch circuit is inserted before the low-noise amplifier, but also a switch circuit can be inserted after the low-noise amplifier. Even compared to the configuration in which the wire is inserted, it is possible to create a receiver with lower distortion using less current.
Its industrial effects are significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例におけるダイバーシチ受
信回路を示すブロック結線図、第2図は本発明のダイバ
ーシチ受信回路の主要部であるスイッチング機能を有す
る低雑音増幅器の第2の実施例を示す回路図、第3図は
本発明のダイバーシチ受信回路の主要部であるスイッチ
ング機能を有する低雑音増幅器の第3の実施例を示す回
路図、第4図は従来のダイバーシチ受信回路を示すブロ
ック結線図である。 20・・・低雑音増幅器、21・・・バイアス電圧発生
回路、22・・・切替制御信号端子、30・・・電源端
子、31〜34・・・スイッチング用バイアス端子、3
5〜36・・・高周波入力端子、37・・・出力端子、
38・・・電流制御端子、40〜41・・・入力整合回
路、42・・・出力整合回路、Q1〜Q2・・・スイッ
チング用トランジスタ、Q3〜Q4・・・高周波増幅用
トランジスタ、Q5・・・電流制御用トランジスタ、Q
6〜Q7・・・高周波増幅、スイッチング両機能を兼ね
た2ゲー1−FET5C1〜C3・・・バイアス電圧供
給用容量、C4・・・エミッタ容量、R1・・・出力負
荷抵抗、R2−R6・・・バイアス電圧供給抵抗、R7
−R8・・・電流制御抵抗。 第2図 第6図
FIG. 1 is a block diagram showing a diversity receiving circuit according to a first embodiment of the present invention, and FIG. 2 is a second embodiment of a low-noise amplifier having a switching function, which is the main part of the diversity receiving circuit according to the present invention. 3 is a circuit diagram showing a third embodiment of a low-noise amplifier having a switching function, which is the main part of the diversity receiving circuit of the present invention, and FIG. 4 is a block diagram showing a conventional diversity receiving circuit. It is a wiring diagram. 20...Low noise amplifier, 21...Bias voltage generation circuit, 22...Switching control signal terminal, 30...Power supply terminal, 31-34...Switching bias terminal, 3
5 to 36...high frequency input terminal, 37...output terminal,
38... Current control terminal, 40-41... Input matching circuit, 42... Output matching circuit, Q1-Q2... Switching transistor, Q3-Q4... High frequency amplification transistor, Q5...・Current control transistor, Q
6~Q7... 2-game 1-FET with both high frequency amplification and switching functions 5C1~C3... Capacitor for bias voltage supply, C4... Emitter capacitance, R1... Output load resistance, R2-R6...・Bias voltage supply resistance, R7
-R8...Current control resistance. Figure 2 Figure 6

Claims (6)

【特許請求の範囲】[Claims] (1)受信機フロントエンド部の低雑音増幅器をダイバ
ーシチブランチ数と同数個と切替制御信号に応じてバイ
アス電圧を生成するバイアス電圧発生器とを具備し、前
記複数の低雑音増幅器をダイバーシチ切替制御信号に応
じて、一つの低雑音増幅器のみを動作させるようにした
ことを特徴とするダイバーシチ受信回路。
(1) The front end of the receiver is equipped with the same number of low-noise amplifiers as the number of diversity branches and a bias voltage generator that generates a bias voltage according to a switching control signal, and the plurality of low-noise amplifiers are controlled by diversity switching. A diversity receiving circuit characterized in that only one low-noise amplifier is operated according to a signal.
(2)受信機フロントエンド部低雑音増幅器は、3端子
能動素子から構成されるダイバーシチブランチ数と同数
の増幅器群、前記増幅器群の共通の1端子に接続する電
流制御回路、前記増幅器群の出力側の端子を共通にし、
前記共通端子に接続される抵抗素子、切替制御信号に応
じてバイアス電圧が印加されるバイアス電圧端子とを具
備し、切替制御信号に応じて、前記増幅器群のうち1つ
の増幅器のみを動作させるようにしたことを特徴とする
請求項1記載ダイバーシチ受信回路。
(2) The receiver front-end low-noise amplifier includes a group of amplifiers of the same number as the number of diversity branches composed of three-terminal active elements, a current control circuit connected to one common terminal of the amplifier group, and an output of the amplifier group. Make the side terminals common,
A resistor element connected to the common terminal, and a bias voltage terminal to which a bias voltage is applied in accordance with a switching control signal, the amplifier being configured to operate only one of the amplifiers in accordance with the switching control signal. 2. The diversity receiving circuit according to claim 1, characterized in that:
(3)電流制御回路として3端子能動素子と抵抗からな
る回路を用いたことを特徴とする請求項2記載のダイバ
ーシチ受信回路。
(3) The diversity receiving circuit according to claim 2, wherein a circuit including a three-terminal active element and a resistor is used as the current control circuit.
(4)電流制御回路として抵抗からなる回路を用いたこ
とを特徴とする請求項2記載のダイバーシチ受信回路。
(4) The diversity receiving circuit according to claim 2, wherein a circuit made of a resistor is used as the current control circuit.
(5)3端子能動素子としてバイポーラトランジスタを
用いたことを特徴とする請求項2、3、4のいずれか記
載のダイバーシチ受信回路。
(5) The diversity receiving circuit according to any one of claims 2, 3, and 4, characterized in that a bipolar transistor is used as the three-terminal active element.
(6)3端子能動素子として2ゲートFETを用いたこ
とを特徴とする請求項2、3、4のいずれか記載のダイ
バーシチ受信回路。
(6) The diversity receiving circuit according to any one of claims 2, 3, and 4, characterized in that a 2-gate FET is used as the 3-terminal active element.
JP2332376A 1990-11-28 1990-11-28 Diversity receiver circuit Expired - Fee Related JPH07101857B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2332376A JPH07101857B2 (en) 1990-11-28 1990-11-28 Diversity receiver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2332376A JPH07101857B2 (en) 1990-11-28 1990-11-28 Diversity receiver circuit

Publications (2)

Publication Number Publication Date
JPH04207233A true JPH04207233A (en) 1992-07-29
JPH07101857B2 JPH07101857B2 (en) 1995-11-01

Family

ID=18254277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2332376A Expired - Fee Related JPH07101857B2 (en) 1990-11-28 1990-11-28 Diversity receiver circuit

Country Status (1)

Country Link
JP (1) JPH07101857B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6360077B2 (en) 1997-07-31 2002-03-19 Nec Corporation Mobile radio communication device provided with functions for detecting and informing interference

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199339A (en) * 1985-03-01 1986-09-03 Nec Corp Diversity radio equipment
JPS61206326U (en) * 1985-06-17 1986-12-26
JPH02131629A (en) * 1988-11-12 1990-05-21 Nec Corp Transmitter-receiver for frequency diversity
JPH02271724A (en) * 1989-04-12 1990-11-06 Nec Corp Space diversity receiver
JPH02138916U (en) * 1989-04-26 1990-11-20

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61199339A (en) * 1985-03-01 1986-09-03 Nec Corp Diversity radio equipment
JPS61206326U (en) * 1985-06-17 1986-12-26
JPH02131629A (en) * 1988-11-12 1990-05-21 Nec Corp Transmitter-receiver for frequency diversity
JPH02271724A (en) * 1989-04-12 1990-11-06 Nec Corp Space diversity receiver
JPH02138916U (en) * 1989-04-26 1990-11-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6360077B2 (en) 1997-07-31 2002-03-19 Nec Corporation Mobile radio communication device provided with functions for detecting and informing interference

Also Published As

Publication number Publication date
JPH07101857B2 (en) 1995-11-01

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