JPH04225457A - microcomputer - Google Patents

Abstract

PURPOSE:To attain a combined use between a real chip and an evaluation chip without occupying uselessly the external terminal of a package. CONSTITUTION:A microcomputer 1 includes a CPU 20 that shares the internal buses ABUS and DBUS and the peripheral circuits in a single chip. Then the microcomputer 1 is provided with a selection circuit 5 which connects selectively a prescribed external terminal 60 connected to the outside of the chip to a system evaluation-only signal terminal 2Ob of the CPU 20 or either one of individual signal terminals 4Ob and 41b of the circuits 40 and 41 respectively.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a microcomputer that is integrated into a single chip and includes a central processing unit and peripheral circuits, and particularly to a microcomputer that combines an existing circuit module with a new circuit module. The present invention relates to a technology that is effective when applied to the common use of commercial chips and real chips.

0002

[Prior Art] ASIC (Application Specific Integrated Circuit) is used to reduce the development cost and development period of semiconductor integrated circuits.
Or, considering methods such as standard cells, it is provided as a standard product by combining multiple macro cells that can be configured as an independent semiconductor integrated circuit or originally configured as an independent semiconductor integrated circuit. The inventor has attempted to form a new semiconductor integrated circuit by forming a custom module designed according to a user's individual specifications on the same semiconductor substrate together with a macro cell.

For example, a network processor (HD64180S) manufactured by Hitachi, Ltd. is used as a core unit, and a custom module is added along with the same unit.
Furthermore, a microcomputer is constructed by expanding some of the peripheral circuit functions included in the core unit with separate modules.

An example of a document describing the HD64180S is an 8-bit microprocessor by "Nikkei Data Pro Microprocessor" MC1-104-501-505 (July 1989).

[0005]

[Problem to be Solved by the Invention] However, when a core unit is combined with a custom module or a function expansion module to satisfy the user's required specifications, the functions or types of the microcomputer vary widely.
If a new system evaluation chip was designed and provided for each type by emulation or the like, it would take time to develop the evaluation chip, and the preparation of the environment for system evaluation would be delayed. However, if the actual chip is configured in such a way that external pins for input or output of evaluation-only signals are arranged in advance, the number of external pins on the package will increase due to the trend toward system-on-chip technology or an increase in the scale of integration. It is virtually impossible to achieve this due to constraints,
Moreover, it becomes difficult to use.

[0006] Furthermore, when configuring a microcomputer to reflect user custom logic and replace the functions of some peripheral circuits included in the core unit with a high-function expansion module, it is also possible to connect the core unit to the outside. If the interface of the microcomputer is different from that of a microcomputer in which the same core unit is integrated into a semiconductor integrated circuit, it is necessary to reuse the test pattern of the core unit already provided in the functional diagnosis of the microcomputer that reflects the user's custom logic. This makes it difficult to create test patterns for the LSI itself, and a great deal of effort is required to create test patterns for the LSI itself.

An object of the present invention is to provide a microcomputer that can serve as both an actual chip and an evaluation chip without unnecessarily occupying the external terminals of the package.

Another object of the present invention is to provide a microcomputer in which a test pattern developed for another microcomputer can be easily used for diagnosis of a logic section borrowed from another microcomputer. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0010

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

In other words, from the viewpoint of dual use of the evaluation chip and the actual chip, a predetermined external terminal connected to the outside of the chip can be connected to either the system evaluation dedicated signal terminal of the central processing unit or the individual signal terminal of the peripheral circuit. A selection circuit that can be selectively connected is provided to configure a microcomputer that includes a central processing unit and peripheral circuits on one chip.

[0012] From the viewpoint of using both the evaluation chip and the actual chip and making it possible to use test patterns for other microcomputers for diagnosis of logic parts that have been used from other microcomputers, a custom module etc. is installed in the core unit. When configuring a microcomputer that satisfies user specifications by combining the above, the individual signal terminals of a predetermined peripheral circuit included in the core unit, the individual signal terminals of a peripheral circuit located outside the core unit, or the central processing unit A selection circuit is provided that selectively connects a predetermined external terminal connected to the outside of the chip to any of the signal terminals dedicated to system evaluation.
It constitutes a microcomputer included in a chip.

From the viewpoint of making it possible to use test patterns for other microcomputers in diagnosing logic parts borrowed from other microcomputers, we have developed a microcomputer that satisfies user specifications by combining the core unit with custom modules. When configuring a computer, a predetermined external terminal connected to the outside of the chip is attached to either an individual signal terminal of a predetermined peripheral circuit included in the core unit or an individual signal terminal of a peripheral circuit arranged outside the core unit. A microcomputer including a central processing unit and peripheral circuits on one chip is constructed by providing a selection circuit for selectively connecting the two.

[0014]

According to the above-described means, in the operation mode used as a real chip, the selection circuit interfaces the individual signal terminals of the predetermined peripheral circuits with the outside to enable the desired system operation. In the operating mode used as an evaluation chip, the selection circuit allows evaluation-dedicated signal terminals to interface with an emulator or the like to support system evaluation.

[0015] When a microcomputer is configured by incorporating custom logic so that the functions of some of the peripheral circuits included in the core unit are replaced by another function expansion module, reflecting the user custom logic, During system operation as a real chip, the selection circuit interfaces individual signal terminals of predetermined peripheral circuits included in the function expansion module with the outside to enable desired system operation. When diagnosing the functionality of a microcomputer, the selection circuit allows the individual signal terminals of peripheral circuits in the core unit whose functions have been replaced by the function expansion module to be interfaced with the outside, so that test patterns for the core unit that have already been provided can be used. Make it.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a network processor 1 according to an embodiment of the present invention. The network processor 1 shown in the figure includes a processing core module 2,
User custom module 3, function expansion module 4,
and a selection circuit 5, which are formed on one semiconductor substrate such as single crystal silicon by known semiconductor integrated circuit manufacturing techniques.

The processing core module (hereinafter simply referred to as core module) 2 has a function as a general-purpose microcomputer equipped with a serial communication interface function, which is already provided as a single microcomputer, and in particular, Although not limited to, CPU (Central Processing)
Multi-protocol, serial, and multi-protocol units that can support multiple communication protocols such as HDLC
Communication Interface (hereinafter simply MSC)
(also referred to as I) 21, Asynchronous Serial Communication Interface (hereinafter also simply referred to as ASCI) 22, which performs asynchronous communication control; Direct Memory Access Controller (hereinafter also referred to as I) which performs direct memory transfer control of communication data. (also simply referred to as DMAC) 23, 24, two timers 25, 26, and a memory management unit 27 that converts logical addresses inside the processing core module 2 into physical addresses.
, and an input/output circuit 28 for exchanging information with the outside of the core module 2, which are commonly connected to an internal bus represented by an address bus ABUS and a data bus DBUS.

The function expansion module 4 includes, for example, two MSCIs 40 and 41, and the data bus DBUS
It is commonly connected to an internal bus such as an address bus ABUS, and is controlled by the CPU 20.

The user custom module 3 includes, but is not particularly limited to, an input/output circuit 30 for exchanging information with the core module 2, as shown in FIG.
It also has an input/output circuit 31 for exchanging information with the outside of the chip via a group of external terminals 34 such as pad electrodes. The input/output circuits 30 and 31 are the bus switch circuit 3
2, an external terminal group 35 such as a pad electrode can alternatively be connected to the
The connection is controlled by an arbitration circuit 33 that arbitrates between access requests from the input/output circuit 30 side and access requests from the input/output circuit 31 side to avoid access conflicts.

The network processor 1 of this embodiment includes:
The user custom module 3 is on-chip so as to reflect the user custom logic centering on the core module 2, and some peripheral circuits included in the core module 2, such as the ASCI 22 and the timer 26, are not required, and the same functions or Expansion module 4 with high functionality of the same circuit
It has the property of being configured as a microcomputer that satisfies the specifications required by the user. In this way, when configuring the microcomputer 1 that reflects user custom logic, the ASCII 2
2. The timer 26 may be deleted from the chip, but the core module 2 is already provided with a mask pattern etc.
has been adopted as is. Therefore, when the microcomputer 1 operates on the system to which it is applied (system operation), the individual signals of the ASCI 22 and the timer 26 do not need to be interfaced with the outside,
The individual signals of MSCIs 40 and 41 included in the function expansion module 4 need to be interfaced with the outside.

Here, the individual signals of the peripheral circuits are strobe signals, timing signals, etc. that each peripheral circuit individually exchanges with circuits outside the LSI. for example,
In MSCI21, 40, 41 and ASCI22, it is used as a synchronization signal, transmission/reception signal, etc., and timer 25, 2
In the case of 6, the signal is used as a timer input signal or a timer output signal, and in the case of the DMACs 23 and 24, it is used as a DMA request signal, a DMA completion signal, etc. In FIG. 1, individual signals in each peripheral circuit are 21a, 22a, 23a.
, 24a, 45a, 26a, 40a, 41a, and individual signal input or output terminal groups in the respective peripheral circuits are shown as 21b, 22b, 23b, 24b, 45b, 2
6b, 40b, 41b.

[0022] The CPU 20 is previously equipped with a function of inputting and outputting evaluation-dedicated signals for emulation. This evaluation-only signal is not particularly limited, but when the emulator (not shown) detects a break condition, the CPU 2
A break interrupt signal (input signal) to stop the emulation operation by 0, a break acknowledge signal (output) to notify the outside that a break interrupt has been accepted, and a break acknowledge signal (output) to notify the outside that it is an instruction fetch cycle. The emulation load instruction register signal changes at a faster timing than the normal load instruction register signal, and the normal memory enable signal changes at a faster timing than the normal memory enable signal that informs the outside that it is a memory access cycle. Memory for emulation
It is considered to be an enable signal, a logical address, etc. This evaluation-only signal is illustrated at 20a in FIG.
The data is input/output to the outside of the CPU 20 from the input or output terminal group (evaluation-only terminal group) indicated by .

The selection circuit 5 selects a predetermined group of external terminals 60 such as pad electrodes connected to the outside of the chip from the CPU.
20 evaluation-dedicated signal terminal groups 20b, individual signal terminal groups 22b and 26b of the ASCI 22 and timer 26 arranged in the core module 2, or individual signal terminal groups 40b of the MSCI 40 and 41 arranged outside the core module 2,
41b, for example, the first
It has a selector 50 and a second selector 51. The first selector 50 is in a first state where the ASCI 22 and the timer 26 are connected to the second selector 51, or the MSCI 40, 41
A second state in which the second selector 51 is made conductive is alternatively selected. The second selector 51 selectively selects a third state in which the CPU 20 is electrically connected to the external terminal group 60 or a fourth state in which the first selector 50 is electrically electrically connected to the external terminal group 60. The state selection by the first selector 50 is controlled according to the logical value of a control bit assigned to one bit of an appropriate register, for example, a register included in the MSCI 40. Further, the second selector 51 selects the third state when the emulation mode is set in the CPU 20, and selects the fourth state when the normal mode is set. Although the operating mode of the CPU 20 is not particularly limited, it is determined by the level of a predetermined mode signal 62 supplied from an external terminal 61 such as a pad electrode.

FIG. 3 shows a communication control system to which the network processor 1 of this embodiment is applied.

In FIG. 3, 10 is a system bus;
The host CPU 11, main memory 12, network processor 1 of this embodiment, etc. are coupled to this. This network processor 1 is connected to the system bus 10.
In addition to this, it is also interfaced with the local bus 13 and shared memory 14. This network processor 1 is also considered as one of the local communication control modules, and the local bus 13 is connected to the user custom module 3 and the core module 2.
are commonly connected to both through an external terminal group 62. This local bus 13 includes, for example, a local memory 15 and an I
An SDN controller 16 and the like are combined. The shared memory 14 is a buffer memory shared by the CPU 20 in the core module 2 and the upper CPU 11, and is, for example, a buffer memory shared by the core module 2 and the function expansion module 4.
It is used as a temporary storage area for data received and transmitted by the serial communication interface included in the . This shared memory 14 is connected to the external terminal group 35, and the user custom module 3 performs arbitration control to determine whether the shared memory 14 is accessed by the CPU 20 or the host CPU 11.

When the network processor 1 of this embodiment is operated as a real chip on a system as shown in FIG. 3, the normal mode is set in the CPU 20 by the mode signal 62. Thereby, the external terminal group 60 is electrically connected to the first selector 50. Then, by writing logic "0", for example, to a predetermined control bit, the first selector 50 is caused to select the second state, and the individual signals 40a and 40a of the MSCIs 40 and 41 included in the function expansion module 4,
41a can be input or output to the outside of the processor 1 via the external terminal group 60. This enables network processor 1 to operate according to user custom logic. At this time, the timer 26, which cannot exchange individual signals with the outside, can be used for timing detection inside the chip. Note that by setting the predetermined control bit to logic "1", it is also possible to use the ASCI 22 and timer 26 in the core module 2 instead of the function expansion module 4 by directly interfacing with the outside.

When performing software evaluation for a system such as that shown in FIG. 3, the emulation mode is set in the CPU 20 by the mode signal 62. This allows the external terminal group 60 to input and output evaluation-only signals via the second selector 51. The network processor 1 set in such an emulation mode is connected as an evaluation chip to an emulator (not shown) and the evaluation target system, and controls the evaluation target system on behalf of the system, and outputs trace information etc. that can trace the control operation to the emulator. do. In system evaluation using this emulation, although the MSCIs 40 and 41 cannot directly exchange individual signals with the outside via the terminal groups 40b and 41b, they operate in an internal loop mode that connects the transmitting section and the receiving section. This allows software debugging of the communication control program. Even when using the timer 26 and the ASCI 22, software debugging of the communication control program can be performed using the loop mode.

When diagnosing the function of the network processor 1, the normal mode is set and the first selector 50
selects the first state, thereby allowing the processing core module 2 to use the test pattern already provided. Function expansion module 4
and user custom modules 3, functional diagnosis is performed using test patterns dedicated to individual modules.

According to the above embodiment, the following effects can be obtained.

(1) The network processor 1 of this embodiment has the user custom module 3 and the function expansion module 4 on-chip so as to reflect the user custom logic around the core module 2, thereby satisfying the user required specifications. However, in the normal mode used as a real chip, the selection circuit 5 interfaces the individual signal terminals 40b and 41b of the function expansion module 4 with the outside to achieve the desired system operation that meets the user's requirements. In the emulation mode used as an evaluation chip, the selection circuit 5
The evaluation-dedicated signal terminal 20b of the PU 20 is interfaced with an emulator or the like to support system evaluation. Therefore, in the network processor 1 that integrates a large number of circuit modules, even though the number of external terminals of the package is limited, the external terminals of the package can be used for both the actual chip and the evaluation chip without occupying them unnecessarily. .

(2) The ASCI 22 and timer 26 included in the core module 2 reflect the user custom logic.
In the network processor 1 in which the function expansion module 4 is combined with the core module 2, the function expansion module 4 is substituted for the individual signal utilization function of the network processor 1.
During system operation as a real chip, the selection circuit 5 connects the individual signal terminals 40b and 4 of the function expansion module 4.
1b is interfaced with the outside to enable the desired system operation. When diagnosing the function of the processor 1, the selection circuit 5 connects the ASCI 22 in the core module 2,
Since the individual signal terminals 22b and 26b of the timer 26 can be interfaced with the outside, it is possible to perform functional diagnosis by reusing the test pattern of the core module 2 that has already been provided. Therefore, the number of man-hours required for creating test patterns for the processor 1 for new development can be reduced.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof. stomach.

For example, the emulation mode setting is not limited to using the dedicated mode signal 62;
The mode may be set by a combination of signal levels such as existing strobe signals in the CPU. Further, the circuit blocks included in the core module, function expansion module, and user custom module are not limited to the above embodiments, and can be modified as appropriate. Also, 1
When the LSI in which the network processor 1 is packaged as a chip is used exclusively for the actual chip, the external terminals 61 are not bonded to the lead terminals of the package.
It can be bonded to a predetermined power supply terminal using a bonding option, or connected to a predetermined power supply wiring using a master slice. Further, in order to use it exclusively as an evaluation chip, the external terminal 61 may be fixed to a potential opposite to that described above. In order to make the assembled LSI available for use as both an actual chip and an evaluation chip, the external terminals 62 are bonded to the lead terminals of the package.

The present invention can also be applied to a technique for dedicating the chip itself to a real chip. For example, in FIG. 1, the first selector is directly coupled to the external terminal group 60, and the second selector 51 is eliminated.

[0035] In the above explanation, the invention made by the present inventor was mainly applied to a network processor, which is the background field of application.
The present invention is not limited thereto, and can be widely applied to various microcomputers.

The present invention is broadly applicable to conditions that are diversified to reflect, at least in part, custom logic.

[0037]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, since the evaluation signal terminals and the individual signal terminals of the peripheral circuits that do not need to be used during evaluation can be selectively interfaced with outside the chip, it is possible to implement them without wasting the external terminals of the package. This has the advantage that it can be used as both a chip and an evaluation chip.

Furthermore, since it is possible to selectively adopt the external interface state for operating the logic part borrowed from another microcomputer as it is, when diagnosing the logic part borrowed from another microcomputer, the This has the effect that test patterns developed in 1998 can be easily reused, and the number of man-hours required to create test patterns for a microcomputer that reflect user custom logic can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a network processor as an embodiment of a microcomputer according to the present invention.

FIG. 2 is a block diagram of an example of a user custom module included in a network processor.

FIG. 3 is a block diagram of an example system configuration to which a network processor is applied.

[Explanation of symbols]

1 Network processor 2 Processing core module 3 User custom module 4 Function expansion module 5 Selection circuit 20 CPU 20b Evaluation-only signal terminal 21 MSCI 21b Individual signal terminal 22 ASCII 22b Individual signal terminal 23 DMAC 23b Individual signal terminal 24 DMAC 24b Individual signal terminal 25 Timer 25b Individual signal terminal 26 Timer 26b Individual signal terminal 40 MSCI 40b Individual signal terminal 41 MSCI 41b Individual signal terminal 50 1st selector 51 Second selector 60 External terminal

Claims (3)

[Claims] 1. A single-chip microcomputer including a central processing unit and a peripheral circuit that share an internal bus, wherein the central processing unit has an input or output terminal for a signal dedicated to system evaluation, and the central processing unit has an input or output terminal for a signal dedicated to system evaluation; Part or all of the circuit has individual signal input or output terminals that are not connected to the internal bus, and a predetermined external terminal connected outside the chip is connected to the evaluation-dedicated signal terminal of the central processing unit or the peripheral circuit. A microcomputer comprising a selection circuit that can be selectively connected to either one of the individual signal terminals. 2. A microcomputer integrated into one chip including a central processing unit and peripheral circuits that share an internal bus, wherein the central processing unit and some of the peripheral circuits form a core unit, and the core unit Predetermined peripheral circuits included in the core unit and peripheral circuits arranged outside the core unit each have individual signal input or output terminals that are not connected to the internal bus, and the central processing unit inputs or outputs signals dedicated to system evaluation. having a terminal and selectively connecting a predetermined external terminal connected to the outside of the chip to any of the evaluation-dedicated signal terminal, the individual signal terminal of the peripheral circuit within the core unit, or the individual signal terminal of the peripheral circuit outside the core unit; A microcomputer comprising a selection circuit. 3. A single-chip microcomputer including a central processing unit and peripheral circuits that share an internal bus, wherein the central processing unit and some of the peripheral circuits form a core unit, and the core unit Predetermined peripheral circuits included in the chip and peripheral circuits arranged outside the core unit each have individual signal input or output terminals that are not connected to the internal bus, and predetermined external terminals connected to the outside of the chip are connected to the core. A microcomputer comprising a selection circuit selectively connected to either an individual signal terminal of a peripheral circuit within the unit or an individual signal terminal of a peripheral circuit outside the core unit.