JPH0423148U - - Google Patents
Info
- Publication number
- JPH0423148U JPH0423148U JP6364590U JP6364590U JPH0423148U JP H0423148 U JPH0423148 U JP H0423148U JP 6364590 U JP6364590 U JP 6364590U JP 6364590 U JP6364590 U JP 6364590U JP H0423148 U JPH0423148 U JP H0423148U
- Authority
- JP
- Japan
- Prior art keywords
- areas
- photoconductive material
- insulating layer
- layer
- gate array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims description 4
- 238000009429 electrical wiring Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は一実施例のゲートアレイにおける１つ
のＭＯＳトランジスタ部分を示す平面図、第２図
は第１図のＡ−Ａ線位置での断面図、第３図は同
実施例で配線を形成する方法を示す断面図、第４
図は同実施例に配線が形成された状態を示す平面
図、第５図は従来の配線が形成されたＭＯＳトラ
ンジスタを示す平面図、第６図は第５図のＢ−Ｂ
線位置での断面図である。
２……基板、４……ソース領域、６……ドレイ
ン領域、８……ゲート酸化膜、１０……ゲート電
極、１２……絶縁膜、１４，１６……コンタクト
ホール、１８……スルーホール、２０……光導電
物質層、２３……マスク、２４，２６，２８……
露光により形成された配線。
Fig. 1 is a plan view showing one MOS transistor part in a gate array of one embodiment, Fig. 2 is a sectional view taken along line A-A in Fig. 1, and Fig. 3 is a wiring formed in the same embodiment. Sectional view showing the method of
The figure is a plan view showing a state in which wiring is formed in the same embodiment, FIG. 5 is a plan view showing a MOS transistor with conventional wiring formed, and FIG. 6 is B-B in FIG.
It is a sectional view at a line position. 2... Substrate, 4... Source region, 6... Drain region, 8... Gate oxide film, 10... Gate electrode, 12... Insulating film, 14, 16... Contact hole, 18... Through hole, 20...Photoconductive material layer, 23...Mask, 24, 26, 28...
Wiring formed by exposure.
Claims (1)
、基本セル上には絶縁層が形成され、絶縁層上に
は光導電物質層が形成され、この光導電物質層は
前記絶縁層のコンタクトホール又はスルーホール
を介して基本セル又は配線と接続されているゲー
トアレイ。 (2) 光導電物質層は、電気配線を行なう部分に
光が当たりそれ以外の部分には光が当たらないパ
ターンをもつマスクを用いて露光され、光が当た
つた部分が電気的配線となる請求項１に記載のゲ
ートアレイ。[Claims for Utility Model Registration] (1) A basic cell of a semiconductor device is formed on a chip, an insulating layer is formed on the basic cell, a photoconductive material layer is formed on the insulating layer, and this photoconductive material A gate array in which the layer is connected to basic cells or wiring through contact holes or through holes in the insulating layer. (2) The photoconductive material layer is exposed using a mask with a pattern that allows light to hit the areas where electrical wiring is to be carried out and prevents light from hitting other areas, and the areas that are exposed to light become the electrical wiring. The gate array according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6364590U JPH0423148U (en) | 1990-06-15 | 1990-06-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6364590U JPH0423148U (en) | 1990-06-15 | 1990-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0423148U true JPH0423148U (en) | 1992-02-26 |
Family
ID=31593883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6364590U Pending JPH0423148U (en) | 1990-06-15 | 1990-06-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0423148U (en) |
-
1990
- 1990-06-15 JP JP6364590U patent/JPH0423148U/ja active Pending
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