JPH04267456A - Common bus system - Google Patents

Abstract

PURPOSE:To make a simultaneous transmitting function possible to write the same data to plural processors with one writing operation and to shorten the data transfer time. CONSTITUTION:A simultaneous signal transmission line 5 is provided in a common bus. When data are transmitted from a processor 8 at a transmitting side to processors 6 and 7 at a receiving side, the processors 6 and 7 respond to the access when the signal transmission line 5 is a TTL high level and inactive, as the output of a ready signal to show data writing execution completion, with active low. The processors 6 and 7 respond to the access when the signal transmission line 5 is a TTL low level and active, with active high.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common bus system used for information transfer between processors in a multiprocessor system.

0002

2. Description of the Related Art Conventionally, this type of common bus system did not have a method for one processor to simultaneously transfer the same data to a plurality of other processors, that is, it did not have a broadcast transmission function.

Block diagrams showing the configuration of an example of the prior art are shown in FIGS. 4 and 5, and a timing chart showing the operation is shown in FIG.

FIG. 4 shows an information processing device configured with a common bus according to the prior art, and the common bus includes an address signal line 1, a data line 2, a write signal line 3, and a ready signal line 4.
In this example, there are four processors 6, 7, 8, 9.
are connected to a common bus. FIG. 5 is a diagram showing the configuration of main parts of the processor in FIG. 4. In this figure, processor 8 is a processor that writes data, processors 6 and 7 are processors to which data is written, and processor 8 has a write signal generation circuit 20. have ready signal output buffers 40 and 41, respectively. The ready signal output buffers 40 and 41 are open collector outputs.

Next, the operation when the processor 8 writes to the inter-processor communication memory of the processor 6 will be explained. As shown in FIG. 6, the processor 8 that performs writing outputs the address and data, and then activates the write signal from the write signal generation circuit 20. In this example, it is active low. The processor 6 that has received the address, data, and write signal uses an address determination function (not shown) to determine whether or not the access is to its own interprocessor communication memory, and if so, the It executes writing to the memory and outputs an active low ready signal to the ready signal line 4 via the output buffer 40 to notify the completion of the execution.

On the other hand, the processor 7 uses an address determination function (not shown) to determine that the access is not to its own memory for inter-processor communication, and does not perform writing and does not notify completion of execution. Processor 8 receives this active low signal on ready signal line 4, recognizes the completion of writing, and deactivates the write signal. Through the above operations, writing from the processor 8 to the processor 6 is executed. In the case of such a method, even if the address determination functions (not shown) of the processors 6 and 7 simultaneously determine that a specific broadcast address is an access to their own interprocessor communication memory, The write execution itself changes in time depending on the operating state of each processor.

[0007]

[Problems to be Solved by the Invention] In the conventional common bus system described above, processor 8 sends a write signal in response to the ready signal of whichever of processors 6 and 7 completed execution and issued the ready signal first. The disadvantage is that a processor that attempts to run late will not be able to perform the correct write operation. In other words,
Conventional common bus systems do not have a broadcast transmission function, so the only way to send the same data to multiple processors is to transfer the same data multiple times to each processor. The disadvantage was that it took a long time to transfer the data.

An object of the present invention is to provide a common bus system that enables a broadcast transmission function to write the same data to multiple processors in a single write operation and can shorten data transfer time. .

[0009]

[Means for Solving the Problems] In the common bus system of the present invention, first and second processors are connected to a common bus, and this common bus includes an address line for transmitting address signals and a common bus for transmitting data. a data line, a write signal line for transmitting a write signal, and a ready signal line for transmitting a ready signal indicating completion of write execution, and each of the processors is capable of writing and reading from the common bus. In a common bus system in an information processing apparatus having a multiprocessor configuration that has an inter-processor communication memory and transfers information between the first and second processors, the common bus includes a broadcast signal line for broadcast communication. and when transmitting data from the first processor on the transmitting side to the second processor on the receiving side, the second processor outputs the ready signal by setting the broadcast signal line to TTL high level. It responds to an access when it is inactive with an active low signal indicating that an event has occurred, and responds with an active high signal that indicates that an event has occurred to an access when the broadcast signal line is active at the TTL low level. It is configured to do this.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention, in which a common bus includes an address signal line 1 for transmitting address signals, a data line 2 for transmitting data, It is composed of a write signal line 3 for transmitting a write signal, a ready signal line 4 for transmitting a ready signal indicating completion of write execution, and a broadcast signal line 5 for broadcast communication. In the example, 4 processors 6, 7
, 8, and 9 are each connected to a common bus.

FIG. 2 is a diagram showing the configuration of the main parts of the processor in FIG. 1. In this figure, processor 8 is a processor that writes broadcast data, and processors 6 and 7
shows the case of a processor to which broadcast data is written. The processor 8 inputs a write signal generation circuit 20, a broadcast signal generation circuit 21, an input buffer 31 that receives a write completion ready signal, and a signal having the opposite polarity of the output of the input buffer 31 and the output of the input buffer 31. Broadcast signal line 5
It has a selector 26 that outputs one of these two inputs depending on the state. Output REA of selector 26
DY is a write completion notification to the processor that instructed the write, is active high, and is connected to the broadcast signal line 5.
If is TTL "high level", the output of the input buffer 31 is selected and output as is. That is, if either the gate 22 or the gate 23 is TTL "low level", READY becomes "high level", and the processor 8 recognizes the notification of completion by the ready signal as active high. If the broadcast signal line 5 is at TTL "low level", the opposite polarity of the output of the input buffer 31 is selected and output as READY. That is, both gate 22 and gate 23 are T.
If TL is "high level", READY is "high level" and the processor 8 recognizes the notification of completion by the ready signal as active high.

The processors 6 and 7 receive an internal write execution completion signal RDY output from a memory control section (not shown) of the processor and a signal of opposite polarity to RDY, and depending on the state of the broadcast signal line 5, , has selectors 24 and 25 that output one of these two inputs, and open collector output gates 22 and 23 that input the output of the selector and the output of the write signal line and output a ready signal to the ready signal line 4. are doing. In the figure, the RDY signal is an active high signal. The output of the selectors 24 and 25 is that the broadcast signal line 5 is T.
If TL is "high level", active high RDY is output, and active low is output to the ready signal line 4 via gates 22 and 23. When the broadcast signal line 5 is at the TTL "low level", the selectors 24 and 25 output an active low RDY, and output the active high signal to the ready signal line 4 via the gates 22 and 23.

Next, the operation of the processor 8 writing broadcast data to the processors 6 and 7 will be explained with reference to FIGS. 2 and 3. First, the processor 8 outputs a broadcast address and broadcast data as shown in FIG. 3, and at the same time outputs a write signal from the write signal generation circuit 20 and a broadcast signal from the broadcast signal generation circuit 21. At this time, the selector 26 of the processor 8
selects the opposite polarity of the output of input buffer 31. That is, when both gates 22 and 23 are at TTL "high level", READY becomes active high.

[0015] The processors 6 and 7 recognize the broadcast address by an address determination function (not shown), and write the address into their respective memory for inter-processor communication,
A ready signal notifying completion is output to the ready signal line 4. At this time, since the broadcast signal line 5 is at TTL "low level", the gates 22 and 23 output active high. Therefore,
Even if one processor completes writing and outputs active high to ready signal line 4, ready signal line 4 remains low until the other processor completes writing. When the other processor completes writing and outputs active high to the ready signal line 4, the ready signal line 4 becomes TT.
L becomes "high level", the processor 8 recognizes the completion of writing, makes the write signal and broadcast signal inactive, and completes the operation.

Although this embodiment shows the case where data is transferred to two processors at the same time, it can be implemented in the same way even if there are three or more processors.

[0017]

As explained above, the present invention provides a broadcast signal line for broadcast communication on a common bus, and transmits data from a first processor on the transmitting side to a second processor on the receiving side. When the second processor outputs a ready signal, the second processor responds with an active low signal indicating that an event has occurred in response to an inactive access when the broadcast signal line is TTL high level, and the second processor outputs a ready signal when the broadcast signal line is TTL high level. Since the configuration is configured to respond with an active high signal indicating that an event has occurred in response to an access when the low level is active, it enables a broadcast transmission function that writes the same data to multiple processors with a single write operation. Data transfer time can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of main parts of the processor in FIG. 1;

FIG. 3 is a timing chart showing the operation of an embodiment of the present invention.

FIG. 4 is a diagram showing the configuration of a conventional common bus system.

FIG. 5 is a diagram showing the configuration of main parts of the processor in FIG. 4;

FIG. 6 is a timing chart showing the operation of a conventional common bus system.

[Explanation of symbols]

1 Address signal line 2 Data line 3 Write signal line 4 Ready signal line 5 Broadcast signal line 6, 7, 8, 9 Processor 20 Write signal generation circuit 21 Broadcast signal generation circuit 22, 23 Open collector output gate (O
/C) 24, 25, 26 Selector (SEL) 31
input buffer

Claims (1)

[Claims] 1. The first and second processors are connected to a common bus, and the common bus includes an address line for transmitting an address signal, a data line for transmitting data, and a data line for transmitting a write signal. a write signal line and a ready signal line for transmitting a ready signal indicating completion of write execution; each processor has an inter-processor communication memory capable of writing and reading from the common bus;
and a common bus system in an information processing apparatus having a multiprocessor configuration in which information is transferred between the first processor on the transmitting side, and a broadcast signal line for broadcast communication is provided on the common bus, and the first processor on the transmitting side said second on the receiving side from
When transmitting data to the second processor, the second processor outputs the ready signal and outputs an active low signal indicating that an event has occurred for access when the broadcast signal line is inactive at the TTL high level. respond with
A common bus system characterized in that the broadcast signal line responds with an active high level indicating that an event has occurred to an access when the broadcast signal line is active at a TTL low level.