JPH04290254A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH04290254A
JPH04290254A JP3053044A JP5304491A JPH04290254A JP H04290254 A JPH04290254 A JP H04290254A JP 3053044 A JP3053044 A JP 3053044A JP 5304491 A JP5304491 A JP 5304491A JP H04290254 A JPH04290254 A JP H04290254A
Authority
JP
Japan
Prior art keywords
semiconductor
lead frame
element mounting
semiconductor device
mounting stand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3053044A
Other languages
Japanese (ja)
Inventor
Sadayuki Moroi
定幸 諸井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3053044A priority Critical patent/JPH04290254A/en
Publication of JPH04290254A publication Critical patent/JPH04290254A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the close contact property of a lead frame with a sealing resin while costs are reduced and to eliminate a need for an etching operation by a method wherein a plurality of holes are made in positions which are faced with inner leads near the edge end part of a semiconductor-element mounting stand part on which a semiconductor element is mounted and sealed with a resin. CONSTITUTION:A semiconductor-element mounting stand part 1 is formed along tips of inner leads 2; a plurality of through holes 3 are made at its end part. At this time, it is desirable that the gap between the semiconductor-element mounting stand part 1 and the tips of the inner leads 2 is narrow as far as possible. When a semiconductor device is assembled by using a lead frame having such a shape, wires which have wire-bonded electrodes on a semiconductor element to the inner leads 2 easily come into contact with the semiconductor- element mounting stand part 1. Therefore, it is desirable to paste an insulating tape 4 on the end part of the semiconductor-element mounting stand part 1.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置に用いるリ
ードフレームに関し、特にその半導体素子搭載台部の形
状に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used in a semiconductor device, and more particularly to the shape of a semiconductor element mounting base thereof.

【0002】0002

【従来の技術】従来、この種の半導体装置に用いるリー
ドフレームは、図3,図4に示すように、半導体素子搭
載台部1の形状が単に長方形であったり、リードフレー
ムと封止樹脂との密着性を高めるために内部リード2や
半導体素子搭載台部1裏面に複数の凹部(ハーフエッチ
)5をエッチング加工によって形成している。この凹部
5の位置は、半導体装置を全体加熱方式によってプリン
ト基板へ実装する際のリードフレームと封止樹脂との熱
膨張差によるボンディングワイヤの破断等の不具合を防
止するためには、内部リードのボンディング点付近にあ
ることが必要であった。
[Prior Art] Conventionally, as shown in FIGS. 3 and 4, lead frames used for this type of semiconductor device have a semiconductor element mounting base 1 that is simply rectangular in shape, or a lead frame and a sealing resin. In order to improve the adhesion, a plurality of recesses (half-etch) 5 are formed on the inner leads 2 and the back surface of the semiconductor element mounting base 1 by etching. The position of this recess 5 is determined by the position of the internal lead in order to prevent problems such as breakage of the bonding wire due to the difference in thermal expansion between the lead frame and the sealing resin when the semiconductor device is mounted on a printed circuit board using the whole heating method. It needed to be near the bonding point.

【0003】0003

【発明が解決しようとする課題】この従来の半導体装置
用リードフレームでは、内部リード2や半導体素子搭載
台部裏面に凹部5を形成するためには、エッチング加工
する必要があり、プレス加工ができず生産数量が多い場
合でもコストを低減することが困難であった。また、内
部リード2に凹部5を形成した場合、内部リードの強度
が低下し、リードフレーム製造工程中及び半導体装置組
立工程中にリードが変形し易いという問題点があった。 さらに、近年半導体装置の多ピン化が進み、内部リード
が細くなると凹部の加工が困難になるという問題点があ
った。
[Problems to be Solved by the Invention] In this conventional lead frame for semiconductor devices, in order to form the recesses 5 on the inner leads 2 and the back surface of the semiconductor element mounting base, etching processing is required, and pressing processing is not possible. However, it has been difficult to reduce costs even when the production volume is large. Further, when the recess 5 is formed in the internal lead 2, the strength of the internal lead is reduced, and there is a problem that the lead is easily deformed during the lead frame manufacturing process and the semiconductor device assembly process. Furthermore, as the number of pins in semiconductor devices has increased in recent years, and the internal leads have become thinner, there has been a problem in that it becomes difficult to process recesses.

【0004】本発明の目的は、これらの問題を解決し、
コスト低減しながらリードフレームと封止樹脂との密着
性を高めると共に、エッチング加工を不要とした半導体
装置用リードフレームを提供することにある。
[0004] The purpose of the present invention is to solve these problems and
It is an object of the present invention to provide a lead frame for a semiconductor device that improves the adhesion between the lead frame and a sealing resin while reducing costs, and eliminates the need for etching.

【0005】[0005]

【課題を解決するための手段】本発明の構成は、半導体
素子を半導体素子搭載台部に載置してこれらを樹脂封止
して組立てる半導体装置用リードフレームにおいて、前
記半導体素子搭載部の縁端部近傍で内部リードと対向す
る箇所に複数の貫通穴を形成したことを特徴とする。
[Means for Solving the Problems] The structure of the present invention provides a lead frame for a semiconductor device in which a semiconductor element is mounted on a semiconductor element mounting base part and then sealed with resin to assemble the semiconductor element, at the edge of the semiconductor element mounting part. A feature is that a plurality of through holes are formed near the end at a location facing the internal lead.

【0006】[0006]

【実施例】図1は本発明の一実施例の半導体装置用リー
ドフレームの部分平面図である。図2は本発明の第2の
実施例の半導体装置用リードフレームの平面図である。 本実施例の半導体素子搭載台部1は、内部リード2の先
端に沿って形成され、かつその端部に貫通穴3を複数個
形成している。その際半導体素子搭載台部1と内部リー
ド2の先端とのすき間はできる限り狭い方が望ましい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a partial plan view of a lead frame for a semiconductor device according to an embodiment of the present invention. FIG. 2 is a plan view of a lead frame for a semiconductor device according to a second embodiment of the present invention. The semiconductor element mounting base 1 of this embodiment is formed along the tip of the internal lead 2, and has a plurality of through holes 3 formed at the end thereof. At this time, it is desirable that the gap between the semiconductor element mounting base 1 and the tip of the internal lead 2 be as narrow as possible.

【0007】このような形状のリードフレームを用いて
半導体装置を組立てた場合、半導体素子上の電極と内部
リード2との間をワイヤボンディングした金線等のワイ
ヤが半導体素子搭載台部1と接触してしまうことが懸念
される。そのため、図2に示す、本発明の第2の実施例
では、半導体素子搭載台部1の端部に電気絶縁性のテー
プ4を貼付するか、同様に絶縁性の液状樹脂等をできる
限り薄く塗布し硬化させている。
When a semiconductor device is assembled using a lead frame having such a shape, a wire such as a gold wire bonded between the electrode on the semiconductor element and the internal lead 2 comes into contact with the semiconductor element mounting base 1. There is a concern that this may happen. Therefore, in the second embodiment of the present invention shown in FIG. 2, an electrically insulating tape 4 is pasted to the end of the semiconductor element mounting base 1, or similarly an insulating liquid resin or the like is applied as thinly as possible. It is applied and cured.

【0008】この第2の実施例によって、もしも半導体
装置組立工程中において、ボンディングワイヤが垂れ半
導体素子搭載第部1と接触するような場合があっても、
電気的には絶縁を保つことができる。
According to the second embodiment, even if the bonding wire sag and comes into contact with the semiconductor element mounting portion 1 during the semiconductor device assembly process,
Electrical insulation can be maintained.

【0009】[0009]

【発明の効果】以上説明したように本発明は、半導体素
子搭載台部の縁端部近傍に複数の貫通穴を備えることに
より、封止樹脂とリードフレームとの密着性を高め、従
来のエッチング加工によって形成した凹部を有するリー
ドフレームと同等の効果がある。また、本発明のリード
フレームは、プレス加工によって製造することが可能で
あり、生産コストを従来の1/5程度まで低減させるこ
とができる。さらに、内部リード上に凹部を形成する必
要がないため、内部リードの強度を低下させることがな
く、リードフレーム製造工程及び半導体装置組立工程中
の歩留を向上させるという効果も有する。
As explained above, the present invention improves the adhesion between the sealing resin and the lead frame by providing a plurality of through holes in the vicinity of the edge of the semiconductor element mounting base. It has the same effect as a lead frame having a recess formed by processing. Further, the lead frame of the present invention can be manufactured by press working, and the production cost can be reduced to about 1/5 of the conventional one. Furthermore, since there is no need to form a recess on the internal lead, the strength of the internal lead is not reduced, and yields are improved during the lead frame manufacturing process and the semiconductor device assembly process.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例の部分平面図。FIG. 1 is a partial plan view of an embodiment of the present invention.

【図2】本発明の第2の実施例の部分平面図。FIG. 2 is a partial plan view of a second embodiment of the invention.

【図3】従来の半導体装置用リードフレームの部分平面
図。
FIG. 3 is a partial plan view of a conventional lead frame for a semiconductor device.

【図4】従来のリードフレームの他の例の部分平面図。FIG. 4 is a partial plan view of another example of a conventional lead frame.

【符号の説明】[Explanation of symbols]

1    半導体素子搭載台部 2    内部リード 3    貫通穴 4    電気絶縁性テープ 5    凹部(ハーフエッチ) 1 Semiconductor element mounting base 2 Internal lead 3 Through hole 4 Electrical insulation tape 5 Recess (half-etch)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体素子を半導体素子搭載台部に載
置してこれらを樹脂封止して組立てる半導体装置用リー
ドフレームにおいて、前記半導体素子搭載部の縁端部近
傍で内部リードと対向する箇所に複数の貫通穴を形成し
たことを特徴とする半導体装置用リードフレーム。
1. In a lead frame for a semiconductor device, which is assembled by placing a semiconductor element on a semiconductor element mounting base and sealing them with resin, a portion facing an internal lead near an edge of the semiconductor element mounting part; A lead frame for a semiconductor device, characterized in that a plurality of through holes are formed in the lead frame.
JP3053044A 1991-03-19 1991-03-19 Lead frame for semiconductor device Pending JPH04290254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3053044A JPH04290254A (en) 1991-03-19 1991-03-19 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3053044A JPH04290254A (en) 1991-03-19 1991-03-19 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH04290254A true JPH04290254A (en) 1992-10-14

Family

ID=12931885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3053044A Pending JPH04290254A (en) 1991-03-19 1991-03-19 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH04290254A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844306A (en) * 1995-09-28 1998-12-01 Mitsubishi Denki Kabushiki Kaisha Die pad structure for solder bonding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5844306A (en) * 1995-09-28 1998-12-01 Mitsubishi Denki Kabushiki Kaisha Die pad structure for solder bonding

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Effective date: 19990119