JPH04291655A - Inter-memory data transfer control system - Google Patents

Abstract

PURPOSE:To transfer data between plural memories for the same transfer time without operating external data in respect to a control system for controlling the data storing positions of a transfer destination and a transfer origin in the case of transferring the data between the memories. CONSTITUTION:An additional memory 2 consisting of an area having the same constitution as a memory 1 connected to a CPU 5 is constituted so as to be duplexed to the memory 1, an address conversion part 3 for adding '1' to the address of the memory 2 and an output selection part 4 for selecting a write output to the memory based on a transfer pattern instruction outputted from the CPU 5 are also included in the control system and constituted so that the memory 1 stores data based on address setting from the CPU 5, the conversion part 3 converts an address outputted from the CPU 5 and adds '1' to the converted value, the memory 2 stores a value obtained by shifting the same data as the data of the memory 1 only by an area and the output selection part 4 writes the reading data of the area of the memory 1 in another area of the memory 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling data storage locations of a transfer source and a transfer destination when data is transferred between memories. When writing and reading data from a subscriber circuit to a memory in an exchange, normally a transfer source and a transfer destination area are provided in the memory area via a CPU, and data is sent and received from each other.

FIG. 5 shows an example of a connection configuration of a data transfer method between memories. In the figure, 21 is a subscriber circuit, 22 is an I
/O interface, 23 is a CPU, and 24 is a memory. Data transmitted and received from the subscriber circuit 21 via the I/O interface 22 is processed by the CPU 23, read out from the memory 24, and written into the memory 24. This read or write data bus is composed of 16 bits, and data is handled in units of 8 bits (1 byte).

The memory 24 consists of a transfer source area for reading and a transfer destination area for writing, and the data storage order of each area is determined by odd-numbered addresses and even-numbered addresses. Therefore, the data area read at the even numbered address of the transfer source

[0] data is C
Data area of even numbered address of transfer destination processed by PU23

Written to [0]. Similarly, the data in data area [1] read at the odd-numbered address of the transfer source is
It is processed by the CPU 23 and written to the data area [1] of the odd numbered address of the transfer destination. i.e. data area

[0]
The 1-byte data of and [1] are read from the same area and written to the same area as 1 word of 16-bit data. However, the data area read at the even numbered address of the transfer source

When data [0] is written to the data area [1] at the odd numbered address of the transfer destination, or when the data area [1] is read at the odd numbered address of the transfer source.
Transfer data to the data area of the even-numbered address [
2], it is necessary to convert the transfer area within the CPU 23.

0004

2. Description of the Related Art A functional block connection diagram of a conventional transfer system is shown in FIG. In the figure, the area surrounded by dotted lines indicates the memory area, which is composed of the upper and lower (8 bits x m) memory areas of MEM-U1 and MEM-L1, and performs normal memory access. The MEM-L1 side stores D00 to D07 on the data bus, and the MEM-U1 side stores D08 to D15 on the data bus. Data on the data bus is stored in each area according to the address from the address bus.

[0005] When data is transferred between memories in a device where the data bus is composed of 16 bits and data is handled in units of 8 bits (1 byte), there are four types of combinations of transfer patterns depending on the combination of transfer start addresses. be. FIG. 7 shows a conventional transfer pattern switching method. In the figure, (1)' means even address → even address, (
2)' shows the case of odd number address → odd number address, (3)' shows the case of even number address → odd number address, and (4)' shows the case of odd number address → even number address. Note that A, B, C, D, E, F
indicates a 1-byte data area. (1) In the case of even address → even address, if the first address on the read side of the transfer source of A is an even number and the first address on the write side of the transfer destination is an even number, 1 word of data AB will be transferred as is. be done. Next 1 word data C
Both D and EF are transferred as is. (2) In the case of 'odd address → odd number address, if the first address on the read side of the transfer source of A is an odd number and the first address on the write side of the transfer destination is an odd number, 1 byte of data A is 1 byte. The next 1 word of data BC and data ED are transferred as they are, and the next 1 byte of data F is transferred as 1 byte of data F. (3) In the case of even number address → odd number address, if the first address on the read side of the transfer source of A is an even number and the first address on the write side of the transfer destination is an odd number, 1 byte of data A is first It is transferred as a byte of data A, and the next data B and data C are taken out and 1 word of data BC is created.
Transfer as . Similarly, data D and E are extracted and transferred as one word of data DE. The next 1 byte of data F is transferred as 1 byte of data F. (4) In the case of 'odd address → even address, if the first address on the read side of the transfer source of A is an odd number and the first address on the write side of the transfer destination is an even number, 1 byte of data A and data B is extracted and transferred as data AB, and the next data C and data D are extracted and transferred as one word of data CD. Similarly, data E and F are extracted and transferred as one word of data EF.

[0006]

[Problem to be Solved by the Invention] Regarding (1)' above, if you read 16 bits (1 word) of data from the memory onto the data bus using normal means and write that data as is to the destination memory. Similarly for (2)', if you first transfer 8 bits (1 byte), then (1
)' pattern. However, (3)' and (4
)', it is necessary to read one byte at a time from the memory, swap the upper and lower parts on the data bus, and then write it to the memory, which requires extra data transfer compared to (1)' and (2)'. In addition, the data transfer time will be more than twice as long.

[0007] In any of the above cases (1)' to (4)', the present invention aims to transfer data between memories in the same transfer time and without external data manipulation. purpose.

[0008]

[Means for Solving the Problems] A diagram of the principle configuration of the present invention is shown in FIG. In the figure, 1 is a memory consisting of an upper data area and a lower data area, 2 is an additional memory consisting of an area with the same configuration as memory 1, 3 is an address conversion unit that adds +1 to an address, and 4 is a transfer pattern instruction from the CPU. 5 is an output selector that selects the write output to the memory. 5 sends an address to the memory via the address bus, upper and lower data via the data bus, and read/write control signals via the control bus, which are transferred to the output selector. Indicates the CPU that sends the pattern instruction.

The memory 1 stores data in the upper data area and the lower data area according to the address setting from the CPU 5, and the memory 2 converts the address from the CPU 5 using the address converter 3 and sets it by +1, and stores the data in the memory 1. The same data is stored in the lower data area and the upper data area with one area shifted. The output selection unit 4 always performs reading and writing from the memory 1 in the memory 1 area, and always performs reading and writing from the memory 2 in the memory 2 area. In response to a transfer pattern instruction from the CPU 5, the output selection unit 4 writes the read data in an area of the memory 1 to another area of the memory 2. The output selection unit 4 determines which one to output onto the data bus based on the transfer pattern, and is configured so that data at a specific address can be output to either the upper or lower part of the bus.

0010

[Operation] A conceptual diagram of the memory structure of the present invention is shown in FIG. Figure (a) shows the state when area conversion is not performed, and Figure (b) shows the situation when area conversion is performed. In the figure, A, B, C, D, E
, F each represent one byte of data, which is stored in the upper or lower area of the memory, and the upper data and lower data of the data bus are selected under write/read control from the CPU.

When the area shown in FIG. 1 (a) is not converted, the lower data A, C, E and upper data B, D, F of the data bus written in the lower area and upper area of memory 1 are Lower data A, C, E and upper data B of the data bus
, D, F from the lower and upper regions of the memory 1.

When performing the area conversion as shown in FIG.
, C, and E, and lower-order data B, D, and F of the data bus are written in the lower area of the memory 2. Memory 2 when reading
The upper data bus A, C, and E are read from the lower area of the memory 2, and the lower data B, D, and F of the data bus are read from the upper area of the memory 2.

[0013]

Embodiment FIG. 3 shows an embodiment of a functional block diagram of the transfer method of the present invention. In the figure, 11 is a memory, 12 is an additional memory, 13 is an address conversion section, and 14 is an output selection section. The first memory 11 includes an upper area MEM-U1 and a lower area MEM-L1, the second memory 12 includes an upper area MEM-U2 and a lower area MEM-L2, and an address conversion unit 13. consists of a +1 adder, and the output conversion section 14 consists of a selector S1 and a selector S2. The ▽ mark on the data bus in the output converter 14 indicates the data read direction and data write direction. Buses from the CPU are address bus AXX-00, data bus D15-08, D07-0.
0, a control line R/W, and a transfer pattern instruction line PT. Address buses and data buses are shown with thick lines, and control lines are shown with thin lines.

In the figure, the memory 11 is a conventional memory, and the memory area MEM-U1/L1 has an 8-bit×m configuration and performs normal memory access. The MEM-L1 side transfers D00 to D07 on the data bus to the MEM-U1
side stores D08 to D15 on the data bus. At the same time, an address incremented by +1 is specified by the conversion circuit of the address conversion unit 13 to the memory area MEM-U2/L2 of the memory 12 added in the present invention, and according to the address, D08 to D15 on the data bus are sent to the MEM-L2 side.
, D00 to D0 on the data bus on the MEM-U2 side.
Remember 7. As a result, the data will be written to each memory simultaneously. At the time of reading, the MEM-L1 side outputs to D00 to D07 on the data bus, and the MEM-U1 outputs to D08 to D15 on the data bus. At the same time, the area MEM of the memory 12 added in the present invention
-U2/L2 is given an address incremented by 1 by the address converter 13, and according to that address, MEM-L
The 2nd side connects MEM- to D00 to D07 on the data bus.
The U2 side is connected to the ■ side of the selectors S1 and S2 of the output selection section 14 in order to output to D08 to D15 on the data bus.

Selectors S1 and S2 of the output selection section 14 are as follows:
Depending on the transfer instruction pattern from the CPU, either the ■ or ■ route is selected, and which route is to be output onto the data bus is determined. As a result, it is possible to output data at a specific address to either the upper or lower end on the bus. That is, if the ■ side of the selectors S1 and S2 of the output selection section 14 is selected, reading and writing are performed by the memory 11, and when the ■ side of the selectors S1 and S2 is selected, the reading is performed by the memory 12, and the memory 11 Writing is performed by.

FIG. 4 shows an example of switching between each transfer pattern. (1) is even number address → even number address, (2) is odd number address → odd number address, (3) is even number address →
Odd address (4) indicates a transfer pattern from odd address to even address. In the figure, read at the transfer source,
The data to be written to the transfer destination is indicated by A, B, C, D, E, and F. MEM-U1/L1 is the memory area of the memory 11, ME
M-U2/L2 indicates the memory area of the memory 12, and D
07-D00, D08-D15 indicate data on the data bus. (1) In the case of even address → even address, the transfer source data is read from the even address by MEM-U1/L1 and the odd address by MEM-U2/L2, and the transfer destination data is read from the even address by MEM-U1/L1. write to,
At the same time, write the odd address to MEM-U2/L2. Therefore, the transfer source MEM-U2/L2 is not used, but the transfer source MEM-U1/L1 is read and the transfer destination MEM-U2/L2 is not used.
-Write an even address to U1/L1 and write MEM at the same time.
-Write an odd address to U2/L2, but AB, CD
, EF are transferred between the memories 11. (2) In the case of odd address→odd address, the transfer source data is read from the odd address using MEM-U1/L1 and the even address from MEM-U2/L2, and the transfer destination data is read from the odd address using MEM-U1/L1. write to,
At the same time, write an even address to MEM-U2/L2. Therefore, the transfer source MEM-U2/L2 is not used, but the transfer source MEM-U1/L1 is read and the transfer destination MEM-U2/L2 is not used.
-Write an odd address to U1/L1 and write MEM at the same time.
-Write an even address to U2/L2, but write 1 byte of A, each word of BC, DE, and 1 byte of F to memory 11.
Transfer between. (3) In the case of an even number address → an odd number address, the transfer source data is read from the even address by MEM-U1/L1 and the odd number address by MEM-U2/L2, and the transfer destination data is read from the odd address by MEM-U1/L1. write to,
At the same time, write an even address to MEM-U2/L2. Therefore, the transfer source MEM-U1/L1 is not used, but the transfer source MEM-U2/L2 is read and the transfer destination MEM
-Write an odd address to U1/L1 and write MEM at the same time.
-Write an even address to U2/L2, but write 1 byte of A, each word of BC, DE, and 1 byte of F to memory 12.
Transfer from (4) In the case of odd address → even address, the transfer source data is read from the odd address using MEM-U1/L1 and the even address using MEM-U2/L2, and the transfer destination data is read from the even address using MEM-U1/L1. write to,
At the same time, write the odd address to MEM-U2/L2. Therefore, the transfer source MEM-U1/L1 is not used, but the transfer source MEM-U2/L2 is read and the transfer destination MEM
-Write an odd address to U1/L1 and write MEM at the same time.
-Write an even address to U2/L2, but AB, CD
, EF are transferred from memory 12.

In the above example, in the case of (1) and (2), the selectors S1 and S2 of the output selection unit 14 are selected on the ■ side, and the data is transferred between the memories 11 to perform the writing process, and (
3) and (4), the selector S of the output selection section 14
1 and the ■ side of S2 are selected and data is transferred between the memories 12 to perform a write process.

[0018]

[Effects of the Invention] The present invention eliminates the problem of the prior art from doubling the transfer time due to the data transfer pattern, and also eliminates the need for external data manipulation, so the data transfer pattern is taken into account. This enables high-speed data transfer between memories. Therefore, the processing capacity of the entire system is improved.

[Brief explanation of the drawing]

[Figure 1] Principle configuration diagram of the present invention

[Figure 2] Conceptual diagram of the memory configuration of the present invention

[Figure 3]
Functional block configuration diagram of the embodiment

[Figure 4] Example of switching transfer pattern

[Figure 5] Connection configuration example of data transfer method

[Figure 6] Functional block configuration diagram of conventional example

[Figure 7]
Conventional example of transfer pattern switching

[Explanation of symbols]

1, 11, 24 Memory 2,12 Additional memory 3,13 Address conversion section 4, 14 Output selection section 5,23 CPU 21 Subscriber circuit 22 I/O interface

Claims (2)

[Claims] Claim 1: The data bus is composed of 16 bits,
In a device in which data is handled in units of 8 bits, an additional memory consisting of an area having the same configuration as the memory (1) is added to the memory (1) consisting of an upper data area and a lower data area connected to the CPU (5). (2) is provided to create a duplex configuration, and an address converter (3) that adds +1 to the address to the additional memory (2) and selects the write output to the memory (1) based on a transfer pattern instruction from the CPU (5). The memory (1) is provided with an output selection section (4) to
), data is stored in the upper data area and lower data area according to the address settings from the memory (2) and the CPU (5).
The address from is converted by the address converter (3) and +1
The output selection unit (4) always reads and writes data to the memory (1), and stores the same data as the data to the memory (1) in the lower data area and the upper data area by shifting one area. is performed in the memory (1) area,
Reading and writing to and from the memory (2) are performed in the area of the memory (2), and according to a transfer pattern instruction from the CPU (5), the output selection unit (4) transfers read data from the area of the memory (1) to the memory (2). ), data at a specific address can be output to either the upper or lower end of the bus. 2. A system in which the data bus is expanded to 8×n bits, wherein the memories are configured in n-layers, and when data is written, the address is shifted by one address to each memory and written. The inter-memory data transfer control method according to item 1.