JPH04297060A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To vary a resistance of a resistor by merely altering a voltage to be applied to a control terminal of a p-type impurity diffused layer by providing a low potential side resistance terminal at one end of an n-type impurity diffused layer in the p-type impurity diffused layer and providing a high potential side resistance terminal to be applied at the other terminal by the same potential as that of a buried layer. CONSTITUTION:An n-type impurity diffused layer 15 is provided in a p-type impurity diffused layer 16 provided in an epitaxial layer 23 on a buried layer 19. A silicon oxide film 18 is provided on a surface including the layer 15, and a low potential side resistance terminal 13 and a high potential side resistance terminal 14a connected to the layer 15 are provided on the film 18 through contact holes. Further, a control terminal 12 connected to the layer 16 and a high potential side resistance terminal 14b connected to an n-type impurity lead layer 24 are provided. The layer 24 is connected to the n-type low concentration impurity epitaxial layer 23 and the layer 19 provided on the surface including the layer 19.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, the present invention relates to a semiconductor integrated circuit having a diffused resistance element.

0002

2. Description of the Related Art In a conventional semiconductor integrated circuit, as shown in FIG. 3, a p-type impurity diffusion layer 16 is formed in the same manner as the base region of an npn bipolar transistor, and resistor terminals are formed at both ends of the p-type impurity diffusion layer 16. 25a, 25b, and
An n-type impurity diffusion layer 15 is provided around the p-type impurity diffusion layer 16 to prevent current from leaking from the p-type impurity diffusion layer 16.
A high potential is applied to the terminal 26 through the terminal 26.

0003

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit, when it is desired to change the resistance value depending on circuit characteristics (for example, load capacitance, etc.), a plurality of resistance elements are prepared, and the resistance is changed by a combination of these resistance elements. Since the value has to be changed, there is a problem that the area becomes large.

0004

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes a highly concentrated impurity buried layer of opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a low concentration impurity layer of opposite conductivity type provided on a surface including the buried layer. a concentration impurity layer, a one conductivity type diffusion layer provided in the opposite conductivity type low concentration impurity layer on the buried layer, and a reverse conductivity type diffusion layer having an impurity concentration lower than that of the buried layer provided in the one conductivity type diffusion layer. a conductivity type diffusion layer, and a first conductivity type diffusion layer connected to one end of the opposite conductivity type diffusion layer.
a second resistance terminal connected to the other end of the opposite conductivity type diffusion layer and applying the same potential as the buried layer; and a second resistance terminal connected to the one conductivity type diffusion layer to determine the resistance value. and a control terminal for applying a variable potential.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention.

As shown in FIG. 1, a p-type silicon substrate 17
An n-type high concentration impurity buried layer 19 provided on one main surface, an n-type low concentration impurity epitaxial layer 23 provided on the surface including the buried layer 19, and a buried layer 1 provided on the epitaxial layer 23.
9 and the p-type impurity diffusion layer 16 provided in the epitaxial layer 23 above the buried layer 19.
through the n-type impurity diffusion layer 15 provided in the p-type impurity diffusion layer 16, the silicon oxide film 18 provided on the surface including the n-type impurity diffusion layer 15, and the contact hole provided in the silicon oxide film 18. A low potential side resistance terminal 13 and a high potential side resistance terminal 14a connected to the n-type impurity diffusion layer 15, a control terminal 12 connected to the p-type impurity layer 16, and a high potential side resistance connected to the n-type impurity extraction layer 24. The terminal 14b is configured to include the terminal 14b.

Here, the emitter voltage V is applied to the control terminal 12.
When a voltage of EE is applied, all of the current flowing through this resistor flows through the n-type impurity diffusion layer 15, resulting in a relatively large resistance value. Further, since the potential of the p-type impurity diffusion layer 16 surrounding the n-type impurity diffusion layer 15 is VEE, the above-mentioned current does not flow outside. On the other hand, V is applied to the control terminal 12.
When a voltage 1V higher than EE is applied, the current flowing through this resistor flows through the buried layer 19, resulting in a relatively small resistance value.

FIG. 2 is a circuit diagram showing an example of application of the present invention.

As shown in FIG. 2, 1a, 1b, 1c are E
Transistors forming the CL circuit, 20 is the switch current generation voltage VCSI, 21 is the switch current generation transistor, 2 is the emitter resistance of the transistor 21, 3 is the common resistance of the transistors 1a and 1b, 4 is the collector resistance of the transistor 1c, 5 is an emitter follower transistor; 7a and 7b are logic input terminals connected to the bases of transistors 1a and 1b, respectively; 8 is a reference voltage input terminal connected to the base of transistor 1c;
9 is a collector voltage VCC supply terminal, 10 is an emitter voltage VEE supply terminal, 11 is an emitter follower output terminal, 6
is a variable resistor using the present invention, and 12 is a control terminal of the resistor. Here, the resistance value of the variable resistor 6, which is the emitter resistance, can be changed simply by changing the potential of the control terminal 12 of the variable resistor 6.The emitter resistance depends on whether the capacitance value of the load circuit connected to the output terminal 11 is large or small. Since the variable resistor 6 can be set according to the capacitance value of the load circuit, it is possible to reduce variations in the operation delay time of the circuit.

[0011]

As described above, the present invention has the advantage that the resistance value can be easily changed by changing the voltage applied to the control terminal, and circuit design can be facilitated.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an application example of the present invention.

FIG. 3 is a cross-sectional view showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1a, 1b, 1c Transistor 2 Emitter resistor 3 Resistor 4 Collector resistor 5 Emitter follower transistor 6
Variable resistors 7a, 7b Logic input terminal 8 Reference voltage input terminal 9 Collector voltage VCC supply terminal 10 Emitter voltage VEE supply terminal 11 Emitter follower output terminal 12 Control terminal 13 Low potential side resistance terminals 14a, 14b High potential side resistance terminal 15
N-type impurity diffusion layer 16 P-type impurity diffusion layer 17 P-type silicon substrate 18 Silicon oxide film 19 Buried layer 20 Switch current generation voltage VCSI 21
Switch current generation transistor 23 Epitaxial layer 24 Leading layers 25a, 25b Resistance terminal 26 Terminal

Claims (1)

[Claims] 1. An opposite conductivity type high concentration impurity buried layer provided on a semiconductor substrate of one conductivity type, an opposite conductivity type low concentration impurity layer provided on the surface including the buried layer, and an opposite conductivity type low concentration impurity layer provided on the surface including the buried layer; one conductivity type diffusion layer provided within the conductivity type low concentration impurity layer; an opposite conductivity type diffusion layer provided within the one conductivity type diffusion layer and having an impurity concentration lower than the buried layer; and the opposite conductivity type diffusion layer. a first resistance terminal connected to one end of the resistor terminal; and a second resistance terminal connected to the other end of the reverse conductivity type diffusion layer and applied with the same potential as the buried layer.
A semiconductor integrated circuit comprising: a resistance terminal; and a control terminal connected to the one conductivity type diffusion layer to apply a potential to vary the resistance value.