JPH0437519B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a decoder circuit, and particularly to a decoder circuit for a semiconductor MOS memory.

<Prior art> Figure 3 shows a conventionally used semiconductor MOS
This is a diagram showing an overview of the arrangement of memories. Regions 11 and 12 extending to the left and right are memory cell array sections, and a central region 13 sandwiched between the memory cell array sections 11 and 12 is provided as a row decoder section. It is being Regions 14 and 15 disposed below the memory cell array sections 11 and 12 are column decoder sections, and sense amplifier sections 16 and 17 are disposed following the column decoder sections 14 and 15.

The row decoder section 13 is composed of a plurality of row decoder circuits, and one of the row decoder circuits is activated by an address signal. The output of the row decoder circuit is commonly called a word line, and the output of the activated row decoder circuit is 1.
Only the word line of the book is activated and becomes a high potential.
Then, only the memory cells connected to this word line are selected, and data exchange between the memory cells and the data line is executed.

FIG. 4 shows the row decoder circuit 23, word line 21,
Memory cells 20 ₁ to 20 _o and data line 22 ₁
It is a schematic diagram for explaining the relationship between ~22 _o .
The row decoder circuit 23 shown in the figure is just one example.
An example of a DMOS configuration is shown. In the following description, any row decoder circuit may be used since it is not directly related to the detailed circuit configuration of the row decoder section.

Moreover, the data lines 22 ₁ to 22 _o of each memory cell are 1
Although only a book is shown, it is not limited to one book, and there is no problem even if there are two books.

As mentioned above, only one word line is selected at a certain point in time, and this selected word line will be referred to as word line W _i from now on. Next, considering the case where another word line W _j is selected, the high potential of the previously selected word line W _i shifts to a low potential, and the potential of the word line W _j changes from a low potential to a high potential instead. Displaced to. FIG. 5 illustrates the temporal changes during this period. At time t ₀ , the address switches and the selected word line becomes
Changes from W _i to W _j . Accordingly, the word line W _i
The word line potentials V _wi and V _wj of and W _j change like the curves shown in the figure. In order to charge and discharge the word line capacitance, the word line potential V _wi shifts from a high potential to a low potential a little later than the address switching time t ₀ , and the word line potential V _wj shifts from a low potential to a high potential. .
Generally, word lines can be discharged faster than they can be charged, so the relationship between each potential V _wi and V _wj is as shown in the figure. In other words, it discharges from a high potential to a low potential.
The change in V _wi is faster than the change in V _wj when charging from a low potential to a high potential. Further, this relationship is also desirable because the word line W _i and the word line W _j are not selected at the same time.

However, in order for the semiconductor MOS memory to operate at high speed, it is desirable that the potential V _wj becomes a high potential as soon as the potential V _wi falls below a certain activation reference level. In FIG. 5, this activation reference level is shown as _VTH . This activation reference level V _TH is MOS
This is the threshold voltage of the transistor. In order to speed up memory operation, in the example showing potential changes as shown in FIG _.
The shorter the time interval between _{t 1} and t ₂ , the better, but in the conventional decoder circuit described above,
It was difficult to shorten the time interval, and there was a limit to how fast memory could be made.

<Object of the Invention> The present invention is a decoder circuit that eliminates the drawbacks of the decoder circuit that forms the word line signal for selecting the conventional semiconductor MOS memory and can increase the speed. When a word line becomes unselected and changes from a high potential to a low potential, if the potential falls below the activation reference level, the potential of the word line to be selected next is quickly changed from a low potential to a high potential.

<Embodiment> FIG. 1 is a circuit diagram of a main part showing an embodiment according to the present invention. This circuit is a circuit provided in addition to the decoder circuit 23 that supplies signals to the word line shown in FIG. 4, but as will be described later, the word line in FIG. 1 is connected to the word line in the conventional decoder circuit. The circuit configuration of the decoder circuit 23 itself is not limited to the circuit shown in FIG. 4.

Furthermore, the additional circuit shown in FIG. 1 can be added to the word line shown in FIG. Good too.

In FIG. 1, since circuits having the same configuration are connected to each of the word lines W ₀ to W _k , the word line W _i will be cited and explained. That is, a first enhancement type MOS transistor T _E1i whose gate input is the word line W _i is provided, and the MOS transistor T _E1i
The source of is grounded, and the drain is commonly connected to the drain of the first enhancement type MOS transistor in the other word line to provide an OR output,
A load element T _L made of, for example, a depletion type MOS transistor is connected between the OR output point A and the power supply _Vcc . Further, a second enhancement type MOS transistor T _E2i whose gate input is the above-mentioned OR output is provided, and the MOS transistor T _E2i
A circuit to be added to the decoder circuit 23 is constructed by connecting the drain and source to the power supply V _cc and the word line _Wi, respectively.

In the circuit with the above configuration, the current word line
Assume that W _i is selected and all other word lines are unselected. At this time, the first enhancement type MOS transistor T _E1p of each word line ~
The logical sum output point A with parallel tangents to the drain of T _E1k is
It has a low potential close to OV. As a result, the second enhancement type MOS transistors T _E2p to _{T E2k connected} between each word line and the power supply Vcc
is in the off state.

Next, when word line W _i goes from selected to unselected,
The potential V _i of W _i changes from a high potential to a low potential. When the potential of the word line W _i becomes equal to or lower than the threshold voltage V _TH of the MOS transistor, the MOS transistor T _E1i , which has been in the on state, turns off. As a result, the potential at point A transitions from a low potential to a high potential,
Second enhancement type MOS transistor T _E2p
~T Turn on _E2k and try to charge all word lines. However, when the word line potential reaches the potential that turns on the first enhancement type MOS transistors T _E1p to T _E1k , the potential at point A decreases, so each word line is balanced at a potential slightly higher than the threshold potential V _TH . state. After this, the potential of the word line W _j selected from the unselected one becomes a high potential, and as a result, the first enhancement type MOS transistor T _E1j connected to the word line W _j turns on.
The potential at point A becomes a low potential of approximately OV, and the second enhancement type MOS transistors T _E2p to T _E2k are all turned off.

When the potential of the word line that has gone from being selected to being unselected as described above becomes below the threshold potential, the circuit shown in Figure 1 is activated and rapidly charges all word lines to about the threshold potential. This helps the potential of the word line that has changed from unselected to selected to quickly rise to a high potential.

Figure 2 shows changes in the potential V _wi of the word line that went from selected to unselected, and the potential V _wj of the word line that went from unselected to selected, and shows the shortening of the time interval between times t ₁ and t ₂ '. is planned. Note that for word lines that continue to be non-selected, the word lines in the decoder circuit are in a non-selected state and are charged from OV at time _t1 .

<Effects> According to the present invention, by adding a simple circuit to configure a decoder circuit, a semiconductor MOS
Memory selection operations can be sped up.

[Brief explanation of drawings]

FIG. 1 is a main circuit diagram showing an embodiment of the present invention, FIG. 2 is a potential change diagram for explaining the operation of the circuit, FIG. 3 is a conceptual diagram showing a general memory configuration, and FIG. The figure is a conventional decoder circuit diagram, and FIG. 5 is a potential change diagram for explaining the operation of the conventional circuit. W ₁ ~ _{W k} ...Word line, T _E1p ~ T _E1k ... First enhancement type MOS transistor, T _E2p ~
T _E2k ... second enhancement type MOS transistor, T _L ... load element, 23 ... decoder circuit,
20 ₁ to 20 _o ...memory cells.

Claims (1)

[Claims] 1. In a decoder circuit that forms a word line signal for selecting a memory cell based on an input address signal, a gate connected to the word line,
and the first enhancement type whose source is grounded.
The potential at the common connection point of the drains and a load element inserted between the MOS transistor and the power source and the point where the drains of the first enhancement type MOS transistor are commonly connected to each other is input to the gate, and the power source is connected to the power source. and a second enhancement type MOS transistor connected between the word lines.