JPH0443271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of controlling a raster scan type graphic display.

Conventional structure and its problems Raster scan type CRT displays draw figures and characters using dot rows (pixel rows).
As shown in Figure a, jaggedness (jagging) occurs, and straight lines and curves cannot be displayed smoothly, giving a sense of discomfort. P1 in FIG. 1a indicates one pixel.

Figure 1b shows a conventional example of jagging correction that prevents this jaggedness from perceiving the human eye.Pixels P2 with different brightness are added where the pixel row changes, making use of a visual illusion. The jagged edges are removed.

However, in the conventional example described above, since the brightness of pixels is changed, lines displayed on a CRT display may appear thick or thin, and the line thicknesses do not appear uniform.

Purpose of the Invention The present invention eliminates the drawbacks of the above-mentioned conventional example, and only slightly increases the frame memory capacity.
The purpose is to substantially double the resolution and correct jagging.

Composition of the Invention In order to achieve the above object, the present invention reduces the frame capacity when converting a figure into a pixel string by converting it in two pixel pairs and doubling the vertical (m) x horizontal (n) resolution. m×n×d to 2m×
By simply increasing it to m×n×(d+2) instead of increasing to 2n×d, the actual resolution is doubled and the jagging is reduced.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the configuration of an embodiment of the present invention. In FIG. 2, reference numeral 1 denotes a frame memory, and this frame memory 1 stores figures as a set of pixel (dot) sequences.

FIG. 3 shows details of the frame memory 1, which is constructed by stacking a plurality of m×n bit planes. The plurality of planes includes a plane 1A representing color and a plane 1B for jag correction. Plane 1A representing color is
Prepare the required number of sheets depending on the number of color types. Black and white is 1
One piece is enough. The plane 1B for jag correction is composed of two planes. Using the memory in row i, column j and row i (j-1) of frame memory 1, as described later,
2i row 2j column on the screen of CRT display 7, (2i +
1) Row 2j column, 2i row (2j+1) column, (2i+1) row (2j
+1) The four light emitting positions of the column are memorized.

In FIG. 2, 2 is a buffer, and this buffer 2 temporarily stores information read from the frame memory 1. The buffer 2 also stores information representing colors and jag correction information for a plurality of pixels, and sequentially sends out information in accordance with the display on the CRT display 7. 3 is an auxiliary buffer, and this auxiliary buffer 3 holds jag correction information among the information of the buffer 2 sent out last time.
That is, when the data of the i-th row (j-1) column was sent out last time, the jag correction information of the i-th row (j-1) column is held. In this way, the buffer 2 and the auxiliary buffer 3 allow the color information of the i-th row and the j-th column and the jag correction data of the i-th row (j-1) and the i-th row and the j-th column to be used simultaneously. Reference numeral 4 denotes a color map, and if the information representing the color output from the buffer 2 represents a color code, this color map 4 converts it into an RGB (red, green, blue) color signal. If the frame memory 1 stores color signals, the color map 4 is not necessary. 5 is a delay circuit, and this delay circuit 5 either sends out the output of the color map 4 as it is, or
(2n) Delay or control sending. (H is horizontal sweep time) 6 is a digital-to-analog (DA) converter, and this DA converter 6 converts a digital color signal into an analog voltage or current. Reference numeral 7 denotes a cathode ray tube (CRT) display, and this CRT display 7 is a so-called raster scan type CRT display that displays images in response to horizontal and vertical synchronization signals and color signals (video signals). The CRT display 7 uses a vertical synchronization signal to display 1/2 interlace scan, normally 1/2 non-interlace scan.
If it is an interlace scan, use it as a 1/4 interlace scan. This results in
The number of vertical scans is 2m, doubling the resolution. 8 is a timing generation section, and this timing generation section 8 stores XY in the frame memory 1.
Address and read timing, horizontal and vertical synchronization signals are sent to the CRT display 7, and even and odd sweep classification and delay timing are sent to the delay circuit 5.

From buffer 2 to color map 4, H/n
Send information every time. The delay circuit 5 either sends out the information from the color map 4 as is or sends it out as is, depending on the jag correction information from the buffer 2 or the auxiliary buffer 3.
Controls whether to send with a delay of H/(2n). For even number sweeps (sweeps that can be expressed as 2i), the jag correction information of buffer 2 is used, and for odd number sweeps (sweeps that can be expressed as 2i + 1), the jag correction information is used for auxiliary buffer 3.
The jag correction information is used to determine whether or not there is a delay.

This doubles the horizontal resolution. Reference numeral 9 denotes a processing section, and this processing section 9 converts information expressed by a mathematical formula into a pixel string and stores it in the frame memory 1.

The processing unit 9 assumes that the CRT display 7 has a resolution of 2m×2n and converts it into a pixel array. Furthermore, when converting, two pixels (on a CRT display) are converted as a pair. 2
Pixel pairs are shown in FIG. 4.
Only the pair shown in c is used, and the pair shown in figure 4 d is not used.
(Figure 4 shows how to position paired pixels on a 2m x 2n CRT display.) Figure 4D is not used because buffer 2 is H/
This is because it is sent out every n, but not every H/(2n). When a figure is converted into an image using the pixel pairs A, A, and C in Figure 4, the following images appear on the CRT display 7: 2i row, 2j column, (2i + 1) row, i column, 2i row, (2j + 1) column, (2i + 1) row, (2j + 1) ) There are eight types of pixel patterns that can appear at the four points in the column as shown in FIG. This excludes the pattern where two pixels are lined up in the horizontal direction.

This pattern is written near the i row and j column of the frame memory 1. Since there are 8 types of patterns, normally a 3-bit memory is required, but in the present invention, since there are two jag correction memory planes, Memorize using two locations in the column. As an example,
The pattern of 2i rows on the CRT display is stored in the i row, j column of the frame memory 1, and the pattern of (2i+1) rows is stored in the i row, column (j-1) of the frame memory 1. Figure 6 shows this pattern, and is an example of the layout of the display pattern on the CRT for the values "0", "1", and "2" of the jag correction information in the i row and j column of frame memory 1. be. Since the value "3" of the jag correction information in the frame memory is not used, it is convenient to use it for another purpose, such as filling in figures.

Next, the operation of the above embodiment will be explained.

The information read from the frame memory 1 is temporarily stored in the buffer 2 and then sent out every (H/n) time. When this information is zero, a background color (generally black) is sent to the CRT display 7. When the information regarding the color sent from buffer 2 is other than zero, check the jag correction section of buffer 2 for an even number sweep, check the auxiliary buffer 3 for an odd number sweep, and if it is "0", change the background color to "1". ”, the color signal is not delayed, and “2”, the color signal is delayed by H/(2n),
Color map 4, delay circuit 5, DA converter 6
The data is sent to the CRT display 7 via . Specifically, the background color is always output, and only when there is a color signal, the background color and color signal are exchanged and sent out at the same time.

In this embodiment, two locations, i row, j column, and i row, column (j-1), of the frame memory 1 are used for storage, but two locations, i row, j column, and i row, column (j+1), are used for storage. can also be configured. In this case, it is sufficient to input information for two locations into the buffer 2 and send out information for the two locations at the same time. The allocation of information at two locations is shown in FIG. 6, but any other allocation method may be used without any problem as long as the eight patterns shown in FIG. 5 can be stored.

Note that the above embodiment is intended to increase the resolution of pixel positions, but not to increase the resolution, that is, the ability to distinguish between two pixels. Furthermore, although two lines that are close to each other cannot be expressed in the present invention, it is rare for lines to be close to each other on a high-definition display, so this does not pose a major problem in practice.

Note that in the above embodiment, a display is used in which the scanning speed in the horizontal direction is faster than in the vertical direction, but in the case of a CRT display whose scanning speed is faster in the vertical direction, vertical and horizontal scanning, horizontal and vertical, top and bottom,
The same result can be obtained by switching the relationship between left and right.

Effects of the Invention According to the present invention, the actual resolution can be doubled by simply adding 2 bits to each memory cell of the memory, which is effective in reducing jagging. Additionally, as the resolution increases, flickering will generally increase unless the scanning speed of the CRT display is increased, but in the present invention, flickering is prevented without increasing the scanning speed because light is emitted in pairs of two pixels. be able to.

[Brief explanation of the drawing]

FIGS. 1a and 1b are diagrams showing display states of a conventional graphic display, FIG. 2 is a block diagram of a device implementing a method for controlling a graphic display according to an embodiment of the present invention, and FIG. 3 is a diagram showing the display state of a conventional graphic display. Detailed configuration diagram of the frame memory of the device, Figure 4 A, B,
C, E, FIGS. 5a to 5h, and 6 are explanatory diagrams of the operation of the same embodiment. 1... Frame memory, 2... Buffer, 3...
... Auxiliary buffer, 4 ... Color map, 5 ... Delay circuit, 6 ... DA converter, 7 ... CRT display, 8 ... Timing generation section, 9 ... Processing section.

Claims (1)

[Claims] 1 having a raster scan type graphic cathode ray tube display and m×n memory cells,
It has a frame memory, converts 2 pixel pairs into a pixel column, adds 2 bits to each memory cell of the frame memory, and adds 2 bits to each memory cell in the frame memory.
A method for controlling a graphic display characterized in that 4 bits of a memory cell are used to specify whether or not to emit light for odd and even scans and whether to delay the light emission timing by H/(2n) (H is horizontal scanning time). .