JPH0447502B2 - - Google Patents
Info
- Publication number
- JPH0447502B2 JPH0447502B2 JP57112389A JP11238982A JPH0447502B2 JP H0447502 B2 JPH0447502 B2 JP H0447502B2 JP 57112389 A JP57112389 A JP 57112389A JP 11238982 A JP11238982 A JP 11238982A JP H0447502 B2 JPH0447502 B2 JP H0447502B2
- Authority
- JP
- Japan
- Prior art keywords
- carrier wave
- resistor
- phase
- controlled oscillator
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
- H04L27/2272—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals using phase locked loops
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Networks Using Active Elements (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【発明の詳細な説明】
発明の技術分野
本発明は、PSK信号を同期検波する為の搬送
波を安定に再生する搬送波再生回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a carrier wave regeneration circuit that stably regenerates a carrier wave for synchronously detecting a PSK signal.
従来技術と問題点
第1図は、4相PSK信号を同期検波する為の
搬送波を再生する従来の搬送波再生回路の一例の
ブロツク図であり、1は4相PSK信号の入力端
子、2,3は位相検波器、4は90°移相器、5は
ベースバンド処理回路、6は電圧制御発振器、7
はループフイルタであり、7′はループフイルタ
の他の例を示すものである。電圧制御発振器6の
出力信号は、位相検波器2及び90°移相器4を介
して位相検波器3に加えられ、入力4相PSK信
号が検波され、検波出力はベースバンド処理回路
5に加えられる。ベースバンド処理回路5では、
電圧制御発振器6の出力信号と入力4相PSK信
号の搬送波成分との位相差をθとすると、例え
ば、sin4θの信号を出力し、ループフイルタ7を
介して電圧制御発振器6の制御電圧とし、位相差
θが零になるように電圧制御発振器6の出力信号
位相が制御されることになり、入力4相PSK信
号の搬送波成分に位相同期した搬送波が電圧制御
発振器6の出力信号として再生されることにな
る。Prior Art and Problems Figure 1 is a block diagram of an example of a conventional carrier wave regeneration circuit that regenerates a carrier wave for synchronously detecting a 4-phase PSK signal. is a phase detector, 4 is a 90° phase shifter, 5 is a baseband processing circuit, 6 is a voltage controlled oscillator, 7
is a loop filter, and 7' shows another example of the loop filter. The output signal of the voltage controlled oscillator 6 is applied to the phase detector 3 via the phase detector 2 and the 90° phase shifter 4, the input 4-phase PSK signal is detected, and the detected output is added to the baseband processing circuit 5. It will be done. In the baseband processing circuit 5,
If the phase difference between the output signal of the voltage controlled oscillator 6 and the carrier wave component of the input 4-phase PSK signal is θ, then, for example, a signal of sin4θ is outputted, passed through the loop filter 7 as the control voltage of the voltage controlled oscillator 6, and the phase difference is The output signal phase of the voltage controlled oscillator 6 is controlled so that the phase difference θ becomes zero, and a carrier wave that is phase synchronized with the carrier wave component of the input 4-phase PSK signal is reproduced as the output signal of the voltage controlled oscillator 6. become.
このような位相同期ループを有する搬送波再生
回路のループフイルタとしては、抵抗とコンデン
サとを組合せたローパスフイルタが一般的である
が、7′で示すように、演算増幅器8を用いたア
クテイブフイルタによるローパスフイルタを用い
る場合もある。 As a loop filter for a carrier wave recovery circuit having such a phase-locked loop, a low-pass filter that combines a resistor and a capacitor is generally used. A filter may also be used.
又位相検波器2,3の位相検波感度や電圧制御
発振器6の電圧感度が一定ではなく、製品によつ
てばらつきが生じるものであり、又伝送路の帯域
制限に応じて位相検波感度が異なるものとなる。
従つて、製品毎に又使用条件により各種の感度を
調整する必要がある。その為、従来は、例えば、
入力端子1に減衰器を接続して入力PSK信号の
レベルを調整する手段や位相同期ループに増幅器
を接続してループゲインを調整する手段等が採用
されていた。しかし構成が複雑化すると共に可変
範囲が狭い欠点があり、又増幅器は広帯域の構成
が必要となり、高価となる欠点がある。又アクテ
イブフイルタをループフイルタとして用いた場合
は、演算増幅器の入力側のインピーダンスと帰還
用のインピーダンスとの比に応じたゲインを得る
ことができるが、7′で示す構成では、DCゲイン
が大きくなり過ぎるので、位相同期ループの安定
性に問題が生じる欠点がある。 Furthermore, the phase detection sensitivity of the phase detectors 2 and 3 and the voltage sensitivity of the voltage controlled oscillator 6 are not constant and vary depending on the product, and the phase detection sensitivity varies depending on the band limit of the transmission path. becomes.
Therefore, it is necessary to adjust various sensitivities for each product and depending on the conditions of use. Therefore, conventionally, for example,
A method for adjusting the level of the input PSK signal by connecting an attenuator to the input terminal 1, and a method for adjusting the loop gain by connecting an amplifier to the phase-locked loop were adopted. However, there are disadvantages in that the configuration is complicated and the variable range is narrow, and the amplifier requires a broadband configuration and is expensive. Also, when an active filter is used as a loop filter, it is possible to obtain a gain according to the ratio of the impedance on the input side of the operational amplifier and the feedback impedance, but in the configuration shown by 7', the DC gain becomes large. This has the drawback of causing problems with the stability of the phase-locked loop.
発明の目的
本発明は、簡単な構成により位相同期ループゲ
インの設定を可能とし、安定な搬送波の再生を行
うことができるようにすることを目的とするもの
である。以下実施例について詳細に説明する。OBJECTS OF THE INVENTION It is an object of the present invention to make it possible to set a phase-locked loop gain with a simple configuration and to perform stable carrier wave reproduction. Examples will be described in detail below.
発明の実施例
第2図は本発明の実施例のブロツク図であり、
第1図と同一符号は同一部分を示す。本発明に於
ては、位相同期ループのループフイルタ9を、演
算増幅器10と、この演算増幅器10の入力端子
側の第1の抵抗R1と、帰還用の直列接続の第2
の抵抗R2及びコンデンサC1と、このコンデン
サC1に並列接続した第3の抵抗R3とから構成
したものである。このループフイルタ9のゲイン
は、R2+R3/R1で表されるものとなり、又
ACゲインはコンデンサC1と並列の第3の抵抗
R3の選定により大きくなり過ぎることがないよ
うにすることができるものとなる。従つて所望の
ループゲインを得るように第1の抵抗R1を調整
した場合でも、位相同期ループを安定に動作させ
ることができるものとなる。Embodiment of the invention FIG. 2 is a block diagram of an embodiment of the invention.
The same reference numerals as in FIG. 1 indicate the same parts. In the present invention, the loop filter 9 of the phase-locked loop includes an operational amplifier 10, a first resistor R1 on the input terminal side of the operational amplifier 10, and a second resistor connected in series for feedback.
, a resistor R2 and a capacitor C1, and a third resistor R3 connected in parallel to the capacitor C1. The gain of this loop filter 9 is expressed as R2+R3/R1, and
The AC gain can be prevented from becoming too large by selecting the third resistor R3 in parallel with the capacitor C1. Therefore, even when the first resistor R1 is adjusted to obtain a desired loop gain, the phase-locked loop can be operated stably.
第3図は本発明の他の実施例の要部のループフ
イルタの部分を示すもので、増幅器11の差動出
力信号を第1の抵抗R4,R5を介して演算増幅
器12の反転入力端子及び非反転入力端子に加え
る接続構成とし、又演算増幅器12の帰還用とし
て第2,第3の抵抗R6,R7とコンデンサC2
とを接続したものである。この実施例のループフ
イルタは、前述の実施例と同様に、位相同期ルー
プの動作を不安定にすることなく、ループゲイン
を任意に調整することができると共に、演算増幅
器12に差動出力信号を入力させることにより、
ドリフトを小さくすることができる利点が生じる
ものである。 FIG. 3 shows the essential loop filter of another embodiment of the present invention, in which the differential output signal of the amplifier 11 is passed through the first resistors R4 and R5 to the inverting input terminal of the operational amplifier 12 and The connection configuration is such that it is added to the non-inverting input terminal, and second and third resistors R6 and R7 and a capacitor C2 are used for feedback of the operational amplifier 12.
This is a connection between Like the previous embodiment, the loop filter of this embodiment can arbitrarily adjust the loop gain without destabilizing the operation of the phase-locked loop, and also outputs a differential output signal to the operational amplifier 12. By inputting
This has the advantage that drift can be reduced.
発明の効果
以上説明したように、本発明は、受信PSK信
号を同期検波する為の再生搬送波を出力する電圧
制御発振器6に、PSK信号の搬送波と再生搬送
波との位相差に対応した制御電圧を加えるループ
フイルタ9を、高利得の演算増幅器10,12
と、この入力側のループゲイン調整用の第1の抵
抗R1,R4と、演算増幅器10,12の出力端
子と入力端子との間に直列接続した第2の抵抗R
2,R6とコンデンサC1,C2と、このコンデ
ンサC1,C2に並列に接続した第3の抵抗R
3,R7とにより構成したものであり、第3の抵
抗R3,R7によりACゲインが極端に大きくな
ることはなく、第1の抵抗R1,R6の調整によ
りループゲインを調整した場合でも、位相同期ル
ープの動作を安定化することができる。Effects of the Invention As explained above, the present invention applies a control voltage corresponding to the phase difference between the carrier wave of the PSK signal and the recovered carrier wave to the voltage controlled oscillator 6 that outputs the recovered carrier wave for synchronously detecting the received PSK signal. The loop filter 9 to be added is replaced by high gain operational amplifiers 10 and 12.
, first resistors R1 and R4 for loop gain adjustment on the input side, and a second resistor R connected in series between the output terminal and input terminal of the operational amplifiers 10 and 12.
2. R6, capacitors C1 and C2, and a third resistor R connected in parallel to these capacitors C1 and C2.
3, R7, the AC gain will not become extremely large due to the third resistor R3, R7, and even if the loop gain is adjusted by adjusting the first resistor R1, R6, the phase synchronization will be maintained. The operation of the loop can be stabilized.
従つて、PSK信号を同期検波する位相検波器
2,3や電圧制御発振器6の感度等のばらつきに
対応して、再生搬送波を出力する電圧制御発振器
6を含む位相同期ループゲインを調整した時に、
ACゲインも適当な値とすることができるから、
安定な搬送波再生を行わせることができる利点が
ある。 Therefore, when adjusting the phase-locked loop gain including the voltage-controlled oscillator 6 that outputs the recovered carrier wave in response to variations in the sensitivity of the phase detectors 2 and 3 that synchronously detect PSK signals and the voltage-controlled oscillator 6,
Since the AC gain can also be set to an appropriate value,
There is an advantage that stable carrier wave regeneration can be performed.
第1図は従来の搬送波再生回路のブロツク図、
第2図は本発明の一実施例のブロツク図、第3図
は本発明の他の実施例の要部ブロツク図である。
1は入力端子、2,3は位相検波器、4は90°
移相器、5はベースバンド処理回路、6は電圧制
御発振器、7,7′,9はループフイルタ、10,
12は演算増幅器、11は差動出力の増幅器、R
1〜R7は抵抗、C1,C2はコンデンサであ
る。
Figure 1 is a block diagram of a conventional carrier wave regeneration circuit.
FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a block diagram of essential parts of another embodiment of the present invention. 1 is input terminal, 2 and 3 are phase detectors, 4 is 90°
phase shifter, 5 is a baseband processing circuit, 6 is a voltage controlled oscillator, 7, 7', 9 are loop filters, 10,
12 is an operational amplifier, 11 is a differential output amplifier, R
1 to R7 are resistors, and C1 and C2 are capacitors.
Claims (1)
電圧制御発振器から出力し、前記PSK信号の搬
送波と前記再生搬送波との位相差をベースバンド
処理回路により検出し、該位相差に対応した信号
をループフイルタを介して前記電圧制御発振器の
制御電圧とする搬送波再生回路に於て、 前記電圧制御発振器の制御電圧を出力する前記
ループフイルタを、高利得の演算増幅器と、該演
算増幅器の入力側のループゲイン調整用の第1の
抵抗と、前記演算増幅器の出力端子と入力端子と
の間に直列接続した第2の抵抗及びコンデンサ
と、該コンデンサに並列に接続した第3の抵抗と
により構成した ことを特徴とする搬送波再生回路。[Claims] 1. A regenerated carrier wave for synchronously detecting a PSK signal is output from a voltage controlled oscillator, a phase difference between the carrier wave of the PSK signal and the regenerated carrier wave is detected by a baseband processing circuit, and the phase difference is detected by a baseband processing circuit. In the carrier wave regeneration circuit which outputs the control voltage of the voltage controlled oscillator through a loop filter, a signal corresponding to the voltage controlled oscillator is used as the control voltage of the voltage controlled oscillator. A first resistor for loop gain adjustment on the input side of the amplifier, a second resistor and a capacitor connected in series between the output terminal and the input terminal of the operational amplifier, and a third resistor and a capacitor connected in parallel to the capacitor. A carrier wave regeneration circuit comprising a resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112389A JPS594257A (en) | 1982-06-29 | 1982-06-29 | Carrier regenerative circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57112389A JPS594257A (en) | 1982-06-29 | 1982-06-29 | Carrier regenerative circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS594257A JPS594257A (en) | 1984-01-11 |
| JPH0447502B2 true JPH0447502B2 (en) | 1992-08-04 |
Family
ID=14585445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57112389A Granted JPS594257A (en) | 1982-06-29 | 1982-06-29 | Carrier regenerative circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594257A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0691561B2 (en) * | 1988-11-22 | 1994-11-14 | 日本電気株式会社 | Carrier wave synchronization circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS547182B2 (en) * | 1971-09-11 | 1979-04-04 |
-
1982
- 1982-06-29 JP JP57112389A patent/JPS594257A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS594257A (en) | 1984-01-11 |
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