JPH0462465B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor resistance element used in semiconductor integrated circuits and the like.

[Conventional technology]

Conventionally, this type of semiconductor resistance element (hereinafter referred to as a resistance element) is mounted on a P-type semiconductor substrate (hereinafter referred to as a P substrate) to which the lowest potential (hereinafter referred to as Vee) used on a circuit is applied. The highest potential used on the circuit (hereinafter referred to as Vcc
That's what it means. ) is applied to the N-type impurity region (hereinafter referred to as
This is called the N area. ) is formed by providing contacts at both ends of a P ⁺ type impurity region (hereinafter referred to as P ⁺ region) selectively provided on the top.

The pattern shape of the P ⁺ area is usually composed of a combination of rectangles. In other words, the PN between the P substrate and the N region
The junction is in a reverse bias state because Vee is applied to the P substrate and Vcc is applied to the N region.
The PN junction between the P ⁺ regions is used as a resistive element
Since the potential applied to the P ⁺ region was between Vcc and Vee, it was in a reverse bias state, and each PN junction was therefore electrically isolated.

Furthermore, this type of resistance element may be constructed by applying a voltage on the high side of the potential applied to the P ⁺ region used as a resistance element to the N region mentioned above, and it is natural that the voltage between the N region and the P ⁺ region is The PN junction was designed to be maintained in a reverse bias state.

[Problem that the invention seeks to solve]

Next, problems with such a conventional semiconductor resistance element will be explained with reference to the drawings.

FIG. 4a is a plan view showing a pattern layout of an example of a conventional resistance element, and FIG. 4b is a sectional view taken along line A-A' in FIG. 4a.

That is, 11 is a P substrate, 12 is an N region, and 13 is a P substrate.
is a P ⁺ region and is used as a resistive element. 1
4 is an N ⁺ type impurity region (hereinafter referred to as N ⁺ -N region) for supplying potential to the N region 12, and 15 is a P region.
P ⁺ type impurity region (hereinafter referred to as P ⁺ -P substrate) for supplying potential to the substrate 11, 16 an insulating film, 7
1 to 74 are openings for taking out electrodes (hereinafter referred to as openings), 81 to 84 are wiring lines, and 12a is an N ⁺ type impurity buried layer (hereinafter referred to as N ⁺ buried layer). As mentioned above, the wiring 81 has
Vcc is applied to the wiring 84, and Vee is applied to the wiring 84.

Recent advances in integrated circuits have led to higher integration and lower power consumption.As a result, resistive elements have also become smaller and processes have begun to utilize high-value layer resistances (for example, ρs10KΩ/~). Therefore, a phenomenon has occurred in which the resistance value deviates significantly due to a difference in the driving voltage of the resistor.

In other words, a change in the reverse bias voltage applied to the PN junction between the N region 12 and the P ⁺ region 13 changes the spread width of the depletion layer formed at the PN junction surface of the P ⁺ region 13, so that the resistance of the resistor element changes. Vary the value. In particular, the larger the layer resistance value (ρs) of the resistive element, the more
The spread of the depletion layer changes in response to changes in reverse bias voltage, and as the resistance element becomes smaller, the spread of the depletion layer takes up a larger proportion of the resistance width and thickness. Become. Therefore, in a circuit configuration that requires a balance in the resistance value itself, it is necessary to design a pattern that takes into account the variation in the resistance value, which has the disadvantage that it takes time to design.

Furthermore, in the conventional resistance element described above, as shown in Figure 4c, noise on the signal line increases the signal voltage to Vcc + V _F value (here, V _F value is the forward bias voltage at which forward current flows into the PN junction). , usually
It is around 700mV. ) or more, N area 12 and
The PN junction between the P ⁺ regions 13 is forward biased and a forward current i flows, which is multiplied by β (β indicates the current amplification factor and is approximately 1 to 10 in a normal parasitic PNP transistor) β,i flows in the direction of the P-substrate 11, causing so-called parasitic PNP transistor operation, which causes circuit malfunctions, and furthermore, has the drawback of causing wiring to melt due to large currents.

Furthermore, the conventional resistance element described above has an N region 12
Since a Vcc source is required to apply to the Vcc line, the 12 patterns in the N area must be extended to the position where the Vcc line is wired, which complicates the pattern layout and increases the chip size due to the additional area. There were flaws.

FIG. 5a is a plan view showing the pattern layout of the other conventional resistor element described in the prior art section, and FIG. 5b is a sectional view taken along the line A-A' in FIG. 5a. The difference from FIG. 4 is that a wiring 82 is used in place of the wiring 81 in FIG. 4.

As mentioned above, Vee is applied to the wiring 84, and the N region 12 is connected to the high voltage side of the voltage driving the P ⁺ region 13 (the wiring 8 shown in FIGS. 5a and 5b).
Since the potential 2) is applied, in normal use, the variation in resistance value due to the difference in drive voltage to the resistor in the resistor element mentioned above is solved, and the disadvantages of complexity in pattern layout and large chip size are also solved. However, a new drawback has arisen that did not pose a problem with the above-mentioned resistance element.

In the conventional resistance element shown in FIGS. 5a and 5b, the high-value side and low-value side of the voltage that drives the P ⁺ region 13 must be provided as electrode openings 72 and 73, respectively.
When using a resistance element, the polarity is determined. Therefore, for methods such as the well-known master slice method and gate array method, in which various electric circuits can be constructed by simply changing the wiring on a fixed integrated circuit element pattern, the polarity of the resistive element is fixed. This has the drawback of limiting its use.

Furthermore, in the conventional resistance element described above, the noise on the signal line on the wiring 83 side causes the signal voltage to
When the potential is higher than that of the second side, N region 12 and P ⁺
The PN junction between regions 13 is forward biased, and therefore a parasitic PNP transistor operation similar to the malfunction that occurred in the resistor element described above occurs, causing circuit malfunction and furthermore, causing wiring to melt due to large currents. There were flaws.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor resistance element with a simple pattern layout, which solves the above-mentioned drawbacks.

[Means for solving problems]

The semiconductor resistance element of the present invention includes an N-type impurity region provided on one main surface of a P-type semiconductor substrate, a P-type impurity region provided within the N-type impurity region, and a region at each end of the P-type impurity region. a wiring provided in contact with a surface of the N-type impurity region that is in contact with a surface and both ends of the P-type impurity region, which is in ohmic contact with the P-type impurity region and has shot-key contact with the N-type impurity region; There is.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1a is a plan view showing a pattern layout of a first embodiment of the present invention, and FIG. 1b is a sectional view taken along line A-A' in FIG. 1a.

That is, an opening reaching the P substrate 11 is formed on the insulating film 16 covering the P substrate 11, which has the P ⁺ region 13 selectively provided on the N region 12 selectively provided on the P substrate 11. 72a, 73a, and 74 are provided.

Here, the opening 74 is an opening for taking out the electrode of the P + -P substrate region 15 provided on the P substrate 11 in order to apply Vee to the P substrate 11, and the opening 74 is an opening for taking out the electrode of the P ⁺ -P substrate region 15 provided on the P substrate 11. is used as a resistive element
This is an opening for electrode extraction provided at both ends of the P ⁺ region 13 so as to include the N region 12 .

Then, by depositing a metal thin film and patterning it as a wiring, the wiring 82a,
Opening part 72a under 83a, N area 12 under 73a
Short key barrier regions 92 and 93 are formed in the P ⁺ region 13 and the opening 74 below the wiring 84.
An ohmic contact surface is formed for the lower P ⁺ -P substrate region 15 .

Commonly used metal thin films include Al, Pt-Al,
There are Ti-Al, Ti-W-Al, etc.

The resistance element structure formed as described above is
As shown in the equivalent circuit shown in FIG. 1c, the PN junction surface J12 between the P substrate 11 and the N region 12 is
Since Vee is applied to the PN junction surface J32 between the P ⁺ region 13 and the N region 12, the voltage applied to the N region 12 is in a reverse bias state. Since the voltage on the high side applied to the ⁺ region 13 becomes a value through one Schottky barrier, that is, one forward potential difference (hereinafter referred to as V _SBD ) of the Schottky diode SBD, the voltage applied to the P ⁺ region 13 and A forward bias state occurs at some points between the two, and the maximum forward bias point is
This is the P ⁺ region 13 near which the high-value side voltage of the P ⁺ region 13 is input, and the potential difference is V _SBD .

The relationship between current and voltage when the PN junction is forward biased is approximately as follows: I=Is・exp(V/V _T )...(1) (Is is the saturation current value, V _T is the thermal voltage value) expressed.

Normally, the order of current and voltage in a PN junction is about I = 1 μA and V = 700 mV, and
The forward bias of the Schottky diode is on the order of the order of V=450 mV for I=1 μA.

Therefore, the forward bias current for one V _SBD above is:
When calculated using equation (1), I=1×10 ^-4 μA, which is of the order of magnitude, and there is no problem in actual use. Therefore, the reverse bias voltage applied to the PN junction surface J32 can be made extremely small compared to the conventional example.
The depletion layer that spreads within the P ⁺ region 13 can be suppressed to a minimum, and the bias state of the PN junction surface J32 is constant even when the driving voltage applied to the resistor element is different, so the resistance value does not fluctuate. Does not occur.

Furthermore, in the first embodiment, since the N region 12 is always clamped by one step of V _SBD from the voltage on the high side of the drive voltage applied to the resistor element, the polarity when using the resistor does not matter. Furthermore, in the forward bias state between the PN junction surface J32, the maximum potential difference is V _SBD
Since there is only one piece, P ⁺ area 13 - N area 12
The so-called parasitic PNP transistor between the -P substrate 11 is not driven.

Furthermore, in the first embodiment, since the power applied to the N region 12 is a high-value voltage that drives the resistor, it can be arranged freely in the pattern layout, and there is no need to worry about polarity, so it is easy to use. You will no longer be subject to the restrictions of

FIG. 2a is a plan view showing the pattern layout of the second embodiment of the present invention, and FIG. 2b is A of FIG. 2a.
-A' line sectional view.

In this second embodiment, the opening 72 shown in FIG.
They are exactly the same except for the pattern shapes under a and 73a.

That is, the openings 72b and 73b are openings provided at both ends of the P ⁺ region 13 used as a resistance element, and are located on the P ⁺ region 13 surrounded on four sides by the openings 72b and 73b. This is an example in which an N region 12 is opened in the area.

In the second embodiment, the reverse bias characteristics of the Schottky diode SBD are harder than those in the first embodiment, so the difference between the high and low values of the drive voltage of the resistor element is particularly important. is large (for example,
10V or more. ), but perfect circuit operation can be expected because no leakage current occurs.

FIG. 3 is a plan view showing a pattern layout of a third embodiment of the present invention.

This embodiment is completely the same as the second embodiment except that the pattern shapes under the openings 72a and 73a shown in FIG. 1 are different. That is, the openings 72c and 73c are provided so as to enlarge the shot key barrier regions 92a and 93a, and the effect is similar to that of the first embodiment.

〔Effect of the invention〕

As explained above, in the present invention, the electrode lead-out electrode of the resistance element is provided so as to span the N region and the P ⁺ region, so that the Schottky diode formed between the electrode metal and the N region is inserted. As a result, the resistance value can be kept constant regardless of fluctuations in the drive voltage, making it easy and quick to design resistance patterns for the recent advances in pattern miniaturization and lower power consumption in circuits. Furthermore, since malfunctions due to noise can be prevented, the present invention can be applied to semiconductor resistive elements near input/output terminals, which were previously particularly vulnerable to noise and had to take a lot of effort in terms of circuit and pattern layout and increase the chip size. Since it can be used with only semiconductor resistive elements, it is not subject to any restrictions on circuit usage and can be easily designed. In addition, since it can be used regardless of polarity, it can be easily used in semi-custom ICs that have been developed in recent years. Furthermore, since the layout can be easily designed and patterned freely, the chips can be made smaller and further improvement in yield can be expected. Therefore, according to the present invention, it is possible to easily design large-scale integrated circuits using high-precision semiconductor resistive elements with high reliability for future advances in miniaturization, high performance, and even semi-customization. This has the effect that it can be manufactured with good yield.

[Brief explanation of drawings]

FIG. 1a is a plan view showing the pattern layout of the first embodiment of the present invention, and FIG. 1b is A of FIG. 1a.
-A' line sectional view, Fig. 1c is an equivalent circuit diagram of Fig. 1a, Fig. 2a is a plan view showing the pattern layout of the second embodiment of the present invention, Fig. 2b is Fig. 2 FIG. 3 is a plan view showing the pattern layout of the third embodiment of the present invention; FIG.
is a plan view showing a pattern layout of a conventional example,
Fig. 4b is a cross-sectional view taken along the line A-A' in Fig. 4a, Fig. 4c is an explanatory diagram of the parasitic PNP transistor operation, and Fig. 5
FIG. 5a is a plan view showing another conventional pattern layout, and FIG. 5b is a sectional view taken along line A-A' in FIG. 5a. 11...P substrate, 12...N region, 12a...
N ⁺ buried layer, 13...P ⁺ region, 14...N ⁺ -N
region, 15...P ⁺ -P substrate, 16... insulating film,
72a, 72b, 73a, 73b, 74...opening portion, 82a, 82b, 83a, 83b, 84...
Wiring, 92, 92a, 93, 93a... Schottky barrier region, J12, J32... PN junction surface, SBD... Schottky diode.

Claims (1)

[Claims] 1. An N-type impurity region provided on one main surface of a P-type semiconductor substrate, a P-type impurity region provided within the N-type impurity region, and surfaces of both ends of the P-type impurity region and the P-type impurity region. The N in contact with both ends of
1. A semiconductor resistance element comprising a wiring provided in contact with a surface of a type impurity region and having an ohmic contact with the P type impurity region and a Schottky contact with the N type impurity region.