JPH0472640U - - Google Patents
Info
- Publication number
- JPH0472640U JPH0472640U JP1990116314U JP11631490U JPH0472640U JP H0472640 U JPH0472640 U JP H0472640U JP 1990116314 U JP1990116314 U JP 1990116314U JP 11631490 U JP11631490 U JP 11631490U JP H0472640 U JPH0472640 U JP H0472640U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- heat dissipation
- semiconductor chip
- fins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Description
第１図ａ，ｂ，ｃは本考案の一実施例の断面図
、正面図および側面図、第２図ａ，ｂ，ｃは本考
案の第二の実施例の断面図、正面図および側面図
、第３図ａ，ｂ，ｃは従来の半導体装置の断面図
、正面図および側面図、第４図は従来の絶縁型パ
ツケージの熱分布を示す模式的断面図、第５図は
従来と実施例の絶縁型のパツケージの最大許容損
失（自立）を比較した特性図である。
１，１ａ……半導体チツプマウント用フレーム
、２……半導体チツプ、３……アルミワイヤ、４
……リード、５，５ａ……放熱用フイン、６……
レーザー捺印用領域。
Figures 1 a, b, and c are sectional views, front views, and side views of one embodiment of the present invention; Figures 2 a, b, and c are sectional views, front views, and side views of a second embodiment of the present invention. Figures 3a, b, and c are cross-sectional views, front views, and side views of conventional semiconductor devices, Figure 4 is a schematic cross-sectional view showing the heat distribution of a conventional insulated package, and Figure 5 is a conventional semiconductor device. FIG. 3 is a characteristic diagram comparing the maximum permissible loss (self-reliance) of insulated packages of Examples. 1, 1a...Frame for semiconductor chip mount, 2...Semiconductor chip, 3...Aluminum wire, 4
... Lead, 5, 5a ... Heat dissipation fin, 6 ...
Area for laser marking.
Claims (1)
チツプを配設し、これを樹脂成形し封入して形成
された半導体装置において、前記樹脂の表面にこ
の樹脂を用いた放熱用フインが一体成形により形
成されたことを特徴とする半導体装置。 ２ 半導体チツプマウント用フレームの一部が、
放熱用フインの内部まで延長されている請求項１
記載の半導体装置。 ３ 放熱用フインが、ストライプ状に形成された
請求項１または２記載の半導体装置。[Claims for Utility Model Registration] 1. In a semiconductor device formed by disposing a semiconductor chip on a frame for mounting a semiconductor chip and molding and encapsulating this with a resin, heat dissipation using this resin on the surface of the resin A semiconductor device characterized in that fins are formed by integral molding. 2 A part of the semiconductor chip mount frame is
Claim 1: The heat radiation fin extends to the inside of the heat dissipation fin.
The semiconductor device described. 3. The semiconductor device according to claim 1 or 2, wherein the heat dissipation fins are formed in a stripe shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990116314U JPH0472640U (en) | 1990-11-06 | 1990-11-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990116314U JPH0472640U (en) | 1990-11-06 | 1990-11-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0472640U true JPH0472640U (en) | 1992-06-26 |
Family
ID=31864130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990116314U Pending JPH0472640U (en) | 1990-11-06 | 1990-11-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0472640U (en) |
-
1990
- 1990-11-06 JP JP1990116314U patent/JPH0472640U/ja active Pending
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