JPH05110415A - Tri-state output circuit - Google Patents

Abstract

PURPOSE:To reduce the occupancy area of the output circuit in a chip by making the number of components required for the circuit configuration less than that of a conventional circuit in the tri-state output circuit. CONSTITUTION:The output is controlled by connecting a transfer gate 4 operated in response to a control signal E, a P MOS transistor(TR) 5 and an NMOS TR 6 operated in an opposite phase to the gate 4, a PMOS TR 2 and an NMOS TR 3 operated by a data signal D to the input of an output stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 3-state output circuit, and more particularly to circuit construction of a 3-state output circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional three-state output circuit includes an inverter 1 for generating a reverse phase signal -E of a signal E, a NAND gate 9 for receiving a data signal D and a control signal -E. , A NOR gate 10 that receives the data signal D and the control signal E, a P-type MOS transistor 7 that receives the output of the NAND gate 9 and drives it to the power supply VDD side, and an N type that receives the output of the NOR gate 10 and drives it to the ground side. Type MOS transistor 8 and P type MOS
It has a structure in which the drains of the transistor 7 and the N-type MOS transistor 8 are connected to form an output X.

When the control signal E is "L", NA
Both the ND gate 9 and the NOR gate 10 receive the data signal D
, And the in-phase of the data signal D is output to the output X. When the control signal E is "H", the NAND gate 9 outputs "H" regardless of the data signal D, and the P-type MOS transistor 7 is "off".
The NOR gate 10 outputs "L", the N-type MOS transistor 8 is also "off", and the output X is in a high impedance state. The truth diagram of this circuit is shown in FIG.

[0004]

However, in this conventional 3-state output circuit, since the circuit configuration is complicated and the number of elements is large, the output circuit occupies a large area in the chip, and the chip is not designed for mask design. There was a problem that the size became large.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel three-state output circuit which can solve the above-mentioned problems inherent in the prior art. To do.

[0006]

In order to achieve the above object, a three-state output circuit according to the present invention has a transfer gate which receives a control signal and operates according to the signal, and a transfer gate having a reverse phase. The output control is provided by using the pull-up and pull-down switches that operate in accordance with the above, and the pull-up and pull-down switches that operate according to the data signal.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be specifically described with reference to the drawings for each of its preferred embodiments.

FIG. 1 is a circuit configuration diagram showing a first embodiment according to the present invention.

Referring to FIG. 1, when the control signal E is "L", the transfer gate 4 is "on",
At the same time, since the P-type MOS transistor 5 and the N-type MOS transistor 6 are turned “off”, the inverted signal of the data signal D is transmitted to the gate of the P-type MOS transistor 7 and the gate of the N-type MOS transistor 8, and thus the output X Has
A signal in phase with the data signal D is output.

When the control signal E is "H", the transfer gate 4 is "off".
Transistor 5 and N-type MOS transistor 6 are "on"
Therefore, regardless of the data signal D, the P-type MOS transistor 7 is "off" and the N-type MOS transistor 8 is also "off", so that the output X is in a high impedance state.

Although the conventional circuit requires 12 elements for the circuit configuration, the circuit of the first embodiment can be configured with 10 elements.

FIG. 2 is a circuit configuration diagram showing a second embodiment according to the present invention.

Referring to FIG. 2, the circuit according to the second embodiment is a circuit for controlling n 3-state output circuits by one control signal E, and includes an inverter 1, a P-type MOS transistor 5 and an N-type. The MOS transistor 6 is commonly used to control each 3-state output circuit.

In the conventional circuit, since only the inverter 1 can be shared, the number of elements required for the circuit configuration is 10n + 2, whereas in the circuit of the second embodiment, the P-type MOS transistor 5 which is a pull-up switch and the pull-down switch. Since the N-type MOS transistor 6 can be shared, the number of required elements is 6n + 4.

That is, in the circuit of the second embodiment, the required number of elements can be reduced by 4n-2.

[0016]

As described above, according to the present invention,
By using the transfer gate and the pull-up and pull-down switches instead of the NAND gate and the NOR gate, the number of elements necessary for the circuit configuration is reduced, so that the area occupied by the output circuit in the chip can be reduced. The effect that the chip size can be reduced in the mask design is obtained.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment according to the present invention.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is a truth diagram.

[Explanation of symbols]

 1 ... Inverter 2, 5, 7 ... P-type MOS transistor 3, 6, 8 ... N-type MOS transistor 4 ... Transfer gate 9 ... NAND gate 10 ... NOR gate

Claims (2)

[Claims] 1. A transfer gate that operates according to a control signal, a pull-up switch and a pull-down switch that operate in opposite phases to the transfer gate, and a pull-up switch that operates complementarily to each other according to a data signal. A pull-down switch and a MOS transistor complementary connected to each other between power supplies are provided, and one output of the transfer gate is connected to an output part of the both pull-up switches and one gate of the MOS transistor, and A three-state output circuit, wherein the output is controlled by connecting the outputs of the two to the output parts of the both pull-down switches and the other gate of the MOS transistor. 2. When forming a circuit for controlling n (n is a positive integer) number of 3-state output circuits by one control signal, an inverter and the pull-up that operates in a phase opposite to that of the transfer gate. And a pull-down switch are commonly used.
The 3-state output circuit described in 1.