JPH05183095A - Semiconductor device packaging - Google Patents
Semiconductor device packagingInfo
- Publication number
- JPH05183095A JPH05183095A JP3359856A JP35985691A JPH05183095A JP H05183095 A JPH05183095 A JP H05183095A JP 3359856 A JP3359856 A JP 3359856A JP 35985691 A JP35985691 A JP 35985691A JP H05183095 A JPH05183095 A JP H05183095A
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- semiconductor device
- lead
- ground
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 半導体装置周囲のガルウイング状に折曲して
その先端を基板の信号回路用接続パッドに接続した信号
線路用リードを、高速信号を伝送損失少なく効率良く伝
えることのできる半導体装置実装体を得る。
【構成】 信号線路用リード21両側にガルウイング状
に折曲したグランド用リード61をそれぞれ並べて備え
て、それらのグランド用リード61先端を基板のグラン
ド回路用接続パッド82に接続する。それと共に、信号
線路用リード21の幅Wを一定値に保持して、信号線路
用リード21下方の基板31に設けたグランドプレーン
71とその上方の信号線路用リード21との間の距離H
の信号線路用リード21先方に向けての減少量に合わせ
て、隣合う信号線路用リード21とグランド用リード6
1との側面間の距離Sを信号線路用リード21先方に向
けて漸次増大させる。
(57) [Abstract] [Purpose] A signal line lead, which is bent in a gull wing shape around a semiconductor device and whose tip is connected to a signal circuit connection pad of a substrate, is capable of efficiently transmitting a high-speed signal with little transmission loss. A semiconductor device package that can be obtained is obtained. A gull-wing bent ground lead 61 is arranged on both sides of the signal line lead 21, and the tips of the ground lead 61 are connected to a ground circuit connection pad 82 of the substrate. At the same time, the width W of the signal line lead 21 is maintained at a constant value, and the distance H between the ground plane 71 provided on the substrate 31 below the signal line lead 21 and the signal line lead 21 above it.
The signal line leads 21 and the adjacent signal line leads 21 and the ground leads 6 are adjusted in accordance with the amount of decrease toward the destination.
The distance S between the side surface and 1 is gradually increased toward the tip of the signal line lead 21.
Description
【0001】[0001]
【産業上の利用分野】本発明は、高速信号で動作させる
半導体チップ等の高周波素子を収納した半導体装置を基
板に表面実装してなる半導体装置実装体に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting body in which a semiconductor device containing a high-frequency element such as a semiconductor chip operated by a high speed signal is surface-mounted on a substrate.
【0002】[0002]
【従来の技術】従来より、セラミック又は樹脂等からな
るパッケージに高周波素子を気密に封入してなる半導体
装置、又は高周波素子を樹脂内部に気密に封止してなる
半導体装置がある。2. Description of the Related Art Conventionally, there is a semiconductor device in which a high frequency element is hermetically sealed in a package made of ceramic or resin or a semiconductor device in which a high frequency element is hermetically sealed in a resin.
【0003】これらの半導体装置においては、図21に
示したように、半導体装置10周囲の4方又は2方等
に、高速信号を伝える細帯状をした金属製の信号線路用
リード20を複数本延出している。In these semiconductor devices, as shown in FIG. 21, a plurality of strip-shaped metal signal line leads 20 for transmitting high-speed signals are provided on four sides or two sides around the semiconductor device 10. It is extended.
【0004】この半導体装置10を基板30に表面実装
する際には、図21に示したように、その周囲に延出し
た信号線路用リード20をガルウイング状に折曲してい
る。そして、そのガルウイング状に折曲した信号線路用
リード20先端を基板30の信号回路用接続パッド80
に接続している。そして、信号線路用リード20を介し
て、基板30の信号回路(図示せず)と半導体装置10
に収納した高周波素子40との間を高速信号を伝えるよ
うにしている。When the semiconductor device 10 is surface-mounted on the substrate 30, as shown in FIG. 21, the signal line leads 20 extending around the semiconductor device 10 are bent in a gull wing shape. The tip of the signal line lead 20 bent in the gull wing shape is connected to the signal circuit connection pad 80 of the substrate 30.
Connected to. Then, via the signal line leads 20, the signal circuit (not shown) of the substrate 30 and the semiconductor device 10 are connected.
A high-speed signal is transmitted to and from the high-frequency element 40 housed in.
【0005】ここで、信号線路用リード20をガルウイ
ング状に折曲するとは、図21に示したように、半導体
装置10周囲にほぼ水平に延出した信号線路用リード2
0中途部を下方にほぼL字状に折曲すると共に、そのほ
ぼL字状に折曲した信号線路用リード20先端をさらに
水平方向にほぼL字状に折曲することをいう。Bending the signal line lead 20 in a gull wing shape means that the signal line lead 2 extends substantially horizontally around the semiconductor device 10 as shown in FIG.
0 It means that the middle part is bent downward in a substantially L shape, and the tip of the signal line lead 20 bent in a substantially L shape is further bent in a substantially L shape in the horizontal direction.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記半
導体装置10を基板30に表面実装してなる半導体装置
実装体100においては、その半導体装置10周囲のガ
ルウイング状に折曲してその先端を基板の信号回路用接
続パッド80に接続した信号線路用リード20を、単に
半導体装置10周囲の空気中に晒した状態としていて、
その高速信号を伝える信号線路用リード20の特性イン
ピーダンスを、信号線路用リード20内端に連なる半導
体装置10の内部回路、即ちパッケージ50の信号線路
52や半導体装置10に収納した高周波素子40の信号
回路の持つ特性インピーダンスの50Ω等にマッチング
させていなかった。However, in the semiconductor device mounting body 100 in which the semiconductor device 10 is surface-mounted on the substrate 30, the tip of the substrate is bent like a gull wing around the semiconductor device 10. The signal line lead 20 connected to the signal circuit connection pad 80 is simply exposed to the air around the semiconductor device 10.
The characteristic impedance of the signal line lead 20 for transmitting the high-speed signal is the internal circuit of the semiconductor device 10 connected to the inner end of the signal line lead 20, that is, the signal line 52 of the package 50 or the signal of the high frequency element 40 housed in the semiconductor device 10. The characteristic impedance of the circuit, such as 50Ω, was not matched.
【0007】そのため、上記半導体装置実装体100に
おいては、信号線路用リード20を介して、半導体装置
10に収納した高周波素子40と基板の信号回路との間
を高速信号を伝えた場合に、信号線路用リード20を高
速信号が伝わる際の挿入損失、反射損失等が大きくて、
信号線路用リード20を高速信号を伝送損失少なく効率
良く伝えることができなかった。このことは特に、信号
線路用リード20に20GHz以上等の超高速信号を伝
えた場合に顕著であった。Therefore, in the semiconductor device package 100, when a high-speed signal is transmitted between the high-frequency element 40 housed in the semiconductor device 10 and the signal circuit of the substrate via the signal line lead 20, a signal is transmitted. The insertion loss and the reflection loss when a high-speed signal is transmitted through the line lead 20 are large,
High-speed signals could not be efficiently transmitted through the signal line leads 20 with little transmission loss. This was particularly remarkable when an ultrahigh-speed signal of 20 GHz or higher was transmitted to the signal line lead 20.
【0008】本発明は、このような課題に鑑みてなされ
たもので、半導体装置周囲に延出してガルウイング状に
折曲した信号線路用リードであって、その先端を基板の
信号回路用接続パッドに接続した信号線路用リードを、
高速信号を伝送損失少なく効率良く伝えることのできる
半導体装置実装体を提供することを目的としている。The present invention has been made in view of the above problems, and is a signal line lead extending around a semiconductor device and bent in a gull wing shape, the tip of which is a connection pad for a signal circuit on a substrate. The signal line lead connected to
An object of the present invention is to provide a semiconductor device mounting body capable of efficiently transmitting a high-speed signal with little transmission loss.
【0009】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置実装体は、高周波素子を収納し
た半導体装置周囲に延出した高速信号を伝える信号線路
用リードをガルウイング状に折曲し、その信号線路用リ
ード先端を基板の信号回路用接続パッドに接続してなる
半導体装置実装体において、前記信号線路用リード両側
に信号線路用リードの折曲形状に倣ってガルウイング状
に折曲したグランド用リードをそれぞれ並べて備えて、
それらのグランド用リード先端を前記基板のグランド回
路用接続パッドに接続し、前記信号線路用リードをコプ
レナー線路構造とすると共に、そのコプレナー線路構造
とした信号線路用リード下方の前記基板にグランドプレ
ーンを設けて、そのグランドプレーンとその上方の前記
ガルウイング状に折曲した信号線路用リードとの間の距
離Hの信号線路用リード先方に向けての減少量に合わせ
て、前記信号線路用リードの幅W又は隣合う前記信号線
路用リードとグランド用リードとの側面間の距離Sの一
方又はその両方を、信号線路用リード先方に向けて漸次
増減させ、前記ガルウイング状に折曲した信号線路用リ
ードの特性インピーダンスを半導体装置の内部回路の持
つ特性インピーダンスにマッチングさせたことを特徴と
している。In order to achieve the above object, in a semiconductor device mounting body of the present invention, a signal line lead for transmitting a high speed signal extending around a semiconductor device accommodating a high frequency element is formed into a gull wing shape. In a semiconductor device mounting body that is bent and the tip ends of the signal line leads are connected to the signal circuit connection pads of the substrate, a gull wing shape is formed on both sides of the signal line leads following the bent shape of the signal line leads. Equipped with bent ground leads,
The tip of the ground lead is connected to the ground circuit connection pad of the substrate, and the signal line lead has a coplanar line structure, and a ground plane is formed on the substrate below the signal line lead having the coplanar line structure. The width of the signal line lead is provided in accordance with the amount of decrease in the distance H between the ground plane and the gull-wing bent signal line lead above the signal plane lead. One or both of W or the distance S between the side surfaces of the adjacent signal line lead and the ground lead adjacent to each other is gradually increased or decreased toward the tip of the signal line lead, and the signal line lead bent in the gull wing shape. The characteristic impedance is matched with the characteristic impedance of the internal circuit of the semiconductor device.
【0010】ここで、コプレナー線路構造とは、信号線
路両側にグランド線路を、信号線路と同一平面上にそれ
ぞれ並べて備えた線路構造をいう。Here, the coplanar line structure means a line structure in which ground lines are provided on both sides of the signal line and arranged on the same plane as the signal line.
【0011】[0011]
【作用】上記構成の半導体装置実装体においては、半導
体装置周囲のガルウイング状に折曲して、その先端を基
板の信号回路用接続パッドに接続した信号線路用リード
であって、その両側に信号線路用リードの折曲形状に倣
ってガルウイング状に折曲したグランド用リードをそれ
ぞれ並べて備えて、それらのグランド用リード先端を基
板のグランド回路用接続パッドに接続し、コプレナー線
路構造とした信号線路用リードの特性インピーダンス
が、信号線路用リードの幅Wと、信号線路用リードとそ
れに隣合うグランド用リードとの側面間の距離Sと、信
号線路用リードとその下方の基板に設けたグランドプレ
ーンとの間の距離Hと、信号線路用リードとその下方の
グランドプレーンとの間に介在する誘電体の誘電率εと
をパラメータ値とする所定の算定式により決定される。In the semiconductor device package having the above structure, the signal line leads are bent in a gull wing shape around the semiconductor device, and the ends thereof are connected to the signal circuit connection pads of the substrate. A signal line with a coplanar line structure in which gull-wing-shaped ground leads are arranged side by side according to the bent shape of the line leads, and the tips of the ground leads are connected to the ground circuit connection pads on the board. The characteristic impedance of the lead for signal is the width W of the lead for signal line, the distance S between the side faces of the lead for signal line and its adjacent ground lead, and the ground plane provided on the lead for signal line and the substrate therebelow. And the distance H between the signal line lead and the ground plane below the signal line lead as the parameter value. It is determined by a predetermined calculation formula.
【0012】信号線路用リードとその下方のグランドプ
レーンとの間に介在する誘電体は、比誘電率が約1の空
気、又はそれに加えて所定誘電率を持つセラミック又は
樹脂等からなる基板であって、その信号線路用リードと
グランドプレーンとの間に介在する誘電体の誘電率εは
一定値となる。それと共に、半導体装置周囲に延出して
ガルウイング状に折曲し、その先端を基板の信号回路用
接続パッドに接続した信号線路用リードとその下方の基
板に設けたグランドプレーンとの間の距離Hは、信号線
路用リードの長さと信号線路用リードの折曲形状とを一
定とすれば、信号線路用リード先方に行くに従い漸次所
定減少量で減少する値となる。The dielectric material interposed between the signal line lead and the ground plane therebelow is air having a relative permittivity of about 1 or a substrate made of ceramic or resin having a predetermined permittivity in addition to the air. Then, the dielectric constant ε of the dielectric material interposed between the signal line lead and the ground plane has a constant value. At the same time, the distance H between the signal line lead, which extends around the semiconductor device and is bent in a gull wing shape, and whose tip is connected to the signal circuit connection pad of the substrate, and the ground plane provided on the substrate below the H When the length of the signal line lead and the bent shape of the signal line lead are constant, the value becomes a value that gradually decreases by a predetermined reduction amount toward the tip of the signal line lead.
【0013】従って、上記構成の半導体装置実装体にお
いては、基板に設けたグランドプレーンとその上方のガ
ルウイング状に折曲した信号線路用リードとの間の距離
Hの信号線路用リード先方に向けての減少量に合わせ
て、信号線路用リードの幅W又は隣合う信号線路用リー
ドとグランド用リードとの側面間の距離Sの一方又はそ
の両方を、信号線路用リード先方に向けて漸次増減させ
て、半導体装置周囲のガルウイング状に折曲した信号線
路用リードの特性インピーダンスを半導体装置の内部回
路の持つ特性インピーダンスにマッチングさせることが
できる。Therefore, in the semiconductor device package having the above structure, the signal line leads ahead of the distance H between the ground plane provided on the substrate and the signal line leads bent in a gull wing shape thereabove. The width W of the signal line lead or one or both of the distances S between the side surfaces of the adjacent signal line lead and the ground lead are gradually increased or decreased in accordance with the decrease amount of the signal line lead toward the tip of the signal line lead. As a result, the characteristic impedance of the gull-wing-shaped signal line lead around the semiconductor device can be matched with the characteristic impedance of the internal circuit of the semiconductor device.
【0014】具体的には、信号線路用リードの幅Wを一
定値に保持すると共に、基板に設けたグランドプレーン
とその上方の信号線路用リードとの間の距離Hの信号線
路用リード先方に向けての減少量に合わせて、隣合う信
号線路用リードとグランド用リードとの側面間の距離S
を信号線路先方に向けて漸次増大させて、半導体装置周
囲のガルウイング状に折曲した信号線路用リードの特性
インピーダンスを半導体装置の内部回路の持つ特性イン
ピーダンスにマッチングさせることができる。Specifically, the width W of the signal line lead is maintained at a constant value, and the signal line lead tip having a distance H between the ground plane provided on the substrate and the signal line lead above the ground plane is provided. The distance S between the side surfaces of the adjacent signal line lead and the ground lead in accordance with the decrease amount toward
Can be gradually increased toward the signal line destination, and the characteristic impedance of the gull-wing bent signal line lead around the semiconductor device can be matched with the characteristic impedance of the internal circuit of the semiconductor device.
【0015】又は、隣合う信号線路用リードとグランド
用リードとの側面間の距離Sを一定値に保持すると共
に、基板に設けたグランドプレーンとその上方のガルウ
イング状に折曲した信号線路用リードとの間の距離Hの
信号線路用リード先方に向けての減少量に合わせて、信
号線路用リードの幅Wを信号線路先方に向けて漸次減少
させて、半導体装置周囲のガルウイング状に折曲した信
号線路用リードの特性インピーダンスを半導体装置の内
部回路の持つ特性インピーダンスにマッチングさせるこ
とができる。Alternatively, the distance S between the side surfaces of the adjacent signal line lead and the ground lead is maintained at a constant value, and the ground plane provided on the substrate and the signal line lead bent above in a gull wing shape. The width W of the signal line lead is gradually reduced toward the signal line tip in accordance with the amount of decrease in the distance H between the signal line lead tip and the signal line lead, and the width W is bent in a gull wing shape around the semiconductor device. It is possible to match the characteristic impedance of the signal line lead with the characteristic impedance of the internal circuit of the semiconductor device.
【0016】又は、基板に設けたグランドプレーンとそ
の上方のガルウイング状に折曲した信号線路用リードと
の間の距離Hの信号線路用リード先方に向けての減少量
に合わせて、信号線路用リードの幅Wを信号線路用リー
ド先方に向けて漸次減少させると共に、隣合う信号線路
用リードとグランド用リードとの側面間の距離Sを漸次
増大させて、半導体装置周囲のガルウイング状に折曲し
た信号線路用リードの特性インピーダンスを半導体装置
の内部回路の持つ特性インピーダンスにマッチングさせ
ることができる。Alternatively, for the signal line lead, the distance H between the ground plane provided on the substrate and the gall-wing bent signal line lead above the ground plane is reduced in accordance with the reduction amount toward the signal line lead tip. The width W of the lead is gradually decreased toward the tip of the signal line lead, and the distance S between the side faces of the adjacent signal line lead and the ground lead is gradually increased to bend in a gull wing shape around the semiconductor device. It is possible to match the characteristic impedance of the signal line lead with the characteristic impedance of the internal circuit of the semiconductor device.
【0017】[0017]
【実施例】次に、本発明の実施例を図面に従い説明す
る。図1ないし図6はそれぞれ本発明の半導体装置実装
体の好適な実施例を示し、図1ないし図3はそれらの一
部省略平面図、図4ないし図6はそれらの正面断面図を
示している。以下、これらの図中の半導体装置実装体を
説明する。Embodiments of the present invention will now be described with reference to the drawings. 1 to 6 each show a preferred embodiment of a semiconductor device mounting body of the present invention, FIGS. 1 to 3 are partially omitted plan views thereof, and FIGS. 4 to 6 are front sectional views thereof. There is. The semiconductor device mounting body in these figures will be described below.
【0018】図1、図2、図3の半導体装置実装体10
1,102,103は、図7、図8、図9、図10にそ
れぞれ示した半導体装置11,12,13を用いて形成
している。The semiconductor device mounting body 10 shown in FIGS. 1, 2 and 3.
1, 102, 103 are formed by using the semiconductor devices 11, 12, 13 shown in FIGS. 7, 8, 9, and 10, respectively.
【0019】半導体装置11,12,13は、図10に
示したように、高速信号で動作させる半導体チップ等の
高周波素子40を、セラミック又は樹脂(図ではセラミ
ックと金属としている)等で形成したパッケージ50に
気密に封入している。In the semiconductor devices 11, 12 and 13, as shown in FIG. 10, a high frequency element 40 such as a semiconductor chip operated by a high speed signal is formed of ceramic or resin (ceramic and metal are used in the figure) or the like. The package 50 is hermetically sealed.
【0020】パッケージ50周囲には、階段面54を備
えて、その階段面54にパッケージ50内外に連なるメ
タライズからなる信号線路52を備えている。Around the package 50, a staircase surface 54 is provided, and the staircase surface 54 is provided with a signal line 52 made of metallized and continuous inside and outside the package 50.
【0021】信号線路52内端は、ワイヤ42を介し
て、高周波素子40の信号用電極に接続している。The inner end of the signal line 52 is connected to the signal electrode of the high frequency element 40 via the wire 42.
【0022】信号線路52外端には、金属製の信号線路
用リード21,22,23内端を接続して、信号線路用
リード21,22,23をパッケージ50外方に延出し
ている。The inner ends of the signal line leads 21, 22, 23 made of metal are connected to the outer ends of the signal line 52, and the signal line leads 21, 22, 23 are extended to the outside of the package 50.
【0023】信号線路用リード21,22,23両側に
は、図7、図8、図9にそれぞれ示したように、金属製
のグランド用リード61,62,63を、信号線路用リ
ード21,22,23と微小距離あけて、信号線路用リ
ード21,22,23と同一平面上に、信号線路用リー
ド21,22,23とほぼ平行にそれぞれ並べて備えて
いる。そして、信号線路用リード21,22,23を、
コプレナー線路構造としている。As shown in FIGS. 7, 8 and 9, metal ground leads 61, 62, 63 are provided on both sides of the signal line leads 21, 22, 23, respectively, and the signal line leads 21, 22 and 23 are provided on the same plane as the signal line leads 21, 22 and 23 with a slight distance from each other and substantially parallel to the signal line leads 21, 22 and 23. Then, the signal line leads 21, 22, and 23 are
It has a coplanar line structure.
【0024】具体的には、図7、図8、図9にそれぞれ
示したように、パッケージ周囲の階段面54の信号線路
52両側に、パッケージ50内外に連なるメタライズ等
からなるグランド線路56を、信号線路52と微小距離
あけて、信号線路52とほぼ平行にそれぞれ並べて備え
ている。そして、その信号線路52両側のグランド線路
56外端に、金属製のグランド用リード61,62,6
3内端をそれぞれ接続して、グランド用リード61,6
2,63をパッケージ50外方に延出した信号線路用リ
ード21,22,23両側に、信号線路用リード21,
22,23と微小距離あけて、信号線路用リード21,
22,23とほぼ平行にそれぞれ並べて延出している。Specifically, as shown in FIGS. 7, 8 and 9, on both sides of the signal line 52 of the staircase surface 54 around the package, ground lines 56 made up of metallization and the like continuous with the inside and outside of the package 50 are provided. The signal line 52 and the signal line 52 are arranged in parallel with each other with a slight distance therebetween. At the outer ends of the ground line 56 on both sides of the signal line 52, the metal ground leads 61, 62, 6 are provided.
3 inner ends are connected to each other to connect the ground leads 61, 6
2, 63 extending to the outside of the package 50 on both sides of the signal line leads 21, 22 and 23,
22 and 23 are separated from each other by a minute distance, and the signal line leads 21 and
22 and 23 are arranged substantially parallel to each other and extend.
【0025】グランド線路56内端は、ワイヤ(図示せ
ず)を介して、半導体装置11,12,13に収納した
高周波素子40のグランド用電極(図示せず)に接続し
ている。The inner end of the ground line 56 is connected to a ground electrode (not shown) of the high frequency element 40 housed in the semiconductor device 11, 12, 13 via a wire (not shown).
【0026】半導体装置11,12,13周囲に延出し
た信号線路用リード21,22,23とグランド用リー
ド61,62,63とは、図1ないし図6にそれぞれ示
したように、それらを共にほぼ同一形状のガルウイング
状に折曲して、それらの信号線路用リード21,22,
23先端とグランド用リード61,62,63先端とを
基板31,32,33の信号回路用接続パッド80とグ
ランド回路用接続パッド82とにそれぞれ接続してい
る。そして、半導体装置11,12,13を基板31,
32,33に表面実装している。As shown in FIGS. 1 to 6, the signal line leads 21, 22 and 23 and the ground leads 61, 62 and 63 extending around the semiconductor devices 11, 12 and 13 are respectively arranged as shown in FIGS. Both are bent in a gull wing shape having substantially the same shape, and the signal line leads 21, 22,
The tip of 23 and the tips of the ground leads 61, 62, 63 are connected to the signal circuit connection pads 80 and the ground circuit connection pads 82 of the substrates 31, 32, 33, respectively. Then, the semiconductor devices 11, 12, 13 are mounted on the substrate 31,
Surface mounted on 32 and 33.
【0027】半導体装置11,12,13周囲のガルウ
イング状に折曲した信号線路用リード21,22,23
下方の基板31,32,33には、グランドプレーン7
1,72,73を設けている。Signal line leads 21, 22, 23 bent in a gull wing shape around the semiconductor devices 11, 12, 13
The ground plane 7 is formed on the lower substrates 31, 32, and 33.
1, 72, 73 are provided.
【0028】具体的には、図4に示した半導体装置実装
体101,102,103にあっては、半導体装置10
1,102,103周囲のガルウイング状に折曲した信
号線路用リード21,22,23下方の、信号回路用接
続パッド80とグランド回路用接続パッド(図示せず)
部分周辺を除く、基板31表面に、銅箔等からなるグラ
ンドプレーン71を広く設けている。Specifically, in the semiconductor device mounting bodies 101, 102 and 103 shown in FIG. 4, the semiconductor device 10 is used.
Signal circuit connection pads 80 and ground circuit connection pads (not shown) below the signal line leads 21, 22 and 23 bent in the gull wing shape around 1, 102 and 103.
A ground plane 71 made of copper foil or the like is widely provided on the surface of the substrate 31 except for the peripheral portion.
【0029】また、図5に示した半導体装置実装体10
1,102,103にあっては、半導体装置101,1
02,103周囲のガルウイング状に折曲した信号線路
用リード21,22,23下方の基板32内中途部の横
方向に、銅箔等からなるグランドプレーン72を広く設
けている。The semiconductor device mounting body 10 shown in FIG.
1, 102, 103, the semiconductor devices 101, 1
A wide ground plane 72 made of copper foil or the like is provided laterally in the middle of the substrate 32 below the signal line leads 21, 22 and 23 bent in the gull wing shape around 02 and 103.
【0030】また、図6に示した半導体装置実装体10
1,102,103にあっては、半導体装置101,1
02,103周囲のガルウイング状に折曲した信号線路
用リード21,22,23下方の基板33裏面に、銅箔
等からなるグランドプレーン73を広く設けている。Further, the semiconductor device mounting body 10 shown in FIG.
1, 102, 103, the semiconductor devices 101, 1
A ground plane 73 made of copper foil or the like is widely provided on the back surface of the substrate 33 below the signal line leads 21, 22, 23 bent in the gull wing shape around 02, 103.
【0031】それと共に、基板31,32,33に設け
たグランドプレーン71,72,73とその上方のガル
ウイング状に折曲した信号線路用リード21,22,2
3との間の距離Hの信号線路用リード21,22,23
先方に向けての減少量に合わせて、信号線路用リード2
1,22,23の幅W(以下Wという)又は隣合う信号
線路用リード21,22,23とグランド用リード6
1,62,63との側面間の距離S(以下Sという)の
一方又はその両方を、信号線路用リード21,22,2
3先方に向けて漸次増減させている。At the same time, the ground planes 71, 72, 73 provided on the substrates 31, 32, 33 and the signal line leads 21, 22, 2 above which are bent in a gull wing shape.
Signal line leads 21, 22, 23 with a distance H between
Signal line leads 2 according to the amount of decrease toward the other end
Width W of 1, 22, 23 (hereinafter referred to as W) or adjacent signal line leads 21, 22, 23 and ground lead 6
One or both of the distances S (hereinafter referred to as S) between the side surfaces of the signal lines 1, 62, 63 and the signal line leads 21, 22, 2
We are gradually increasing or decreasing toward the three destinations.
【0032】具体的には、図1に示した半導体装置実装
体101の半導体装置11にあっては、図7に示したよ
うに、Wを一定値に保持すると共に、図4、図5、図6
にそれぞれ示したように、半導体装置11を基板31,
32,33に実装した際の、信号線路用リード21先方
に向けてのHの減少量に合わせて、Sを信号線路用リー
ド21先方に向けて漸次増大させている。Specifically, in the semiconductor device 11 of the semiconductor device mounting body 101 shown in FIG. 1, as shown in FIG. 7, W is held at a constant value, and at the same time, as shown in FIGS. Figure 6
As shown in FIG.
S is gradually increased toward the tip of the signal line lead 21 in accordance with the reduction amount of H toward the tip of the signal line lead 21 when mounted on 32 and 33.
【0033】また、図2に示した半導体装置実装体10
2の半導体装置12にあっては、図8に示したように、
Sを一定値に保持すると共に、図4、図5、図6にそれ
ぞれ示したように、半導体装置12を基板31,32,
33に実装した際の、信号線路用リード22先方に向け
てのHの減少量に合わせて、Wを信号線路用リード22
先方に向けて漸次減少させている。Further, the semiconductor device mounting body 10 shown in FIG.
In the semiconductor device 12 of No. 2, as shown in FIG.
While keeping S at a constant value, as shown in FIGS. 4, 5 and 6, the semiconductor device 12 is mounted on the substrates 31, 32,
W is mounted on the signal line lead 22 according to the reduction amount of H toward the destination of the signal line lead 22.
It is gradually decreasing toward the other side.
【0034】また、図3に示した半導体装置実装体10
3の半導体装置13にあっては、図4、図5、図6にそ
れぞれ示したように、半導体装置13を基板31,3
2,33に実装した際の、信号線路用リード23先方に
向けてのHの減少量に合わせて、図9に示したように、
Wを信号線路用リード23先方に向けて漸次減少させて
いると共に、Sを信号線路用リード23先方に向けて漸
次増大させている。Further, the semiconductor device package 10 shown in FIG.
In the semiconductor device 13 of No. 3, as shown in FIG. 4, FIG. 5, and FIG.
As shown in FIG. 9, according to the amount of reduction of H toward the other end of the signal line lead 23 when mounted on the Nos. 2 and 33,
W is gradually reduced toward the lead 23 for the signal line, and S is gradually increased toward the lead 23 for the signal line.
【0035】そして、基板31,32,33に実装した
半導体装置11,12,13周囲のガルウイング状に折
曲した信号線路用リード21,22,23の特性インピ
ーダンスを、半導体装置11,12,13の内部回路の
持つ特性インピーダンスの50Ω等にマッチングさせて
いる。Then, the characteristic impedances of the signal line leads 21, 22 and 23 bent in the gull wing shape around the semiconductor devices 11, 12 and 13 mounted on the substrates 31, 32 and 33 are determined by the semiconductor devices 11, 12, 13 respectively. Is matched to the characteristic impedance of the internal circuit of 50Ω, etc.
【0036】図1ないし図6にそれぞれ示した半導体装
置実装体は、以上のように構成している。The semiconductor device mounting bodies shown in FIGS. 1 to 6 are configured as described above.
【0037】図11ないし図16はそれぞれ本発明の半
導体装置実装体の他の好適な実施例を示し、図11ない
し図13はそれらの平面図、図14ないし図16はそれ
らの正面断面図を示している。以下、これらの図中の半
導体装置実装体を説明する。11 to 16 show other preferred embodiments of the semiconductor device mounting body of the present invention. FIGS. 11 to 13 are plan views thereof, and FIGS. 14 to 16 are front sectional views thereof. Shows. The semiconductor device mounting body in these figures will be described below.
【0038】図11ないし図16にそれぞれ示した半導
体装置実装体104,105,106は、図17ないし
図20にそれぞれ示した半導体装置14,15,16を
用いて形成している。The semiconductor device mounting bodies 104, 105 and 106 shown in FIGS. 11 to 16 are formed by using the semiconductor devices 14, 15 and 16 shown in FIGS. 17 to 20, respectively.
【0039】半導体装置14,15,16は、図20に
示したように、半導体チップ等の高周波素子40を、樹
脂90内部に気密に封止している。In the semiconductor devices 14, 15 and 16, as shown in FIG. 20, a high frequency element 40 such as a semiconductor chip is hermetically sealed inside a resin 90.
【0040】樹脂90周囲の4方又は2方(図では2方
としている)等には、金属製の信号線路用リード24,
25,26内端を一体に埋め込んでいる。そして、樹脂
90周囲に信号線路用リード24,25,26を複数本
並べて延出している。On the four sides or two sides of the resin 90 (two sides in the figure) and the like, metal signal line leads 24,
The inner ends of 25 and 26 are embedded together. A plurality of signal line leads 24, 25, 26 are arranged side by side around the resin 90 and extended.
【0041】樹脂90に埋め込んだ信号線路用リード2
4,25,26内端は、図20に示したように、樹脂9
0内部の高周波素子40の信号用電極に、ギャングボン
ディング法により、直接にはんだ付け接続している。Signal line lead 2 embedded in resin 90
As shown in FIG. 20, the inner ends of 4, 25 and 26 are made of resin 9
The signal electrodes of the high-frequency element 40 inside 0 are directly soldered and connected by a gang bonding method.
【0042】信号線路用リード24,25,26両側に
は、図17、図18、図19にそれぞれ示したように、
金属製のグランド用リード64,65,66を、信号線
路用リード24,25,26と微小距離あけて信号線路
用リード24,25,26と同一平面上に信号線路用リ
ード24,25,26とほぼ平行にそれぞれ並べて備え
ている。そして、信号線路用リード24,25,26を
コプレナー線路構造としている。On both sides of the signal line leads 24, 25, 26, as shown in FIGS. 17, 18 and 19, respectively,
The metal ground leads 64, 65, 66 are separated from the signal line leads 24, 25, 26 by a minute distance and are provided on the same plane as the signal line leads 24, 25, 26 on the same plane. And are installed in parallel with each other. The signal line leads 24, 25, 26 have a coplanar line structure.
【0043】具体的には、信号線路用リード24,2
5,26内端を埋め込んだ樹脂90両側に、グランド用
リード64,65,66内端をそれぞれ一体に埋め込ん
でいる。それと共に、グランド用リード64,65,6
6内端を樹脂90内部の高周波素子40のグランド用電
極(図示せず)に、ギャングボンディング法により、直
接にはんだ付け接続している。Specifically, the signal line leads 24, 2
The inner ends of the ground leads 64, 65, 66 are integrally embedded on both sides of the resin 90 in which the inner ends of 5, 5, 26 are embedded. Along with that, the ground leads 64, 65, 6
The inner end of 6 is directly soldered and connected to the ground electrode (not shown) of the high frequency element 40 inside the resin 90 by the gang bonding method.
【0044】半導体装置14,15,16周囲に延出し
た信号線路用リード24,25,26とグランド用リー
ド64,65,66とは、図11ないし図16にそれぞ
れ示したように、それらを共にほぼ同一形状のガルウイ
ング状に折曲して、それらの信号線路用リード24,2
5,26先端とグランド用リード64,65,66先端
とを基板34,35,36の信号回路用接続パッド80
とグランド回路用接続パッド82とにそれぞれ接続して
いる。そして、半導体装置14,15,16を基板3
4,35,36に表面実装している。The signal line leads 24, 25 and 26 extending around the semiconductor devices 14, 15 and 16 and the ground leads 64, 65 and 66 are respectively provided as shown in FIGS. 11 to 16. Both are bent in a gull wing shape having substantially the same shape, and the signal line leads 24 and 2 are formed.
5, 26 and the tips of the ground leads 64, 65, 66 are connected to the signal circuit connection pads 80 of the substrates 34, 35, 36.
And the ground circuit connection pad 82, respectively. Then, the semiconductor devices 14, 15, 16 are mounted on the substrate 3
Surface mounted on 4, 35, 36.
【0045】樹脂90周囲のガルウイング状に折曲した
信号線路用リード24,25,26下方の基板34,3
5,36には、グランドプレーン74,75,76を広
く設けている。Substrates 34, 3 below the signal line leads 24, 25, 26 bent in a gull wing shape around the resin 90
Wide ground planes 74, 75, and 76 are provided in the reference numerals 5 and 36.
【0046】具体的には、図14に示した半導体装置実
装体104,105,106にあっては、ガルウイング
状に折曲した信号線路用リード24,25,26下方
の、信号回路用接続パッド80とグランド回路用接続パ
ッド(図示せず)部分周辺を除く、基板34表面にグラ
ンドプレーン74を広く設けている。Specifically, in the semiconductor device mounting bodies 104, 105, 106 shown in FIG. 14, signal circuit connection pads under the signal line leads 24, 25, 26 bent in a gull wing shape. The ground plane 74 is widely provided on the surface of the substrate 34 except for the periphery of 80 and the connection pad (not shown) for the ground circuit.
【0047】また、図15に示した半導体装置実装体1
04,105,106にあっては、ガルウイング状に折
曲した信号線路用リード24,25,26下方の基板3
5内中途部の横方向に、銅箔等からなるグランドプレー
ン75を広く設けている。Further, the semiconductor device mounting body 1 shown in FIG.
In 04, 105 and 106, the board 3 below the signal line leads 24, 25 and 26 bent in a gull wing shape
A ground plane 75 made of a copper foil or the like is widely provided in the lateral direction of the middle portion of the interior of the vehicle.
【0048】また、図16に示した半導体装置実装体1
04,105,106にあっては、ガルウイング状に折
曲した信号線路用リード24,25,26下方の基板3
6裏面に、銅箔等からなるグランドプレーン76を広く
設けている。Further, the semiconductor device mounting body 1 shown in FIG.
In 04, 105 and 106, the board 3 below the signal line leads 24, 25 and 26 bent in a gull wing shape
A ground plane 76 made of copper foil or the like is widely provided on the back surface of the No. 6.
【0049】それと共に、基板34,35,36に設け
たグランドプレーン74,75,76とその上方のガル
ウイング状に折曲した信号線路用リード24,25,2
6との間の距離Hの信号線路用リード24,25,26
先方に向けての減少量に合わせて、信号線路用リード2
4,25,26の幅W(以下Wという)又は隣合う信号
線路用リード24,25,26とグランド用リード6
4,65,66との側面間の距離S(以下Sという)の
一方又はその両方を、信号線路用リード24,25,2
6先方に向けて漸次増減させている。At the same time, the ground planes 74, 75 and 76 provided on the substrates 34, 35 and 36 and the signal line leads 24, 25 and 2 above which are bent in a gull wing shape.
Signal line leads 24, 25, 26 at a distance H from
Signal line leads 2 according to the amount of decrease toward the other end
Width W of 4, 25, 26 (hereinafter referred to as W) or adjacent signal line leads 24, 25, 26 and ground lead 6
One or both of the distances S (hereinafter referred to as S) between the side surfaces of the signal lines 4, 65, 66 and the signal line leads 24, 25, 2
We are gradually increasing or decreasing toward the six destinations.
【0050】具体的には、図11に示した半導体装置実
装体104の半導体装置14にあっては、図17に示し
たように、Wを一定値に保持すると共に、図14、図1
5、図16にそれぞれ示したように、半導体装置14を
基板34,35,36に実装した際の、信号線路用リー
ド24先方に向けてのHの減少量に合わせて、Sを信号
線路用リード24先方に向けて漸次増大させている。Specifically, in the semiconductor device 14 of the semiconductor device mounting body 104 shown in FIG. 11, as shown in FIG. 17, W is held at a constant value, and at the same time, as shown in FIGS.
As shown in FIGS. 5 and 16, respectively, when the semiconductor device 14 is mounted on the substrates 34, 35, and 36, S is set for the signal line in accordance with the reduction amount of H toward the signal line lead 24 tip. The lead 24 is gradually increased toward the other end.
【0051】また、図12に示した半導体装置実装体1
05の半導体装置15にあっては、図18に示したよう
に、Sを一定値に保持すると共に、図14、図15、図
16にそれぞれ示したように、半導体装置15を基板3
4,35,36に実装した際の、信号線路用リード25
先方に向けてのHの減少量に合わせて、Wを信号線路用
リード25先方に向けて漸次減少させている。The semiconductor device mounting body 1 shown in FIG.
In the semiconductor device 15 of No. 05, S is held at a constant value as shown in FIG. 18, and the semiconductor device 15 is mounted on the substrate 3 as shown in FIGS.
Signal line lead 25 when mounted on 4, 35, 36
In accordance with the decrease amount of H toward the other end, W is gradually decreased toward the front end of the signal line lead 25.
【0052】また、図13に示した半導体装置実装体1
06の半導体装置16にあっては、図14、図15、図
16にそれぞれ示したように、半導体装置16を基板3
4,35,36に実装した際の、信号線路用リード26
先方に向けてのHの減少量に合わせて、図19に示した
ように、Wを信号線路用リード26先方に向けて漸次減
少させていると共に、Sを信号線路用リード26先方に
向けて漸次増大させている。Further, the semiconductor device mounting body 1 shown in FIG.
In the semiconductor device 16 of No. 06, the semiconductor device 16 is mounted on the substrate 3 as shown in FIGS.
Signal line lead 26 when mounted on 4, 35, 36
In accordance with the decrease amount of H toward the other end, as shown in FIG. 19, W is gradually decreased toward the lead 26 for the signal line and S toward the other end of the lead 26 for the signal line. It is gradually increasing.
【0053】そして、基板34,35,36に実装した
半導体装置14,15,16周囲のガルウイング状に折
曲した信号線路用リード24,25,26の特性インピ
ーダンスを、半導体装置14,15,16の内部回路の
持つ特性インピーダンスの50Ω等にそれぞれマッチン
グさせている。The characteristic impedances of the signal line leads 24, 25 and 26 bent in the gull wing shape around the semiconductor devices 14, 15 and 16 mounted on the substrates 34, 35 and 36 are measured by the semiconductor devices 14, 15, 16 respectively. The characteristic impedance of the internal circuit of 50 Ω is matched with each other.
【0054】図11ないし図16にそれぞれ示した半導
体装置実装体104,105,106は、以上のように
構成している。The semiconductor device mounting bodies 104, 105 and 106 respectively shown in FIGS. 11 to 16 are configured as described above.
【0055】なお、上述半導体装置実装体101,10
2,103,104,105,106の半導体装置1
1,12,13,14,15,16では、グランド用リ
ード61,62,63,64,65,66内端を、直接
に又はパッケージのグランド線路56を介して、高周波
素子40のグランド用電極に接続しているが、本発明
は、グランド用リード61,62,63,64,65,
66内端を接続するためのグランド用電極を持たない高
周波素子40を収納した半導体装置を用いた半導体装置
実装体、又はグランド用リード61,62,63,6
4,65,66内端を、高周波素子40のグランド用電
極に接続せずに、単にパッケージのグランド線路56外
端に接続したり又は樹脂90に一体に埋め込んだりした
半導体装置を用いた半導体装置実装体にも利用可能であ
り、そのような半導体装置実装体に利用しても、上述半
導体装置実装体101,102,103,104,10
5,106とほぼ同様な作用を持つ半導体装置実装体を
形成できる。The semiconductor device mounting bodies 101 and 10 described above are used.
2, 103, 104, 105, 106 semiconductor devices 1
In 1, 12, 13, 14, 15, and 16, the inner electrodes of the ground leads 61, 62, 63, 64, 65, and 66 are connected to the ground electrode of the high-frequency element 40 directly or through the ground line 56 of the package. In the present invention, the ground leads 61, 62, 63, 64, 65,
66 A semiconductor device mounting body using a semiconductor device containing a high frequency element 40 having no ground electrode for connecting the inner end, or ground leads 61, 62, 63, 6
A semiconductor device using a semiconductor device in which the inner ends of 4, 65, 66 are not connected to the ground electrode of the high-frequency element 40, but are simply connected to the outer end of the ground line 56 of the package or are integrally embedded in the resin 90. It is also applicable to a mounted body, and even if it is used for such a semiconductor device mounted body, the semiconductor device mounted bodies 101, 102, 103, 104, 10 described above are used.
It is possible to form a semiconductor device mounting body having substantially the same operation as 5, 106.
【0056】[0056]
【発明の効果】以上説明したように、本発明の半導体装
置実装体によれば、半導体装置周囲のガルウイング状に
折曲してその先端を基板の信号回路用接続パッドに接続
した信号線路用リードの特性インピーダンスを、基板に
設けたグランドプレーンを用いて、そのほぼ全長に亙っ
て半導体装置の内部回路の持つ特性インピーダンスの5
0Ω等にマッチングさせることができる。As described above, according to the semiconductor device package of the present invention, the signal line lead is bent in a gull wing shape around the semiconductor device and its tip is connected to the signal circuit connection pad of the substrate. Of the characteristic impedance of the internal circuit of the semiconductor device over the entire length of the characteristic impedance of
It can be matched to 0Ω or the like.
【0057】そして、そのガルウイング状に折曲した信
号線路用リードを介して、基板に実装した半導体装置に
収納した高周波素子と基板の信号回路との間を20GH
z以上の超高速信号等の高速信号を伝送損失少なく効率
良く伝えることが可能となる。20 GHz is provided between the high-frequency element housed in the semiconductor device mounted on the substrate and the signal circuit on the substrate through the signal line lead bent in the gull wing shape.
It is possible to efficiently transmit a high speed signal such as an ultra high speed signal of z or more with little transmission loss.
【図1】本発明の半導体装置実装体の一部省略平面図で
ある。FIG. 1 is a partially omitted plan view of a semiconductor device mounting body of the present invention.
【図2】本発明の半導体装置実装体の一部省略平面図で
ある。FIG. 2 is a partially omitted plan view of a semiconductor device mounting body of the present invention.
【図3】本発明の半導体装置実装体の一部省略平面図で
ある。FIG. 3 is a partially omitted plan view of a semiconductor device mounting body of the present invention.
【図4】本発明の半導体装置実装体の正面断面図であ
る。FIG. 4 is a front sectional view of a semiconductor device mounting body of the present invention.
【図5】本発明の半導体装置実装体の正面断面図であ
る。FIG. 5 is a front sectional view of a semiconductor device mounting body of the present invention.
【図6】本発明の半導体装置実装体の正面断面図であ
る。FIG. 6 is a front sectional view of a semiconductor device mounting body of the present invention.
【図7】本発明の半導体装置実装体に用いる半導体装置
の一部省略平面図である。FIG. 7 is a partially omitted plan view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図8】本発明の半導体装置実装体に用いる半導体装置
の一部省略平面図である。FIG. 8 is a partially omitted plan view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図9】本発明の半導体装置実装体に用いる半導体装置
の一部省略平面図である。FIG. 9 is a partially omitted plan view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図10】本発明の半導体装置実装体に用いる半導体装
置の一部省略正面断面図である。FIG. 10 is a partially omitted front sectional view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図11】本発明の半導体装置実装体の平面図である。FIG. 11 is a plan view of a semiconductor device mounting body of the present invention.
【図12】本発明の半導体装置実装体の平面図である。FIG. 12 is a plan view of a semiconductor device mounting body of the present invention.
【図13】本発明の半導体装置実装体の平面図である。FIG. 13 is a plan view of a semiconductor device mounting body of the present invention.
【図14】本発明の半導体装置実装体の正面断面図であ
る。FIG. 14 is a front sectional view of a semiconductor device mounting body of the present invention.
【図15】本発明の半導体装置実装体の正面断面図であ
る。FIG. 15 is a front sectional view of a semiconductor device mounting body of the present invention.
【図16】本発明の半導体装置実装体の正面断面図であ
る。FIG. 16 is a front sectional view of a semiconductor device mounting body of the present invention.
【図17】本発明の半導体装置実装体に用いる半導体装
置の平面図である。FIG. 17 is a plan view of a semiconductor device used for the semiconductor device mounting body of the present invention.
【図18】本発明の半導体装置実装体に用いる半導体装
置の平面図である。FIG. 18 is a plan view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図19】本発明の半導体装置実装体に用いる半導体装
置の平面図である。FIG. 19 is a plan view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図20】本発明の半導体装置実装体に用いる半導体装
置の正面断面図である。FIG. 20 is a front sectional view of a semiconductor device used for a semiconductor device mounting body of the present invention.
【図21】従来の半導体装置実装体の正面断面図であ
る。FIG. 21 is a front sectional view of a conventional semiconductor device package.
10、11、12、13、14、15、16 半導体装
置 20、21、22、23 信号線路用リード 24、25、26 信号線路用リード 30、31、32、33、34、35、36 基板 40 高周波素子 50 パッケージ 52 信号線路 56 グランド線路 61、62、63 グランド用リード 64、65、66 グランド用リード 71、72、73 グランドプレーン 74、75、76 グランドプレーン 80 信号回路用接続パッド 82 グランド回路用接続パッド 90 樹脂 100、101、102、103 半導体装置実装体 104、105、106 半導体装置実装体10, 11, 12, 13, 14, 15, 16 Semiconductor device 20, 21, 22, 23 Signal line lead 24, 25, 26 Signal line lead 30, 31, 32, 33, 34, 35, 36 Substrate 40 High-frequency element 50 Package 52 Signal line 56 Ground line 61, 62, 63 Ground lead 64, 65, 66 Ground lead 71, 72, 73 Ground plane 74, 75, 76 Ground plane 80 Signal circuit connection pad 82 For ground circuit Connection pad 90 Resin 100, 101, 102, 103 Semiconductor device mounting body 104, 105, 106 Semiconductor device mounting body
Claims (1)
延出した高速信号を伝える信号線路用リードをガルウイ
ング状に折曲し、その信号線路用リード先端を基板の信
号回路用接続パッドに接続してなる半導体装置実装体に
おいて、前記信号線路用リード両側に信号線路用リード
の折曲形状に倣ってガルウイング状に折曲したグランド
用リードをそれぞれ並べて備えて、それらのグランド用
リード先端を前記基板のグランド回路用接続パッドに接
続し、前記信号線路用リードをコプレナー線路構造とす
ると共に、そのコプレナー線路構造とした信号線路用リ
ード下方の前記基板にグランドプレーンを設けて、その
グランドプレーンとその上方の前記ガルウイング状に折
曲した信号線路用リードとの間の距離Hの信号線路用リ
ード先方に向けての減少量に合わせて、前記信号線路用
リードの幅W又は隣合う前記信号線路用リードとグラン
ド用リードとの側面間の距離Sの一方又はその両方を、
信号線路用リード先方に向けて漸次増減させ、前記ガル
ウイング状に折曲した信号線路用リードの特性インピー
ダンスを半導体装置の内部回路の持つ特性インピーダン
スにマッチングさせたことを特徴とする半導体装置実装
体。1. A lead for a signal line extending around a semiconductor device containing a high frequency element for transmitting a high-speed signal is bent in a gull wing shape, and the tip of the lead for the signal line is connected to a connection pad for a signal circuit of a substrate. In the semiconductor device mounting body comprising the above, the ground leads bent in a gull wing shape are arranged side by side on both sides of the signal line leads, and the tips of the ground leads are provided on the substrate. Connected to the connection pad for the ground circuit, and the signal line lead has a coplanar line structure, and a ground plane is provided on the substrate below the signal line lead having the coplanar line structure. Of the signal line lead of the distance H between the signal line lead bent in the gull wing shape. In accordance with the amount of decrease, one or both of the width W of the signal line lead and the distance S between the adjacent side faces of the signal line lead and the ground lead,
A semiconductor device package, wherein the characteristic impedance of the signal line lead bent in the gull wing shape is gradually increased or decreased toward the tip of the signal line lead to match the characteristic impedance of the internal circuit of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3359856A JP3034672B2 (en) | 1991-12-27 | 1991-12-27 | Semiconductor device package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3359856A JP3034672B2 (en) | 1991-12-27 | 1991-12-27 | Semiconductor device package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05183095A true JPH05183095A (en) | 1993-07-23 |
| JP3034672B2 JP3034672B2 (en) | 2000-04-17 |
Family
ID=18466654
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3359856A Expired - Fee Related JP3034672B2 (en) | 1991-12-27 | 1991-12-27 | Semiconductor device package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3034672B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100242362B1 (en) * | 1995-01-18 | 2000-02-01 | 가네꼬 히사시 | Lead frame for a resin sealed semiconductor device and a manufacturing method for a resin sealed semiconductor device |
| JP2011134941A (en) * | 2009-12-25 | 2011-07-07 | Fujitsu Semiconductor Ltd | Semiconductor device and mounting structure |
| WO2022004644A1 (en) * | 2020-06-29 | 2022-01-06 | 京セラ株式会社 | Wiring substrate and electronic device |
-
1991
- 1991-12-27 JP JP3359856A patent/JP3034672B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100242362B1 (en) * | 1995-01-18 | 2000-02-01 | 가네꼬 히사시 | Lead frame for a resin sealed semiconductor device and a manufacturing method for a resin sealed semiconductor device |
| JP2011134941A (en) * | 2009-12-25 | 2011-07-07 | Fujitsu Semiconductor Ltd | Semiconductor device and mounting structure |
| US8811028B2 (en) | 2009-12-25 | 2014-08-19 | Fujitsu Semiconductor Limited | Semiconductor device and circuit board |
| WO2022004644A1 (en) * | 2020-06-29 | 2022-01-06 | 京セラ株式会社 | Wiring substrate and electronic device |
| JPWO2022004644A1 (en) * | 2020-06-29 | 2022-01-06 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3034672B2 (en) | 2000-04-17 |
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| LAPS | Cancellation because of no payment of annual fees |