JPH0520898A - Ram testing circuit for semiconductor integrated circuit assembled with ram - Google Patents

Abstract

PURPOSE:To test a plurality of RAMs similarly to the case of one RAM and to individually test the RAMs. CONSTITUTION:RAMs (1-n) 31-34 are formed of SRAM, and a common test signal is distributed from external input terminals 1-10 to input address, input data of the RAMs through a selector 11 of signals to be normally used. Write pulses are distributed from the input terminals through a selector 11 of the signals to be normally used. The selectors 11 are decided to be selected according to an external terminal test mode. The outputs of the RAMs are input to coincidence/discordance detectors (1-nd) 12-14 at the same BIT. The detectors 12-14 output '0' if all the input signals are the same value, and 'l' to external output terminals 15-17 if any one signal is different.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RAM test circuit for a semiconductor integrated circuit incorporating a RAM, and more particularly to a plurality of Rs of the same type.
The present invention relates to a RAM test circuit of a semiconductor integrated circuit incorporating a RAM, in which an AM is incorporated.

[0002]

RA incorporated in a conventional semiconductor integrated circuit
As the test circuit of M, the ROM in which the pattern is written
There are a built-in type, a type in which all the input and output of RAM are connected to external terminals, and the like.

When testing a RAM incorporated in a semiconductor integrated circuit, since it is incorporated in the semiconductor integrated circuit,
Various restrictions are born. One of the restrictions is the number of external terminals that can be used only for testing. Also, test time is a big issue. Attempting to connect all the RAM inputs and outputs to external terminals often violates the limit of the number of external terminals that can be used only for testing. This is all the more so when a plurality of RAMs are incorporated. Therefore, in order to reduce the number of external terminals used exclusively for the test and to simplify the test, a test circuit is created in the semiconductor integrated circuit. The smaller the number, the better.

[0004]

The conventional RAM described above.
In the RAM test circuit of the built-in semiconductor integrated circuit, the hardware amount of the test circuit becomes considerably large, and the reliability of the ROM itself becomes a problem. Further, there is a drawback that some items such as access time cannot be measured.

[0005]

According to a first aspect of the present invention, there is provided a RAM test circuit for a semiconductor integrated circuit in which a RAM is incorporated, which is a RAM test circuit for a semiconductor integrated circuit in which a RAM is incorporated. , The test address and the test data are distributed to each RAM in common, the test write pulse is separately provided to each RAM, and the output of the RAM is “1” if all the input signals have the same value. A RAM test circuit for a semiconductor integrated circuit with a built-in RAM, characterized in that if any value is different, it is input to a circuit that outputs "0".

A RAM test circuit of a semiconductor integrated circuit incorporating a RAM according to the second invention is (number of input / output pins of one RAM) + (number of RAM) external terminals dedicated for testing / combined with (one (The number of RAM input signals) x (number of RAM) selectors for test signals and normal signals (the number of output signals of one RAM) The same BIT output of each RAM And a match / mismatch detection circuit for detecting

[0007]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. R of the semiconductor integrated circuit incorporating the RAM shown in FIG.
In the AM test circuit, the RAMs (1 to n) 31 to 34 are SR
The AM is provided with a test signal common to each RAM from the external input terminals 1 to 10 for its input address and input data through a selector 11 for a signal normally used. Further, each write pulse is distributed from an external input terminal via a selector 11 for a signal used in a normal state. Which of these selectors 11 is selected is determined by the external terminal test mode. The outputs of the RAMs are input to the coincidence / non-coincidence detection circuits (1 to nd) 12 to 14 in the same BIT. The coincidence / non-coincidence detection circuits 12 to 14 output "0" to the external output terminals 15 to 17 if all the input signals have the same value and "1" if all the input signals have different values.

When testing the RAM, first, the value of the external terminal test mode is set so that the selector 11 selects the test signal. Then, the external input terminal test address (0 to na) and the test data (0 to n)
d), RAM for test write pulse (1 to n)
(1 to n) 31 to 34 are operated. At this time, the same value is input to the test write pulse (1 to n). Since the same value is input to all RAMs, the output of each RAM has the same value at the same BIT, so the test output (0 to n
d) is a match / mismatch detection circuit 1 unless there is an error in the RAM
2 to 14, all become "0", and when there is an error, "1" is output.

By doing so, all the RAMs can be tested simultaneously at the same time as the test of one RAM. Also, when you want to test only one RAM or when you want to measure the access time, use the other RAM beforehand.
By writing l "0" and using only the test write pulse connected to the RAM to be tested, the output of the other RAM is all "0", so that the test outputs 0 to nd Is the RAM output itself that you want to test, so you can easily test only one RAM and measure the access time.

FIG. 2 is a circuit diagram showing details of the match / mismatch detection circuit shown in FIG.

[0012]

According to the RAM test circuit of the semiconductor integrated circuit incorporating the RAM of the present invention, the coincidence / non-coincidence detection circuit is provided for each data B.
By providing each IT, a plurality of RAMs can be used as one R
It can be tested in the same way as AM, and can also be tested individually, and the number of external terminals used is the same as the number of external terminals used for testing + (the number of input pins of one RAM) + (the number of RAM).
-1, the number of external terminals dedicated for testing is (the number of output pins of one RAM) + 1, and the amount of hardware used is also
(Number of input signals of one RAM) × (number of RAM) 1/2 selector of test signals and signals under normal conditions, and the same BIT of each RAM (number of output signals of one RAM)
There is an effect that a match / mismatch detection circuit between outputs can be used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a match / mismatch detection circuit shown in FIG.

[Explanation of symbols]

1-10 External input terminal 11 selector 12 to 14 coincidence disagreement detection circuit 15-17 External output terminal 23 inputs 24 outputs

Claims (2)

[Claims] 1. In a RAM test circuit of a semiconductor integrated circuit having a built-in RAM in which a plurality of RAMs of the same type are built in, a test address and a test data are provided for each RA.
A circuit that distributes to M in common, has a write pulse for each RAM separately, and outputs "1" if the input signals are all the same value for each BIT, and outputs "0" if one value is different. A RAM test circuit for a semiconductor integrated circuit with a built-in RAM, which is characterized in that: 2. (Number of input / output pins of one RAM) + (RA
M number of test dedicated / combined external terminals, (number of input signals of one RAM) × (number of RAM) selectors of test signals and normal signals (output of one RAM) A RAM test circuit for a semiconductor integrated circuit with a built-in RAM, comprising: a match / mismatch detection circuit for detecting a match / mismatch between the outputs of the same BIT of each RAM.