JPH05210978A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] [Purpose] All the inactive word lines are grounded during operation. A word line selection signal output circuit 5 outputs a word line selection signal based on a column address signal to activate, for example, a word line selection circuit 22, and the word line selection circuit 2
The word lines 33 to 36 connected to 2 are brought into a floating state. The word line booster circuit 21 outputs the output signal WBST1.
~ WBST4 is activated to activate, for example, the word line 36 among the word lines 33 to 36 in the floating state. The ground word line selection circuit 61 receives the drive signal from the word line boosting circuit 21 and receives the word line ground signal WD.
IS1-WDIS4 are output and the remaining floating word lines 33-35 are grounded. In this way, the non-activated word lines 33 to 35 connected to the activated word line selection circuit 22 are grounded to make them less susceptible to the noise from the activated word line 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory).

[0002]

2. Description of the Related Art Conventionally, FIG. 2 shows a conventional semiconductor memory device.
There is something like. This semiconductor memory device operates as follows. At the time of data reading, the row address selection circuit 10 receives the row address signal from the row address input circuit 4 and selects the bit line 12 designated by the row address under the control of the sense operation timing generation circuit 3. ..

On the other hand, the column address input circuit 2 generates a column address signal based on the column address input from the outside and the signal PR from the timing generation circuit 1 and sends it to the column address selection circuit 7. Then, the column address selection circuit 7 activates the word line 8 designated by the column address. The word line ground circuit 9 receives the signal WDIS output from the timing generation circuit 1,
When all the word lines are inactive, the other end side 8'of the word lines is grounded.

Then, the transistor of the memory cell connected to the selected bit line 12 and the activated word line 8 in the memory section 6 is turned on, and the data written in the capacitor is changed to the above. The data is read out to the selected bit line 12. Then, the read data is amplified by the sense amplifier circuit 11 and output through the data output buffer 14.

At the time of writing data, data is sent to the bit line 12 selected by the row address selection circuit 10 as described above via the data input buffer 13. On the other hand, the column address selection circuit 7 activates the word line 8 as described above. Then, the selected bit line 12 in the storage unit 6 is selected.
The transistor of the memory cell connected to the activated word line 8 is turned on, and the data sent to the selected bit line 12 is written in the capacitor.

FIG. 3 is a detailed circuit diagram of column address selection circuit 7 and word line ground circuit 9 shown in FIG. The column address selection circuit 7 is composed of a word line selection signal output circuit 5, a word line boosting circuit 21, and a plurality of word line selection circuits 22 ,. The word line selection signal output circuit 5 outputs the word line selection signal based on the column address signal from the column address input circuit 2 (see FIG. 2) as described above, and the plurality of word line selection circuits 22 ,. , 23
Activate one of them. Further, the input column address signal is sent to the word line boosting circuit 21.
Then, the word line boosting circuit 21 receives the column address signal from the word line selection signal output circuit 5,
Output signal WBST1, WBST2, WBST3, WBST
Activate one of the four. Thus, of the four word lines connected to the word line selection circuit selected by the word line selection signal output circuit 5, only one selected by the output signal from the word line boosting circuit 21 is activated. Of.

For example, the word line selection signal output circuit 5
Consider that the word line selection circuit 22 is activated by the word line selection circuit 22 and the output signal WBST1 is activated by the word line boosting circuit 21. In that case, the word line selection signal of level "L" is output to the word line selection signal line 24, and the transistors 25, ..., 28 are turned off.
On the other hand, the transistors 29, ..., 32 are turned on,
The word lines 33, ..., 36 are in a floating state. In this state, the output signal WBST1 becomes the level "H",
The word line 36 connected to the transistor 32 is activated.

In this case, the word line selection signal of level "H" is output to the word line selection signal line 37 of the other word line selection circuit 23. Therefore, the transistor 4
2, ..., 45 are "off" while the transistor 38,
, 41 are turned on, and the word lines 46, ..., 49 are grounded.

Thus, all the word lines (word lines 46, ..., 49 in the above case) connected to the word line selection circuit (in the above case, the word line selection circuit 23) which is not activated are grounded. However, among the word lines connected to the activated word line selection circuit (word line selection circuit 22 in the above case), the word line not activated (word line 33 in the above case). , ..., 35) are in a floating state.

The timing generation circuit 1 sets the level of the signal WDIS to "L" when one of the word lines is activated as described above, and sets the transistor 50,
… Turn 57 off. On the other hand, when all the word lines are inactive, the level of the signal WDIS is set to "H", the transistors 50, ..., 57 are set to "ON", and all the word lines 33 ,. , 46, ..., 49 are grounded.

[0011]

However, in the conventional semiconductor memory device described above, when any one of the word lines is activated, as described above, the activated word in which the word line in the floating state is adjacent is activated word. There is a problem that it receives noise from the line and malfunctions. Therefore, in order to avoid such a problem, in the word line booster circuit 21 shown in FIG. 3, the line of the output signal in the inactive state (in the above case, the output signals WBST2, ..., WBST4) is grounded. Has been taken.

However, in such a method, the grounding position is far from the word line itself, so that the grounding effect cannot be sufficiently obtained. Therefore, there is a problem that the noise given from the activated word line to the deactivated word line causes a malfunction etc. due to the increase of the chip size and the speeding up of the operation accompanying the increase in the capacity of the semiconductor memory device in recent years. is there.

Therefore, an object of the present invention is to provide a semiconductor memory device in which an inactive word line connected to an activated word line selection circuit is also grounded to reduce the influence of noise from an adjacent word line. Especially.

[0014]

In order to achieve the above object, a semiconductor memory device of the present invention specifies a storage unit and an address of the storage unit based on an address signal from the outside, and assigns the address to the specified address. A word line selection signal output circuit that outputs a word line selection signal for selecting a word line group including a corresponding word line, and a word line that sets the word line group selected based on the word line selection signal into a floating state Based on the address signal from the selection circuit and the word line selection signal output circuit, the voltage of the word line corresponding to the specified address in each of the word line groups in the floating state is boosted to change the word line The word line booster circuit to be activated and the word line select signal output circuit driven by the drive signal from the word line booster circuit. It is characterized by including a ground word line selection circuit for selectively grounding the deactivated word line which is not activated by the word line boosting circuit of the selected word line group Te.

[0015]

When an address signal is input from the outside, a word line selection signal for selecting a word line group including a word line corresponding to an address of a specified storage unit is word-selected based on the input address signal. It is output by the line selection signal output circuit. Then, based on the word line selection signal from the word line selection signal output circuit, the selected word line group is brought into a floating state by the word line selection circuit. Then, based on the address signal from the word line selection signal output circuit, the voltage of the word line corresponding to the specified address in each of the floating word line groups is boosted by the word line boosting circuit. The word line is activated.

On the other hand, the ground word line selection circuit is driven by the drive signal from the word line booster circuit and is activated by the word line booster circuit in the word line group selected by the word line select signal output circuit. Non-activated word lines that are not activated are selectively grounded. Thus
Of the word line group selected by the word line selection signal output circuit, all the word lines that have not been activated by the word line boosting circuit are grounded, and the deactivated word lines are noisy from the activated word lines. Are prevented from being affected by.

[0017]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a circuit diagram of the semiconductor memory device in this embodiment. In this embodiment, a ground word line selection circuit 61 is newly added to the conventional semiconductor memory device shown in FIG.

The ground word line selection circuit 61 has word line ground signals WDIS1, WDIS2, WDIS3, WDIS.
4 is output. The word line ground signal WDIS1 is the transistor 5 connected to the word lines 36 and 49 to which the output signal WBST1 from the word line booster circuit 21 is input.
Input to 3,57 gates. Similarly, the word line ground signals WDIS2, WDIS3, and WDIS4 are similarly connected to the transistors 52, 56, 51 connected to the word lines 35, 48, 34, 47, 33, 46 to which the output signals WBST2, WBST3, WBST4 are input. -It is input to the gates of 55, 50 and 54.

The same circuits as those of the conventional semiconductor memory device shown in FIG. 3 are designated by the same reference numerals as those in FIG. 3 and their explanations are omitted.

The ground word line selection circuit 61 outputs the word line ground signals WDIS1 to WDIS4 corresponding to the activated output signals WBST1 to WBST4 in response to the drive signal from the word line boosting circuit 21. At that time, the activated output signals WBST1 to WBST4
Output word line ground signals WDIS1 to WDIS4
The relationship with the level of is as shown in Table 1.

[0021]

[Table 1]

According to Table 1, for example, the word line selection signal output circuit 5 activates the word line selection circuit 22, and the word line boosting circuit 21 outputs the output signal WBST.
When 1 is activated, the word line ground signal WDIS
The level of 1 becomes "L", and other word ground signals W
The level of DIS2, ..., WDIS4 becomes "H". Therefore, the transistors 53 and 57 of the word line ground circuit 9 are
Turns off, and the other transistors 50, ..., 52,
54, ..., 56 are turned on.

As a result, the word lines 33, ...
, 48 are grounded, and the unactivated word lines 33, ..., 35 among the word lines connected to the activated word line selection circuit 22 are surely grounded. On the other hand, as described above, the transistor 57 is "off", but the word line 49 is grounded as follows. That is, since the word line selection circuit 23 is in the non-selected state as described in the conventional example, the word line selection signal of level "H" is input to the word line selection signal line 37. Therefore, the transistor 41 is turned "on" and the word line 49 is connected.

That is, according to the present embodiment, during operation, all the word lines except the activated word line (for example, the word line 36) are grounded, so that the floating word lines are It does not exist. Therefore, even in the non-activated word line adjacent to the activated word line, it is less susceptible to the noise from the activated word line, and stable data writing / reading can be performed.

In the above embodiment, the word line boosting circuit 21 outputs the output signals WBST1 to WBST4 to activate one of the floating word lines. .. However, the present invention is not limited to this, and normally activates two word lines forming a complementary pair.

[0026]

As is apparent from the above, the semiconductor memory device of the present invention is driven by the drive signal from the word line boosting circuit and is selected by the word line selecting signal output circuit from the word line group. Since the ground word line selection circuit that selectively grounds the non-activated word line that has not been activated by the line booster circuit is provided, the word line booster circuit selects the All word lines that are not activated can also be grounded. Therefore, even a non-activated word line adjacent to the activated word line is hardly affected by noise from the activated word line and can operate stably.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device of the present invention.

FIG. 2 is a block diagram of a conventional semiconductor memory device.

FIG. 3 is a partial circuit diagram of the conventional semiconductor memory device shown in FIG.

[Explanation of symbols]

1 ... Timing generation circuit, 5 ... Word line selection signal output circuit, 6 ... Storage section,
7 ... Column address selection circuit, 9 ... Word line ground circuit,
21 ... Word line boosting circuit, 22, 23 ... Word line selecting circuit, 25-32, 38-45, 50-57 ... Transistor, 33-36, 46-49 ... Word line, 61 ... Ground word line selecting circuit.

Claims (1)

[Claims] 1. A memory section and a word line selection signal for designating an address of the storage section based on an address signal from the outside and selecting a word line group including a word line corresponding to the designated address. A word line selection signal output circuit that outputs the word line selection signal, a word line selection circuit that sets a selected word line group in a floating state based on the word line selection signal, and an address signal from the word line selection signal output circuit The word line boosting circuit for boosting the voltage of the word line corresponding to the designated address in each of the word line groups in the floating state to activate the word line, and the word line boosting circuit Driven by the drive signal, the word line booster circuit of the word line group selected by the word line selection signal output circuit The semiconductor memory device characterized by including a ground word line selection circuit for selectively grounding the deactivated word lines which are not activatable.