JPH05218411A - Field effect transistor and manufacture thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide a field-effect transistor which does not deteriorate the response speed, can easily control the width of a channel region, and is free from short-channel deterioration, and a manufacturing method thereof. In a field-effect transistor including a channel formed in a silicon substrate, source / drain adjacent to both sides of the channel, and a gate electrode formed on the channel via an insulating film, the channel has a threshold voltage. It is composed of a conductive central region corresponding to the voltage and a conductive end region adjacent to both sides of the conductive central region that can prevent deterioration of the short channel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and its manufacturing method. More specifically, it relates to an improvement of a MOS field effect transistor having a channel length of submicron.

[0002]

2. Description of the Related Art Conventionally, in a MOS transistor formed on bulk silicon with a submicron size, when the channel length becomes about the same as the depletion layer width of the source / drain regions, the threshold voltage is lowered. It shows a significant deterioration of electrical properties due to the reduced mobility of carriers. These effects are known as "short channel" degradation, which is a severe constraint on device miniaturization. The first way to overcome some of these constraints is to have a higher doping near the junction of source 31 and drain 32 to reduce the spread of the depletion layer into the channel region as shown in FIG. 4 (a). This is done by forming a so-called halo or pocket 33 of the area. However,
Reference numeral 34 is a gate electrode, and 35 is a channel.

The second method is the use of oblique rotating ion implantation to form non-uniformly doped channels as shown in FIG. 4 (b). According to this method, the end regions 36 near the source and drain are formed in the channel.
At a doping concentration higher than that of the central region 3 of the channel at the same time, so as to reduce the spread of the depletion region.
In step 7, the doping concentration is set so that the carrier mobility can be reduced. However, 38 is a gate electrode, 39 is a source, and 40 is a drain.

[0004]

The first method described above is a constraint when manufacturing a transistor having a channel length of which the implantation depth and the lateral spread are less than 0.5 μm, and further, a higher doping concentration in the drain junction. However, there is a problem that the junction parasitic capacitance is increased and the response speed is reduced. The second method requires a relatively large implantation angle and energy because the impurities need to penetrate to about 1/3 of its channel length, resulting in i) a higher doping concentration at the drain junction to be destroyed. Decrease the voltage, decrease the junction capacitance and decrease the response speed, ii)
Particularly, in a device having a size of less than 0.5 μm, there is a problem that it becomes difficult to control the width of the channel central region.

The present invention has been made to solve the above problems, and provides a field effect transistor which does not deteriorate the response speed, can easily control the width of a channel region, and has no short channel deterioration, and a method for manufacturing the same. Is what you are trying to do.

[0006]

SUMMARY OF THE INVENTION The present invention is a field effect transistor constructed by forming a channel having a non-uniform doping concentration by ion implantation several times in a self-aligned manner perpendicular to a silicon substrate. And its manufacturing method. According to the present invention, in a field effect transistor including a channel formed in a silicon substrate, a source / drain adjacent to both sides of the channel, and a gate electrode formed on the channel via an insulating film, the channel is A field effect transistor is provided which comprises a conductive central region corresponding to a threshold voltage and an end region of a predetermined conductivity higher than said conductivity.

The field effect transistor of the present invention can be manufactured, for example, as follows. First, a silicon nitride film having a window of a gate region is formed on a silicon substrate through a silicon oxide film, and ion implantation is performed through the window of the silicon nitride film to a first region of a predetermined concentration in a channel region.
Do doping. The silicon oxide film is for protecting the silicon substrate, and can be used as an etching stopper in the etching process for opening windows of the silicon nitride film and the polysilicon layer. This film thickness is usually 0.01 to 0.03 μm. The silicon nitride film serves as a mask for ion implantation in the first and second doping steps performed in the channel region and a mask for stacking the gate electrode forming material, and has a window in the gate region. Have. This film thickness is usually 0.3 to 0.
It is 5 μm. The first doping is performed at a predetermined concentration so that the central region of the channel becomes conductive corresponding to a predetermined threshold voltage of the MOSFET. The threshold voltage is usually 0.4 to 1.0V. The predetermined concentration is
Usually 10 ¹¹ to 10 ¹² ion / cm ³ , usually 5 × 10 ¹¹ to
It is performed by controlling the dose of impurity ions to 1 × 10 ¹² ions / cm ² .

Next, a silicon oxide sidewall having a predetermined thickness is formed along the side surface of the silicon nitride on the end side of the gate region, and a polysilicon layer is formed on the remaining gate region. The silicon oxide side wall is for forming a mask when forming the polysilicon layer, and can be formed to have a predetermined thickness so as to cover the end of the gate region by a known method. The predetermined thickness is usually 0.1 to 0.3 μm. The polysilicon layer serves as a mask for implanting impurity ions into the end region of the channel region through both end regions of the gate region, and the polysilicon layer is formed in the remaining gate region so as to be adjacent to the silicon oxide sidewall. It can be formed by embedding silicon. This width is a width corresponding to the central region of the channel, and is usually 0.2 to 1.0 μm.
Is.

Next, after removing the side wall of the silicon oxide, a second doping of a predetermined concentration is performed on the end side of the channel region by ion implantation using the silicon nitride film and the polysilicon layer as a mask. The second doping is for forming an end region of the channel capable of preventing short channel deterioration. After the silicon oxide side wall is removed, the impurity concentration on the end side of the channel region is usually 2 × 10 ^{17 to} 5
× 10 ¹⁷ ion / cm ³ and made as 1 × 10 ¹³ ~3 × 10 ¹³
It is performed by irradiating with impurities of ion / cm ² .

Next, after removing the polysilicon layer and the silicon oxide film below the gate region, a gate insulating film having a predetermined thickness is formed and a gate electrode is formed thereon. A silicon oxide film is usually used as the gate insulating film. This film thickness is 0.01 to 0.05 μm. The gate electrode is formed by burying polysilicon or metal in the gate region, for example.

Next, after removing the silicon nitride film, a source and a drain are formed by ion implantation using the gate electrode as a mask to manufacture a field effect transistor.

[0012]

The channel central region formed only by the first doping exhibits conductivity that sets the threshold voltage of the MOSFET, and the channel end regions formed by the first and second doping prevent short channel deterioration. ..

[0013]

Embodiments of the present invention will be described with reference to the drawings.
In this example, the main fabrication steps for a MOSFET with a non-uniformly doped channel are shown for the formation of an N-channel transistor, but similarly P
-Applicable to channel type transistors and CMOS
It can also be applied to processes.

First, as shown in FIG. 1A, an element isolation region (field oxide film) 2 and an active region 3 are formed in a silicon substrate 1 by a known MOS process technique. Next, a thin insulating oxide film 4 is formed on the active region 3 by a thermal growth method or C
It is formed by the VD method so as to have a film thickness of 20 to 30 nm. Next, by a CVD method, S with a film thickness of 300 to 500 nm is formed.
A window 6 for a channel is formed by patterning the iN layer 5 by stacking the iN layer 5 and using a photoresist for setting a gate electrode or a channel region by a photoetching method. Next, boron ions 7 are injected into the silicon substrate through the window 6 at a dose of 10 ¹¹ to 10 ¹² ions / cm ² , and the doping concentration in the central region of the channel is set so as to correspond to this MOSFET threshold voltage.

Next, as shown in FIG. 1B, a silicon oxide layer is deposited by the CVD method and etched back by the isotropic etching method to form sidewalls 8 and 8 '. The deposited thickness of this CVD silicon oxide layer is set to obtain a sidewall width corresponding to the width of the higher doping channel region. For example, the width of this sidewall is about 1/3 of the channel length of the smallest transistor. Film thickness after sidewall formation 300 to 5
A 00 nm polysilicon layer 9 is deposited.

Next, as shown in FIG. 1C, the polysilicon layer 9 is etched back by an isotropic etching method to leave the polysilicon only in the space between the sidewalls 8 and 8'and the polysilicon layer 10 is left. To form. Next in FIG.
As shown in (d), after removing the sidewalls 8 and 8'of CVD silicon oxide, the polysilicon layer 10 and SiN are removed.
The second channel boron ions 11 are doped using the layer as a self-alignment mask. This implantation sets the impurity atom concentration at the end of the channel to be suitable for reducing the short channel deterioration.

Next, as shown in FIG. 2E, the channel window 6
The polysilicon layer 10 and the insulating oxide film 4 in the inside are removed by wet etching. Next, as shown in FIG. 2F, a gate oxide film 12 is formed by thermal growth to a thickness determined by the electrical characteristics of the MOSFET. In the next step, as shown in FIG. 3G, a polysilicon layer 13 having a film thickness of 400 to 600 nm is deposited by LPCVD and doped with N ⁺ .

Next, as shown in FIG. 2H, the polysilicon layer 13 is etched back by an anisotropic etching method to form a final gate electrode 14. Next, as shown in FIG. 2I, after removing the SiN layer 5 with a wet etching agent,
Impurity ions 15 are implanted by a known method to perform MO.
The LDD (lightly doped drain) region 16 of the SFET is doped.

Next, as shown in FIG. 3J, after forming a side wall 17 of silicon oxide, impurity ions 18 are implanted to form a source 19 and a drain 20 of the MOSFET. Next, a separation layer 21 is deposited as shown in FIG.
A contact window is opened, and a metal layer is deposited and patterned to form a wiring layer 22 to form a MOSFET.

[0020]

According to the present invention, it is possible to provide a field-effect transistor in which the response speed does not decrease, the width of the channel region can be easily controlled, and short-channel deterioration does not occur, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a field effect transistor manufactured in an example of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process of a field effect transistor manufactured in an example of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of the field effect transistor manufactured in the example of the present invention.

FIG. 4 is an explanatory diagram of a conventional field effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation region (field oxide film) 3 Active region 4 Insulating oxide film 5 SiN layer 6 Window 7 Boron ion 8, 8'sidewall 9 Polysilicon layer 10 Polysilicon layer 11 Boron ion 12 Gate oxide film 13 Poly Silicon layer 14 Gate electrode 15 Impurity ion 16 LDD region 17 Side wall of silicon oxide 18 Impurity ion 19 Source 20 Drain 21 Separation layer 22 Wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication 7377-4M H01L 29/78 301 L 7377-4M 301 H

Claims (2)

[Claims] 1. A field effect transistor comprising a channel formed in a silicon substrate, a source / drain adjacent to both sides of the channel, and a gate electrode formed on the channel with an insulating film interposed therebetween. A field effect transistor comprising a conductive central region corresponding to a threshold voltage and an end region having a predetermined conductivity higher than the conductivity. 2. A) A silicon nitride film having a gate region window is formed on a silicon substrate via a silicon oxide film, and ion implantation is performed through the window of the silicon nitride film to a first region of a predetermined concentration in the channel region. B) forming a silicon oxide side wall of a predetermined thickness along the side surface of the silicon nitride on the end side of the gate region and forming a polysilicon layer on the remaining gate region; and c) oxidation. After removing the silicon side wall, a step of performing second doping with a predetermined concentration on the end side of the channel region by ion implantation using the silicon nitride film and the polysilicon layer as a mask, and d) the polysilicon layer and the gate region below the gate region. After removing the silicon oxide film, a gate insulating film having a predetermined thickness was formed, a gate electrode was formed thereon, and after removing the silicon nitride film, the gate electrode was used as a mask. A method of manufacturing a field effect transistor, which comprises forming a source and a drain by ion implantation.