JPH05218421A - Manufacture of mis semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a method of manufacturing a MIS type semiconductor device on an insulating substrate, and an object thereof is to obtain a gate structure for improving the characteristics of a MISFET. [Structure] A step of forming an insulating film in a semiconductor layer by a SIMOX method or the like to form an SOI structure, a step of stacking a semiconductor layer on the semiconductor layer by epitaxial growth, and the like, and selectively forming an insulating film in the semiconductor layer. By repeating the step of forming and the step of selectively doping impurities in the semiconductor layer,
At the center of the island-shaped semiconductor layer stacked on the insulating substrate, there is a channel layer surrounded by a gate diffusion layer on each side of the insulating layer. It is configured so that it is in contact with the layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit on an SOI substrate, and more particularly to a method for manufacturing a gate electrode for improving the characteristics of MOSFET.

The advanced information processing society is developing more and more, and the existence of higher speed computers is required. For this purpose, there is a demand for speeding up of integrated circuit elements, which are basic parts of computers, and further miniaturization and speeding up of MOS transistors, which are substrate elements of these integrated circuit elements.

The present invention is used in these industrial fields.

[0004]

2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 11 is a SiO ₂ film, 12 is a Si layer, 13 is an opening (planned region),
13 'is an opening (overetch), 14 is a channel layer, 15 is a source / drain diffusion layer, 16 is a lower gate poly-Si electrode,
17 is the lower gate SiO ₂ film, 18 is the upper gate SiO ₂ film, 19 is the upper gate poly-Si electrode, 20 is the SiO ₂ film, 21 is CVD / SiO 2.
₂ films, 22 is a PSG film, and 23 is a source / drain Al electrode.

Conventionally, as shown in the sectional view of one Si layer 12 in FIG. 3A, a semiconductor substrate such as a Si layer 12 on an insulator such as a SiO ₂ film 11 is processed into a plurality of islands. ， This each island Si layer 12
Approximately an SiO ₂ film under the central portion in cross section in FIG. 3 (b), as shown in plan view in FIG. 3 (c), not shown in the region where the gate electrode forming portion by removing a portion of the The opening is formed using a mask such as a Si ₃ N ₄ film.

After that, as shown in the sectional view of the completed device in FIG. 3C, an insulator such as a SiO ₂ film or a PSG film is formed by oxidation or deposition to form a poly-Si film or an Al film. The conductor or semiconductor film is deposited, and the conductor or semiconductor film is processed to form the gate electrode.

[0007]

Therefore, in the MOS transistor according to the conventional manufacturing method, since the lower hole is opened by the isotropic etching to engrave the lower portion of the Si layer by using a mask, it is inevitable that the MOS transistor is over-etched. It becomes an etching, and it becomes an overetched opening 13 'from the originally planned area 13.
The lower gate electrode 16 has a larger area by the amount of over-etching than the size of the upper gate electrode 19 that will be formed later, and it is difficult to manufacture with high precision, and the upper and lower gate electrodes 16 and 19 are formed with deviation. There was a problem that would end up.

In order to prevent this, it was usually necessary to make the upper electrode large. In this way, the stray capacitance of the gate electrode increases, making it difficult to improve high-speed operation.

[0009]

FIG. 1 is an explanatory view of the principle of the present invention, and FIG. 2 is a schematic sectional view in order of the steps of the present invention. In the figure, 1 is an insulating substrate, 2, 2A to 2E are semiconductor layers, 3 is an insulating layer, 3A is a lower insulating layer, 3B is a lower gate insulating layer, 3C is a side gate insulating layer, and 3D is an upper gate insulating layer. , 3E is an upper insulating layer, 4 is a gate diffusion layer, 4A is a lower gate diffusion layer, and 4B to 4D
Is a side gate diffusion layer, 4E is an upper gate diffusion layer, 5 is a channel layer, and 6 and 6A to 6C are source / drain diffusion layers.

The above-mentioned displacement of the upper and lower gate diffusion layers can be solved by forming the upper and lower diffusion layers by a lithographic technique. Therefore, in the present invention, the Si layer stacked on the semiconductor layer is
Layer, and SIMOX (Separation by Implant
ed Oxygen) method to inject oxygen to form a SiO ₂ layer,
It has a three-dimensional structure.

At that time, the Si layer and the Si
A region of the O ₂ layer is two-dimensionally defined and formed in a desired region.
In addition, as for the stacking of the Si layers, the Si layers are sequentially epitaxially grown.

By repeating these two steps, Si
By forming a three-dimensional laminated structure of SiO ₂ film or Si ₃ N ₄ film, the gate diffusion layers on the top, bottom, left and right of the island-shaped Si layer can be accurately formed.

The island-shaped semiconductor layer can be formed by an epitaxial growth method, a semiconductor thin film substrate attachment method, or the like, and the insulating layer can be formed by a SIMOX method, a LOCOS method, or the like. That is, an object of the present invention is to show an island-shaped semiconductor layer formed on an insulating substrate in FIG. 1 in a perspective view and a cross-sectional view in the X-axis direction and the Y-axis direction. A channel layer 5 surrounded by a gate diffusion layer 4 on each side of an insulating layer 3 is provided at the center of a semiconductor layer 2 formed in a stacked island shape, and both ends of the channel layer 5 are source / drain. Diffusion layer 6
By using the MIS type semiconductor device characterized by being in contact with, and as shown in FIG. 2A, the island-shaped one conductivity type first semiconductor layer 2A is formed on the insulating substrate 1. Process and as shown in FIG. 2B, the first semiconductor layer 2A
A step of selectively forming a lower insulating layer 3A defining a lower gate diffusion layer 4A therein, and a step of doping an impurity into the first semiconductor layer 2A to form the lower gate diffusion layer 4A, As shown in FIG. 2C, a step of laminating a second semiconductor layer 2B of one conductivity type on the first semiconductor layer 2A, and a side gate diffusion layer 4B in the second semiconductor layer 2B. A step of selectively forming the defining lower gate insulating layer 3B, a step of doping an impurity into the second semiconductor layer 2A to form a side gate diffusion layer 4B, and as shown in FIG. To
A third semiconductor layer 2 of one conductivity type is formed on the second semiconductor layer 2B.
A step of stacking C, and a step of selectively forming a side gate diffusion layer 4C in the third semiconductor layer 2C and a side gate insulating layer 3C defining the channel layer 5 and the source / drain diffusion layer 6A, A step of selectively doping an impurity into the third semiconductor layer 2C to form a side gate diffusion layer 4C; and a step of selectively doping an impurity of an opposite conductivity type into the third semiconductor layer 2C to form a source The step of forming the drain diffusion layer 6A and the third semiconductor layer as shown in FIG.
A step of laminating a fourth semiconductor layer 2D of one conductivity type on 2C, and a side gate diffusion layer 4D in the fourth semiconductor layer 2D.
And a step of selectively forming an upper gate insulating layer 3D that defines the source / drain diffusion layer 6B, and a side gate diffusion layer 4D is formed by selectively doping impurities into the fourth semiconductor layer 2D. A step of forming a source / drain diffusion layer 6B by selectively doping an impurity of opposite conductivity type into the fourth semiconductor layer 2D, and as shown in FIG. A step of stacking a fifth semiconductor layer 2E of one conductivity type on the semiconductor layer 2D, and an upper insulating layer 3E defining an upper gate diffusion layer 4E and a source / drain diffusion layer 5C in the fifth semiconductor layer 2E. And a step of selectively doping impurities into the fifth semiconductor layer 2E to form the upper gate diffusion layer 4E, and a step of forming an upper gate diffusion layer 4E of the opposite conductivity type in the fifth semiconductor layer 2E. Selectively doping impurities to form the source / drain diffusion layer 6C. It is achieved by.

[0014]

As described above, according to the present invention, the gate diffusion layers on the upper, lower, left and right sides of the island-shaped semiconductor layer can be accurately formed, and the gate diffusion layer having a small parasitic capacitance can be formed.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2A to 2C are explanatory views in order of steps of one embodiment of the present invention for an n-channel MOSFET transistor.

In each step, the left side is a perspective view of one laminated semiconductor layer, the center is a plan view of the upper surface thereof, and the right side is a sectional view of the central portion of the semiconductor layer. Si substrate coated with SiO ₂ film as insulating substrate 1, p-type Si layer as semiconductor layer 2, insulating layer 3
As a SiO ₂ layer and the gate diffusion layer 4 as an arsenic-doped n ⁺
A p-type Si layer was used as the channel type gate diffusion layer, the channel layer 5 was used, and an arsenic-doped n ⁺ type source / drain layer was used as the source / drain layer 6.

The product of the second to fifth semiconductor layers 2B to 2E
All layers should be epitaxially grown and the insulating film 3 should be formed.
The SIMOX method was used. According to the above manufacturing conditions,
As shown in Fig. 1 (a), SiO is formed on an 8-inch Si substrate.₂The membrane
Cover with a thickness of 1 μm, and attach a p-type Si substrate on it
The thickness of the first semiconductor layer 2A is 0.1 μm by precision polishing.
To finish. Then, using the resist as a mask, the pattern
Etching to form thousands of island-shaped Si layers
It Then, as shown in FIG. 2B, the SIMOX method is used.
To heat the Si substrate to 650 ℃ and accelerate the oxygen ion
 30KeV, Dose 3.0x10¹⁸/cm²Inject under the conditions of
Side SiO₂Membrane 3A was formed. The peak position is 0.05 μm on the surface,
The width is 0.09 μm. Then, using the ion implantation method,
For example, arsenic ion (As⁺) Accelerating voltage 15KeV, Dose amount 1x
Ten ¹⁵/cm²The lower gate diffusion layer 4A A
Form.

Next, as shown in FIG. 2C, the second Si
Layer 2B is laminated to a thickness of 0.05 μm. Then, the lower gate SiO ₂ layer 3B that defines the side gate diffusion layer 4B is heated to 650 ° C. by a SIMOX method to heat the Si substrate to oxygen ions (O ⁺ ).
Is implanted under the conditions of an accelerating voltage of 15 KeV and a dose of 1.5 × 10 ¹⁸ / cm ² to form a lower gate SiO ₂ film 3B. The peak position is 0.025 μm on the surface and the width is 0.045 μm. After that, for example, arsenic ions (As ⁺ ) are implanted into the second Si layer 2A by an ion implantation method under the conditions of an acceleration voltage of ¹⁵ KeV and a dose amount of 1 × 10 ¹⁵ / cm ² to form a side gate diffusion layer 4B. ..

As shown in FIG. 2D, an n-type third Si layer 2C is epitaxially grown to a thickness of 0.1 μm on the second Si layer 2B. Next, the side gate diffusion layer 4C in the third Si layer 2C and the side gate SiO ₂ layer 3C that defines the channel layer 5 and the source / drain diffusion layer 6A are described in FIG. 2B.
It is selectively formed under the same conditions as the IMOX method.

Side gate diffusion layer 4C is formed by selectively implanting arsenic into third semiconductor layer 2C under the same conditions as the ion implantation method described with reference to FIG. 2B, using a resist film (not shown) as a mask.
And the source / drain diffusion layer 6A is formed.

As shown in FIG. 2 (e), an n-type fourth Si layer 2D is epitaxially grown to a thickness of 0.05 μm on the third Si layer 2C. Next, the side gate diffusion layer 4D and the upper gate SiO ₂ layer 3D that defines the source / drain diffusion layer 6B are selectively formed in the fourth Si layer 2D under the same conditions as the SIMOX method described in FIG. 2B. To form. Then, the side gate diffusion layer 4D is formed in the fourth Si layer 2D by the same method as described above.

Boron is selectively ion-implanted into the fourth Si layer 2D to form the source / drain diffusion layer 6B by the same method as described above. As shown in FIG. 2F, an n-type fifth Si layer 2E is epitaxially grown to a thickness of 1.0 μm on the fourth Si layer 2D. Then, the upper gate diffusion layer is formed in the fifth Si layer 2E.
4E and upper SiO ₂ layer that defines the source / drain diffusion layer 5C
3E is selectively formed by the same method as described above. Then, arsenic is selectively ion-implanted into the fifth Si layer 2E by the same method as described above to form the source / drain diffusion layer 6C.

After that, the entire Si substrate is heat-treated in nitrogen at 1,100 ° C. for 2 hours to activate the implanted oxygen to form the SiO ₂ film 3 three-dimensionally in the semiconductor layer 2. After that, although not shown, the island-shaped Si layer is entirely covered, the Si SiO ₂ film is covered on the Si substrate, and the substrate is flattened with an SOG film or the like, and the gate diffusion layer 4 and the source / drain diffusion layer 6 are formed. Si
A through hole is opened in the O ₂ film, the Al electrode is covered by the sputtering method and patterned to form the gate electrode and source / drain electrode wiring, and the three-dimensional MOSFET is formed into the SiO ₂ film 1
Complete on top.

[0024]

As described above, according to the present invention,
The gate diffusion layers on the upper, lower, left, and right sides of the island-shaped Si layer can be accurately formed, and the gate diffusion layer and the electrode having a small parasitic capacitance can be formed, which greatly contributes to the speedup of the MOSFET.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

2A to 2D are schematic explanatory views in order of steps of one embodiment of the present invention.

FIG. 3 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Insulating substrate 2, 2A to 2E Semiconductor layer 3 Insulating layer 3A Lower insulating layer 3B Lower gate insulating layer 3C Side gate insulating layer 3D Upper gate insulating layer 3E Upper insulating layer 4 Gate diffusion layer 4A Lower gate diffusion layer 4B to 4D Side gate diffusion layer 4E Upper gate diffusion layer 5 Channel layer 6, 6A to 6C Source / drain diffusion layer

Claims (1)

[Claims] 1. A step of forming an island-shaped one conductivity type first semiconductor layer (2A) on an insulating substrate (1), and a lower gate diffusion in the first semiconductor layer (2A). A step of selectively forming a lower insulating layer (3A) that defines the layer (4A), and a step of doping an impurity into the first semiconductor layer (2A) to form a lower gate diffusion layer (4A) And a second semiconductor layer (2) of one conductivity type on the first semiconductor layer (2A).
B), a step of selectively forming a lower gate insulating layer (3B) defining a side gate diffusion layer (4B) in the second semiconductor layer (2B), Forming a side gate diffusion layer (4B) by doping impurities into the semiconductor layer (2A), and forming a third semiconductor layer (2) of one conductivity type on the second semiconductor layer (2B).
C), and a side gate insulating layer (4C) defining the side gate diffusion layer (4C), a channel layer (5) and a source / drain diffusion layer (6A) in the third semiconductor layer (2C). 3C) is selectively formed, a side gate diffusion layer (4C) is formed by selectively doping impurities into the third semiconductor layer (2C), and the third semiconductor layer (4C) is formed. 2C) a step of selectively doping an impurity of opposite conductivity type to form a source / drain diffusion layer (6A), and a fourth semiconductor layer of one conductivity type on the third semiconductor layer (2C) (2
Stacking D), and an upper gate insulating layer defining a side gate diffusion layer (4D) and a source / drain diffusion layer (6B) in the fourth semiconductor layer (2D)
A step of selectively forming (3D), a step of selectively doping an impurity into the fourth semiconductor layer (2D) to form a side gate diffusion layer (4D), and the fourth semiconductor layer A step of selectively doping an impurity of opposite conductivity type in (2D) to form a source / drain diffusion layer (6B); and a fifth semiconductor of one conductivity type on the fourth semiconductor layer (2D) Layer (2
E) stacking step, and selectively forming an upper gate diffusion layer (4E) and an upper insulating layer (3E) defining a source / drain diffusion layer (5C) in the fifth semiconductor layer (2E) And a step of selectively doping an impurity into the fifth semiconductor layer (2E) to form an upper gate diffusion layer (4E), and an opposite conductivity type in the fifth semiconductor layer (2E). And a step of selectively doping the impurity of (1) to form a source / drain diffusion layer (6C), the manufacturing method of the MIS type semiconductor device.