JPH05252032A - D/a converter - Google Patents

Abstract

(57) [Abstract] [Purpose] D for converting digital signals to analog signals
With respect to the A conversion device, the offset included in the conversion output is canceled. A return-zero type DA converter (DAC) 1 for converting an input digital signal Din into an analog signal in accordance with a clock signal from a clock circuit 5, and this D
A chopper-type sample hold that cancels the offset by sampling the effective point of the output analog signal of the A conversion unit 1 and the zero point that is a return zero, and using the sampling value of the zero point as an offset value and subtracting from the sampling value of the effective point The circuit 2 is provided with a filter 3 and a post filter 4 for adding a hold output signal of the chopper type sample and hold circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA converter for converting an input digital signal into an analog signal. A digital transmission system is known in which an analog voice signal is converted into a PCM signal and transmitted, and the receiving side converts the PCM signal into an analog voice signal, and a DA conversion for converting the PCM signal into an analog voice signal on the receiving side. A device is provided. Since such a DA converter includes an offset in the output signal, it is desired to cancel it.

[0002]

2. Description of the Related Art A conventional DA converter is shown in FIG.
21 has a configuration shown in FIG.
AC), 22 is a low pass filter (LPF), 23 is a post filter (PF), and 24 is a clock circuit.

The DA converter 21 converts the input digital signal Din into an analog signal in accordance with the clock signal from the clock circuit 24, and inputs the converted analog signal into the low-pass filter 22. The low-pass filter 22 often uses a switched capacitor filter. In that case, a clock signal is applied from the clock circuit 24 as shown in the figure. The output signal of the low pass filter 22 is input to the post filter 23 and becomes the output analog signal Aout.

When the input digital signal Din is a sine wave, the output signal of the DA converter 21 has a stepwise waveform as shown below, and the output of the sine wave shown below via the low-pass filter 22 and the post filter 23. It becomes the analog signal Aout.

The DA converter 21 is a return-zero type DA converter (circular comparison type) having a switched capacitor structure, and once returns to zero at each conversion step and outputs an effective conversion analog signal after a predetermined conversion step.

[0006]

As shown in the lower part of FIG. 3, the converted output signal includes the offset value OFS due to variations in the operational amplifier and elements of the DA converter 21 and temperature changes. , Low-pass filter 2
The offset value is also included in the analog signal Aout output via 2 and the post filter 23. Therefore, when applied to a voice signal, there is a drawback that the voice quality deteriorates. Also, the return zero type DA converter also includes the offset value OFS,
Deterioration of voice quality becomes a problem. An object of the present invention is to cancel the offset included in the converted output of the DA converter.

[0007]

A DA converter of the present invention will be described with reference to FIG. 1. A return zero type DA converter (DAC) 1 for converting an input digital signal into an analog signal, and this DA converter. A chopper type that cancels the offset of the output analog signal of the DA conversion unit 1 by sequentially sampling the effective point of the output analog signal of the conversion unit 1 and a zero point that is a return zero and using the sampling value at this zero point as an offset value. Sample and hold circuit (S
H) 2 and a filter (LPF) 3 for adding the hold output signal of the chopper type sample and hold circuit 2.

[0008]

When the input digital signal Din shows a sine wave, the output signal of the DA converter 1 has a return-zero type configuration in which it returns to zero as shown below, and includes an offset. The chopper type sample and hold circuit 2 samples the effective point and the zero point of the output analog signal of the DA converter 1 and uses the sampling value of the zero point as an offset value and subtracts it from the sampling value of the effective point to obtain the offset. Cancel. Therefore, the output signal of the sample and hold circuit 2 has an analog signal waveform with the offset canceled, and the harmonic component is removed by the next filter 3.

[0009]

FIG. 1 is a block diagram of an embodiment of the present invention,
The DA converter (DAC) 1 is, for example, a return-zero type DA converter having a switched capacitor configuration, operates in synchronization with the clock signal from the clock circuit 5, and returns to zero as shown below. Is output. The sample hold circuit (SH) 2 has a chopper type configuration, and is synchronized with the clock signal from the clock circuit 5,
The effective point and zero point of the analog signal output from the DA converter 1 are sampled.

The filter (LPF) 3 has, for example, a switched capacitor filter configuration, operates according to the clock signal from the clock circuit 5, removes harmonic components contained in the output signal of the sample hold circuit 2, At the same time, sinx / x is corrected. Further, the post filter (PF) 4 removes the remaining harmonic component to obtain an output analog signal Aout.

The chopper type sample and hold circuit 2 is
For example, with the configuration shown in FIG. 2, SW1, SW
2 is a switch, C is a capacitor, OPA is an operational amplifier,
IN is an input terminal and OUT is an output terminal. Input terminal I
N is connected to the DA converter 1 shown in FIG. 1, and the output terminal OU
T is connected to the filter 3.

The positive terminal of the operational amplifier OPA is (1/2)
V _DD (Signal Ground Level) is added. A capacitor C and a switch SW1 are connected to the negative terminal, and the capacitor C is switched and connected to an input terminal IN and an output terminal OUT by a switch SW2. Also switch SW
1 and SW2 are composed of transistors or the like, and operate in synchronization with a clock signal from the clock circuit 5.

The switch SW1 is turned on to turn on the operational amplifier O.
Connect the output terminal and negative terminal of PA, and switch SW
When 2 is switched to the input terminal IN side, the voltage applied to the input terminal IN is applied to the capacitor C and charged, and the sampling operation is performed. Next, when the switch SW1 is turned off and the switch SW2 is switched to the output terminal OUT side, an output signal corresponding to the charging voltage of the capacitor C is obtained. That is, the hold operation is performed.

3A and 3B are diagrams for explaining the operation of the embodiment of the present invention. FIG. 3A shows an example of the output signal of the DA converter 1, and FIG. 3B shows an example of the hold output signal. (1/2) V _DD is shown. DA
The conversion unit 1 returns to the zero level at every predetermined cycle and outputs an effective conversion analog signal at every constant cycle T1. When the offset value OFS is zero, it is a return zero type, so a zero level [(1/2) is set at every predetermined cycle.
V _DD ], but when the offset value OFS exists, it does not return to the zero level as shown in (a).

Therefore, in the chopper type sample and hold circuit 2, the time point at which the effective conversion analog signal is output and its level is determined is set as the effective point, which is set as the sampling point SP2, and the previous return zero is used. The zero point is set as the sampling point SP1. That is, at the sampling point SP1, the switch SW1 is turned on and the switch SW2 is switched to the input terminal IN side to sample the zero point. Next, switch SW1 is turned off, switch SW2
To the output terminal OUT side.

When the switch SW2 is switched to the input terminal IN side again at the sampling point SP2 of the next effective conversion analog signal, the voltage Va based on the offset value OFS held in the capacitor C and the voltage Vb based on the sampling value of the effective point. Therefore, the capacitor C is charged by the difference (Vb-Va). Then, by switching the switch SW2 to the output terminal OUT side, the capacitor C
The charging voltage is held and output from the output terminal OUT as a hold value as shown in (b).

The clock circuit 5 is composed of the above-mentioned switch SW.
1, which outputs a clock signal for controlling SW2, and can be realized by a known configuration using a counter or the like. The dotted line in (b) is the sampling point S
The offset value OFS sampled by P1 is shown.

As described above, when the output of the DA converter 1 includes an offset, the zero point of the return zero is sampled by the chopper type sample and hold circuit 2, the offset value is held, and the next value is stored. Since the configuration is such that the sampling value of the effective point is subtracted, the offset can be canceled and the deterioration of the voice quality in the case of a voice signal can be prevented.

The present invention is not limited to the above-described embodiment, but can be variously added and changed, and is applied to the case where not only a voice signal but also various digital signals are converted into analog signals. it can.

[0020]

As described above, the present invention is provided with the return-zero type DA conversion section 1, the chopper type sample-hold circuit 2 and the filter 3, and the output analog signal of the DA conversion section 1 is validated. The sample and hold circuit 2 samples the points and the zero point that is the return zero,
With the sampling value at the zero point as the offset value,
It is possible to cancel the offset value included in the sampling value of the effective point. Therefore, there is an advantage that the deterioration of the voice quality can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a chopper type sample hold circuit.

FIG. 3 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 DA converter (DAC) 2 Chopper type sample and hold circuit (SH) 3 Filter (LPF) 4 Post filter (PF) 5 Clock circuit

Claims (1)

[Claims] 1. A return zero type DA converter (1) for converting an input digital signal into an analog signal, an effective point of an output analog signal of the DA converter (1) and a zero point which becomes a return zero in order. Sampling is performed, and the sampling value at the zero point is used as an offset value for the D
A chopper type sample and hold circuit (2) for canceling the offset of the output analog signal of the A conversion section (1), and a filter (3) for adding the hold output signal of the chopper type sample and hold circuit (2) DA converter characterized by.