JPH05313598A - AC drive type plasma display panel drive method - Google Patents
AC drive type plasma display panel drive methodInfo
- Publication number
- JPH05313598A JPH05313598A JP11738792A JP11738792A JPH05313598A JP H05313598 A JPH05313598 A JP H05313598A JP 11738792 A JP11738792 A JP 11738792A JP 11738792 A JP11738792 A JP 11738792A JP H05313598 A JPH05313598 A JP H05313598A
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- Prior art keywords
- discharge
- period
- wall charges
- common electrode
- address
- Prior art date
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Abstract
(57)【要約】
【目的】表示品質を向上させる。
【構成】１フレームを第１〜第８サブフィールドで構成
し、第１サブフィールドを、全面書込み期間と、全面消
去期間と、アドレス期間と、維持放電期間とで構成し、
第２〜第７サブフィールドの各々を、全面消去期間と、
アドレス期間と、維持放電期間とで構成する。
(57) [Summary] [Purpose] To improve display quality. [Structure] One frame is composed of first to eighth sub-fields, and the first sub-field is composed of a whole surface writing period, a whole surface erasing period, an address period, and a sustain discharge period,
In each of the second to seventh subfields, a full erase period,
It is composed of an address period and a sustain discharge period.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、交流駆動型プラズマデ
ィスプレイパネル駆動方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an AC drive type plasma display panel.
【０００２】[0002]
【従来の技術】図３は、交流駆動型プラズマディスプレ
イ装置の全体構成を示す。2. Description of the Related Art FIG. 3 shows the overall structure of an AC drive type plasma display device.
【０００３】交流駆動型プラズマディスプレイパネル１
０は、その一方の面に、互いに平行な走査電極Ｙ１〜Ｙ
ｎ及び共通電極Ｘが設けられ、対向面にこれら電極と直
角な方向にアドレス電極Ａ１〜Ａｎが設けられている。
共通電極Ｘは、各走査電極Ｙ１〜Ｙｎに対応してこれに
接近して設けられ、一端が互いに共通に接続されてい
る。AC drive type plasma display panel 1
Reference numeral 0 denotes scan electrodes Y1 to Y parallel to each other on one surface thereof.
n and a common electrode X are provided, and address electrodes A1 to An are provided on opposing surfaces in a direction perpendicular to these electrodes.
The common electrode X is provided corresponding to each of the scan electrodes Y1 to Yn and close to the scan electrodes Y1 to Yn, and one ends thereof are commonly connected to each other.
【０００４】図４は、１画素である、第ｉ行第ｊ列のセ
ルＣｉｊの断面構成を示す。共通電極Ｘ及び走査電極Ｙ
ｉはガラス基板１１上に形成され、その上に、放電空間
１７に対し絶縁するための誘電体層１２が被着され、さ
らにその上にＭｇＯ保護膜１３が被着されている。一
方、アドレス電極Ａｉは、ガラス基板１１と対向配置さ
れたガラス基板１４上に形成され、その上に蛍光体１５
が被着されている。また、ガラス基板１４及びアドレス
電極Ａｉ上には、画素境界に、セル間混色防止用及び放
電ギャップ維持用のセパレータ１６が形成されている。
ＭｇＯ保護膜１３と蛍光体１５との間の放電空間１７に
は、Ｎｅ＋Ｘｅペニングガスが封入されている。FIG. 4 shows a cross-sectional structure of a cell Cij of one pixel, i-th row and j-th column. Common electrode X and scan electrode Y
i is formed on a glass substrate 11, a dielectric layer 12 for insulating the discharge space 17 is deposited thereon, and a MgO protective film 13 is further deposited thereon. On the other hand, the address electrode Ai is formed on the glass substrate 14 arranged to face the glass substrate 11, and the phosphor 15 is formed thereon.
Is being worn. Further, on the glass substrate 14 and the address electrode Ai, a separator 16 for preventing inter-cell color mixing and maintaining a discharge gap is formed at a pixel boundary.
The discharge space 17 between the MgO protective film 13 and the phosphor 15 is filled with Ne + Xe Penning gas.
【０００５】図３において、共通電極ＸはＸドライバ２
０の出力端に接続され、走査電極Ｙ１〜ＹｎはＹドライ
バ３０の出力端に接続され、アドレス電極Ａ１〜Ａｍは
アドレスドライバ４０の出力端に接続されている。これ
らＸドライバ２０、Ｙドライバ３０及びアドレスドライ
バ４０は制御回路５０からの制御信号により制御され、
制御回路５０は、外部からの表示データＤ、表示データ
Ｄの読込みタイミングを示すクロックＣＬＫ、水平同期
信号ＨＳ及び垂直同期信号ＶＳに基づいてこの制御信号
を生成する。In FIG. 3, the common electrode X is an X driver 2
0, the scan electrodes Y1 to Yn are connected to the output end of the Y driver 30, and the address electrodes A1 to Am are connected to the output end of the address driver 40. These X driver 20, Y driver 30, and address driver 40 are controlled by control signals from the control circuit 50,
The control circuit 50 generates this control signal based on the display data D from the outside, the clock CLK indicating the read timing of the display data D, the horizontal synchronization signal HS, and the vertical synchronization signal VS.
【０００６】図５は、交流駆動型プラズマディスプレイ
パネルの駆動方法の一例を示す電圧波形図であり、１サ
ブフィールド分を示している。この１サブフィールド
は、全面書込み期間と、全面消去期間と、アドレス期間
と、維持放電期間とに区分される。FIG. 5 is a voltage waveform diagram showing an example of a driving method of an AC drive type plasma display panel, showing one subfield. This one subfield is divided into a full write period, a full erase period, an address period, and a sustain discharge period.
【０００７】２N 階調表示を行う場合、１フレームをＮ
個のサブフィールドで構成し、各サブフィールドを前記
４つの期間で構成し、第１〜Ｎサブフィールドでの維持
放電期間の比を２0 ：２1 ：・・・：２N-2：２N-1とす
る（特願平２−３３１５８９号）。図６は、Ｎ＝８の場
合の１フレームの各サブフィールドの構成を示す。When performing 2 N gradation display, one frame is N
Composed of subfields, each subfield is composed of the four periods, the ratio of the sustain discharge period in the first 1~N subfield 2 0: 2 1: ···: 2 N-2: 2 N-1 (Japanese Patent Application No. 2-331589). FIG. 6 shows the structure of each subfield of one frame when N = 8.
【０００８】[0008]
【発明が解決しようとする課題】しかし、１フレーム内
の各サブフィールドで全面書込み及び全面消去を行うの
で、全面消去状態の表示を行う場合でも各サブフィール
ドにおいて本駆動波形では４回放電発光し、例えばＮ＝
８の場合には１フレームで３２回も放電発光する為、全
面消去、すなわち全面黒の表示のときでも、灰色にな
り、高品位表示を阻害する原因となっていた。However, since full writing and full erasing are performed in each sub-field within one frame, even when displaying the full-erased state, discharge is emitted four times with the main drive waveform in each sub-field. , For example N =
In the case of No. 8, since discharge light emission is performed 32 times in one frame, even when the entire surface is erased, that is, the entire surface is displayed in black, it becomes gray, which is a cause of hindering high-quality display.
【０００９】本発明の目的は、このような問題点に鑑
み、表示品質を向上させることができる交流駆動型プラ
ズマディスプレイパネル駆動方法を提供することにあ
る。In view of the above problems, an object of the present invention is to provide an AC drive type plasma display panel driving method capable of improving display quality.
【００１０】[0010]
【課題を解決するための手段及びその作用】本発明に係
る交流駆動型プラズマディスプレイパネル駆動方法を、
図面を参照して説明する。[Means for Solving the Problems and Its Actions] An AC drive type plasma display panel driving method according to the present invention,
A description will be given with reference to the drawings.
【００１１】本発明は、例えば図３に示すようなプラズ
マディスプレイパネル１０を駆動する方法であり、この
プラズマディスプレイパネル１０は、互いに平行に敷設
された複数の走査電極Ｙ１〜Ｙｎと、走査電極Ｙ１〜Ｙ
ｎの各々に対し平行に敷設されかつ一端が互いに共通に
接続された共通電極Ｘと、走査電極Ｙ１〜Ｙｎ及び共通
電極Ｘと離間しかつクロスして互いに平行に敷設された
アドレス電極Ａ１〜Ａｍと、走査電極Ｙ１〜Ｙｎ及び共
通電極Ｘのアドレス電極Ａ１〜Ａｍ側を被った図４に示
すような壁電荷生成用誘電体層１２とを備えている。The present invention is a method for driving a plasma display panel 10 as shown in FIG. 3, for example. The plasma display panel 10 has a plurality of scan electrodes Y1 to Yn laid in parallel with each other and a scan electrode Y1. ~ Y
A common electrode X, which is laid in parallel with each of n, and has one end commonly connected to each other, and address electrodes A1 to Am, which are laid apart in parallel with the scanning electrodes Y1 to Yn and the common electrode X so as to be separated from each other and cross. And the wall charge generating dielectric layer 12 as shown in FIG. 4 covering the scan electrodes Y1 to Yn and the address electrodes A1 to Am of the common electrode X.
【００１２】本発明では、例えば図１及び図２に示す如
く、１フレームをＮ個（図１ではＮ＝８）のサブフィー
ルドで構成し、Ｎ個の該サブフィールドのうち少なくと
も１個のサブフィールドを、（１）共通電極Ｘと全ての
走査電極Ｙ１〜Ｙｎとの間に放電開始電圧よりも高い書
込み電圧のパルスを印加して全画素を放電発光させ壁電
荷を生成させる全面書込み期間と、（２）共通電極Ｘと
全ての走査電極Ｙ１〜Ｙｎとの間に該放電開始電圧より
も低い消去電圧かつ直前の放電で生じた壁電荷と同一極
性のパルスを印加して全画素を放電発光させることによ
り該壁電荷を消去させる全面消去期間と、（３）点灯さ
せようとする画素でクロスする該アドレス電極Ａｊと走
査電極Ｙｉとの間に該放電開始電圧よりも低い選択書込
み電圧のパルスを印加して該画素を放電発光させ壁電荷
を生成させるアドレス期間と、（４）共通電極Ｘと全て
の走査電極Ｙ１〜Ｙｎとの間に放電開始電圧よりも低い
維持電圧かつ直前の放電で生じた壁電荷と同一極性のパ
ルスを印加して該アドレス期間で選択的に書込みした画
素を放電発光させ壁電荷を生成させる維持放電期間とで
構成し、Ｎ個の該サブフィールドのうち残りのＮ−１個
のサブフィールドの各々を、（１’）共通電極Ｘと全て
の走査電極Ｙ１〜Ｙｎとの間に該放電開始電圧よりも低
い消去電圧かつ直前の放電で生じた該壁電荷と同一極性
のパルスを印加して該壁電荷が在る画素を放電発光させ
ることにより該壁電荷を消去させる消去期間と、
（２’）該アドレス期間と、（３’）該維持放電期間と
で構成し、該第１〜第Ｎサブフィールドの各維持放電期
間の長さを互いに異ならせることにより２N 階調表示さ
せる。In the present invention, for example, as shown in FIGS. 1 and 2, one frame is composed of N subfields (N = 8 in FIG. 1), and at least one subfield of the N subfields is formed. A field is (1) a full writing period in which a pulse of a writing voltage higher than the discharge start voltage is applied between the common electrode X and all the scanning electrodes Y1 to Yn to discharge all the pixels to emit light and generate wall charges. (2) Discharge all pixels by applying a pulse between the common electrode X and all the scan electrodes Y1 to Yn that has an erase voltage lower than the discharge start voltage and the same polarity as the wall charges generated by the immediately preceding discharge. A full erase period in which the wall charges are erased by emitting light, and (3) a selective write voltage lower than the discharge start voltage is applied between the address electrode Aj and the scan electrode Yi crossing in the pixel to be turned on. Pulse In addition, an address period in which the pixel is discharged for light emission to generate wall charges, and (4) a sustain voltage lower than the discharge start voltage and a previous discharge between the common electrode X and all the scan electrodes Y1 to Yn are generated. And a sustain discharge period in which a pixel having been selectively written in the address period is discharged to generate wall charges by applying a pulse having the same polarity as the wall charges. -1) Each of the sub-fields has the same (1 ') erase voltage lower than the discharge start voltage between the common electrode X and all the scan electrodes Y1 to Yn and the same wall charge generated by the previous discharge. An erasing period in which the wall charges are erased by applying a pulse of polarity to discharge and emit pixels having the wall charges.
(2 ′) The address period and (3 ′) the sustain discharge period, and the lengths of the sustain discharge periods of the first to N-th subfields are made different from each other to display 2 N gray scales. .
【００１３】本発明では、１フレーム内の１個のサブフ
ィールドにおいてのみ全面書込みを行っているので、全
面消去の表示を行う場合、例えばＮ＝８では１フレーム
で４＋３×７＝２５回放電発光し、全面消去時の放電発
光回数が従来の３２回よりも少なくなって、表示品質が
向上する。According to the present invention, the entire area is written only in one sub-field in one frame. Therefore, when displaying the entire area is erased, for example, when N = 8, 4 + 3 × 7 = 25 discharge light emission in one frame. However, the number of discharge light emission at the time of erasing the entire surface is less than the conventional 32 times, and the display quality is improved.
【００１４】本発明の第１態様では、全面消去期間を有
する上記１個のサブフィールドは、１フレームの最初の
サブフィールドである。In the first aspect of the present invention, the one subfield having the entire erase period is the first subfield of one frame.
【００１５】なお、共通電極は、複数組に分割されてい
てもよい。The common electrode may be divided into a plurality of sets.
【００１６】[0016]
【実施例】以下、図面に基づいて本発明の一実施例を説
明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
【００１７】例えば２５６階調表示を行う場合、図６に
対応して図１に示す如く、１フレームを第１〜８サブフ
ィールドで構成する。第１サブフィールドは、全面書込
み期間と、全面消去期間と、アドレス期間と、維持放電
期間とからなる。第２〜８サブフィールドはいずれも、
第１サブフィールドの全面書込み期間を除いたもの、す
なわち、全面消去期間と、アドレス期間と、維持放電期
間とからなる。For example, when displaying 256 gradations, one frame is composed of the first to eighth subfields as shown in FIG. 1 corresponding to FIG. The first subfield includes a full write period, a full erase period, an address period, and a sustain discharge period. The second to eighth subfields are all
The first subfield is formed by excluding the entire-area writing period, that is, an entire-erasing period, an address period, and a sustain discharge period.
【００１８】第１〜８サブフィールドの各維持放電期間
ｔ１〜ｔ８の比は図６と同様に、 ｔ１：ｔ２：ｔ３：・・・：ｔ７：ｔ８ ＝１：２：４：８：１６：３２：６４：１２８ となっている。The ratio of the sustain discharge periods t1 to t8 of the first to eighth subfields is t1: t2: t3: ...: t7: t8 = 1: 2: 4: 8: 16: It is 32: 64: 128.
【００１９】１フレーム時間は図６の場合と等しく、１
／６０秒である。したがって、本実施例では図６の場合
よりも（全面書込み期間）×７の時間だけ他の期間で使
用でき、パルス幅を図６の場合よりも広くすることがで
きる。One frame time is equal to that in FIG.
/ 60 seconds. Therefore, in the present embodiment, the pulse width can be made wider than in the case of FIG. 6 by being used for another period of time (total writing period) × 7.
【００２０】図２は、第１及び第２のサブフィールドに
おいて、アドレス電極Ａ１〜Ａ４８０、共通電極Ｘ及び
走査電極Ｙ１〜Ｙ４８０に印加される電圧の波形を示
す。第１サブフィールドの電圧波形は図５と同一であ
り、以下にこれを説明する。なお、図中のサブフィール
ド区分信号は、図３の制御回路５０で生成される。FIG. 2 shows waveforms of voltages applied to the address electrodes A1 to A480, the common electrode X, and the scan electrodes Y1 to Y480 in the first and second subfields. The voltage waveform of the first subfield is the same as that of FIG. 5, which will be described below. The subfield division signal in the figure is generated by the control circuit 50 in FIG.
【００２１】（１）全面書込み期間 最初の全面書込み期間では、走査電極Ｙ１〜Ｙｎがグラ
ンドレベルＧＮＤにされ、この状態で共通電極Ｘが、放
電開始電圧Ｖf よりも高い書込み電圧ＶWにされて（全
面書き込みパルス）、共通電極Ｘと走査電極Ｙ１〜Ｙｎ
との間で、すなわち全セルで、書込み放電が行われる。
放電が進むにつれ、共通電極Ｘ電極上の誘電体層１２に
は負の壁電荷が蓄積され、走査電極Ｙ１〜Ｙｎ上の誘電
体層１２には正の壁電荷が蓄積される。この壁電荷は放
電空間の電圧を低減させるため、１μｓ程度で放電が終
結する。(1) Whole Area Write Period In the first whole area write period, the scan electrodes Y1 to Yn are set to the ground level GND, and in this state, the common electrode X is set to the write voltage V W higher than the discharge start voltage V f. (Entire write pulse), common electrode X and scan electrodes Y1 to Yn
And, that is, in all cells, address discharge is performed.
As the discharge progresses, negative wall charges are accumulated in the dielectric layer 12 on the common electrode X electrode, and positive wall charges are accumulated in the dielectric layer 12 on the scan electrodes Y1 to Yn. The wall charges reduce the voltage in the discharge space, so that the discharge ends in about 1 μs.
【００２２】次に、走査電極Ｙ１〜Ｙｎが、放電開始電
圧Ｖf よりも低い維持電圧ＶSにされ、共通電極Ｘがグ
ランドレベルＧＮＤにされ（維持パルス）、これに前記
壁電荷による電圧が加算されて、共通電極Ｘと走査電極
Ｙ１〜Ｙｎとの間で維持放電が行われる。これにより、
共通電極Ｘ電極上の誘電体層１２には正の壁電荷が蓄積
され、走査電極Ｙ１〜Ｙｎ上の誘電体層１２には負の壁
電荷が蓄積されて、放電が終了する。この維持パルスに
より、壁電荷が安定化される。Next, the scan electrodes Y1 to Yn are set to the sustain voltage V S lower than the discharge start voltage V f , the common electrode X is set to the ground level GND (sustain pulse), and the voltage due to the wall charges is applied thereto. After being added, the sustain discharge is generated between the common electrode X and the scan electrodes Y1 to Yn. This allows
Positive wall charges are accumulated in the dielectric layer 12 on the common electrode X electrode, and negative wall charges are accumulated in the dielectric layer 12 on the scan electrodes Y1 to Yn, and the discharge ends. This sustain pulse stabilizes the wall charge.
【００２３】（２）全面消去期間 次に、共通電極Ｘが維持電圧ＶSにされ、走査電極Ｙ１
〜ＹｎがグランドレベルＧＮＤにされて（全面消去パル
ス）、消去放電が生じ、壁電荷が中和されて消去され
る。この消去方法には、放電の進行段階でパルスを中断
させる細幅消去方法と、維持電圧ＶSより低い電圧で微
小な放電を生じさせる太幅消去方法とがある。(2) Full Erase Period Next, the common electrode X is set to the sustain voltage V S , and the scan electrode Y1
.About.Yn are set to the ground level GND (whole surface erase pulse), erase discharge occurs, wall charges are neutralized and erased. This erasing method includes a narrow width erasing method in which a pulse is interrupted in the progress stage of discharge and a wide width erasing method in which a minute discharge is generated at a voltage lower than the sustain voltage V S.
【００２４】（３）アドレス期間 次に、表示データの書込みが線順次に行われる。すなわ
ち、まず走査電極Ｙ１がグランドレベルＧＮＤにされて
選択され、第１表示行の点灯しようとするセルに対応し
たアドレス電極に電圧Ｖａが印加されて（書込みパル
ス）、両電極間で書込み放電が行われ、壁電荷が生成さ
れる。以下、第２〜ｎ表示行についてこの順に、上記同
様の動作が行われる。(3) Address period Next, display data is written line-sequentially. That is, first, the scan electrode Y1 is set to the ground level GND and selected, the voltage Va is applied to the address electrode corresponding to the cell to be lit in the first display row (writing pulse), and the writing discharge is generated between both electrodes. Is performed and wall charges are generated. Hereinafter, the same operation as above is performed in this order for the second to nth display rows.
【００２５】（４）維持放電期間 次に、走査電極Ｙ１〜Ｙｎが共に維持電圧ＶSの状態で
共通電極ＸがグランドレベルＧＮＤにされ（維持パル
ス）、アドレス期間で書込み放電を行なったセルにおい
て壁電荷が加算され、維持放電が行われる。次に、共通
電極Ｘを維持電圧ＶSに戻した状態で走査電極Ｙ１〜Ｙ
ｎが共にグランドレベルＧＮＤにされ（維持パルス）、
アドレス期間で書込み放電を行なったセルにおいて壁電
荷が加算され、維持放電が行われる。以下、このような
動作が交互に繰り返される。すなわち、共通電極Ｘと走
査電極Ｙ１〜Ｙｎとの間に交流維持パルスが供給され
て、画像が表示される。(4) Sustain Discharge Period Next, in the cells in which the common electrode X is set to the ground level GND (sustain pulse) while the scan electrodes Y1 to Yn are both at the sustain voltage V S , and the address discharge is performed in the address period. Wall charges are added and sustain discharge is performed. Next, with the common electrode X returned to the sustain voltage V S , the scan electrodes Y1 to Y
Both n are set to the ground level GND (sustain pulse),
Wall charges are added to the cells that have undergone address discharge in the address period, and sustain discharge is performed. Hereinafter, such an operation is alternately repeated. That is, an AC sustaining pulse is supplied between the common electrode X and the scan electrodes Y1 to Yn to display an image.
【００２６】第２サブフィールドは、第１サブフィール
ドでの全面書込み期間を省略し、維持放電期間を第１サ
ブフィールドのそれの２倍にしている。他は第１サブフ
ィールドと同一である。In the second sub-field, the entire write period in the first sub-field is omitted, and the sustain discharge period is twice as long as that in the first sub-field. Others are the same as the first subfield.
【００２７】第２サブフィールドの全面消去期間におい
ては、直前の維持放電で生成された壁電荷が、全面消去
放電により消失する。第３サブフィールド以下の全面消
去期間についても第２サブフィールドと同様である。In the full erase period of the second subfield, the wall charges generated by the immediately preceding sustain discharge disappear by the full erase discharge. The same applies to the second subfield for the entire erase period after the third subfield.
【００２８】本実施例では、１フレーム内の最初のサブ
フィールドにおいてのみ全面書込みを行っているので、
全面消去の表示を行う場合、１フレームで４＋３×７＝
２５回放電発光し、放電発光回数が従来の３２回よりも
少なくなって、表示品質が向上する。In the present embodiment, since the entire surface writing is performed only in the first subfield within one frame,
When displaying the entire screen, 4 + 3 × 7 = in one frame
The discharge light emission is performed 25 times, the discharge light emission frequency is less than the conventional 32 times, and the display quality is improved.
【００２９】[0029]
【発明の効果】以上説明した如く、本発明に係る交流駆
動型プラズマディスプレイパネル駆動方法では、１フレ
ーム内の１個のサブフィールドにおいてのみ全面書込み
を行っているので、全面消去の表示を行う場合に放電発
光回数が従来よりも少なくなって、表示品質が向上する
という効果を奏する。As described above, in the AC driving type plasma display panel driving method according to the present invention, since the entire surface writing is performed only in one subfield within one frame, the case of performing the display of the entire erasing. In addition, the number of times of discharge light emission becomes smaller than that in the past, and the display quality is improved.
【図１】本発明の１実施例に係り、２５６諧調表示する
場合の１フレームの各サブフィールド構成図である。FIG. 1 is a diagram showing the configuration of each subfield of one frame when displaying 256 gradations according to an embodiment of the present invention.
【図２】第１及び第２のサブフィールドでの各電極に印
加される電圧波形図である。FIG. 2 is a voltage waveform diagram applied to each electrode in the first and second subfields.
【図３】交流駆動型プラズマディスプレイ装置の概略構
成図である。FIG. 3 is a schematic configuration diagram of an AC drive type plasma display device.
【図４】図３のセルの断面構成図である。4 is a cross-sectional configuration diagram of the cell of FIG.
【図５】従来例に係り、１サブフィールドでの各電極に
印加される電圧波形図である。FIG. 5 is a voltage waveform diagram applied to each electrode in one subfield according to a conventional example.
【図６】従来例に係り、２５６諧調表示する場合の１フ
レームの各サブフィールド構成図である。FIG. 6 is a configuration diagram of each subfield of one frame in a 256-tone display according to a conventional example.
Ａ１〜Ａｍ アドレス電極 Ｘ 共通電極 Ｙ１〜Ｙｎ 走査電極 A1 to Am Address electrodes X Common electrodes Y1 to Yn Scan electrodes
Claims (2)
（Ｙ１〜Ｙｎ）と、該走査電極の各々に対し平行に敷設
されかつ一端が互いに共通に接続された共通電極（Ｘ）
と、該走査電極及び該共通電極と離間しかつクロスして
互いに平行に敷設されたアドレス電極（Ａ１〜Ａｍ）
と、該走査電極及び該共通電極の該アドレス電極側を被
った壁電荷生成用誘電体層（１２）と、を備えたプラズ
マディスプレイパネル（１０）を駆動する交流駆動型プ
ラズマディスプレイパネル駆動方法において、 １フレームをＮ個のサブフィールドで構成し、 Ｎ個の該サブフィールドのうち少なくとも１個のサブフ
ィールドを、該共通電極と全ての該走査電極との間に放
電開始電圧よりも高い書込み電圧のパルスを印加して全
画素を放電発光させ壁電荷を生成させる全面書込み期間
と、該共通電極と全ての該走査電極との間に該放電開始
電圧よりも低い消去電圧かつ直前の放電で生じた壁電荷
と同一極性のパルスを印加して全画素を放電発光させる
ことにより該壁電荷を消去させる全面消去期間と、点灯
させようとする画素でクロスする該アドレス電極と該走
査電極との間に該放電開始電圧よりも低い選択書込み電
圧のパルスを印加して該画素を放電発光させ壁電荷を生
成させるアドレス期間と、該共通電極と全ての該走査電
極との間に放電開始電圧よりも低い維持電圧かつ直前の
放電で生じた壁電荷と同一極性のパルスを印加して該ア
ドレス期間で選択的に書込みした画素を放電発光させ壁
電荷を生成させる維持放電期間とで構成し、 Ｎ個の該サブフィールドのうち残りのＮ−１個のサブフ
ィールドの各々を、該共通電極と全ての該走査電極との
間に該放電開始電圧よりも低い消去電圧かつ直前の放電
で生じた壁電荷と同一極性のパルスを印加して該壁電荷
が在る画素を放電発光させることにより該壁電荷を消去
させる消去期間と、該アドレス期間と、該維持放電期間
とで構成し、 該第１〜第Ｎサブフィールドの各維持放電期間の長さを
互いに異ならせることにより２N 階調表示させることを
特徴とする交流駆動型プラズマディスプレイパネル駆動
方法。1. A plurality of scan electrodes (Y1 to Yn) laid parallel to each other, and a common electrode (X) laid parallel to each of the scan electrodes and having one ends commonly connected to each other.
And address electrodes (A1 to Am) laid apart in parallel with and crossing the scanning electrodes and the common electrode.
An AC drive type plasma display panel driving method for driving a plasma display panel (10) comprising: a wall charge generating dielectric layer (12) covering the scan electrode and the address electrode side of the common electrode. , 1 frame is composed of N subfields, and at least one subfield of the N subfields has a writing voltage higher than a discharge start voltage between the common electrode and all the scanning electrodes. Pulse is applied to cause all pixels to discharge and emit light to generate wall charges, and an erase voltage lower than the discharge start voltage and an immediately preceding discharge between the common electrode and all the scan electrodes. A pulse having the same polarity as the wall charges is applied to cause all pixels to discharge and emit light, thereby causing a full erase period in which the wall charges are erased and a pixel to be turned on cross. An address period in which a pulse of a selective write voltage lower than the discharge start voltage is applied between the address electrode and the scan electrode to cause the pixel to discharge and emit light to generate wall charges, and the common electrode and all the scan electrodes. A sustain voltage lower than the discharge start voltage and a pulse having the same polarity as the wall charges generated by the immediately preceding discharge are applied between the discharge voltage and And an erase voltage lower than the discharge start voltage between the common electrode and all the scan electrodes in each of the remaining N-1 subfields of the N subfields. An erasing period for erasing the wall charges by applying a pulse having the same polarity as that of the wall charges generated by the immediately preceding discharge to discharge and discharge the pixels having the wall charges, the address period, and the sustain discharge period. With And, AC-driven plasma display panel driving method characterized by displaying 2 N gray scale by varying the length of the sustain discharge period of said to N-th sub-field to each other.
フィールドは、前記１フレームの最初のサブフィールド
であることを特徴とする請求項１記載の交流駆動型プラ
ズマディスプレイパネル駆動方法。2. The AC drive type plasma display panel driving method as claimed in claim 1, wherein the one subfield having a full writing period is a first subfield of the one frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11738792A JP2756053B2 (en) | 1992-05-11 | 1992-05-11 | AC Drive Type Plasma Display Panel Driving Method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11738792A JP2756053B2 (en) | 1992-05-11 | 1992-05-11 | AC Drive Type Plasma Display Panel Driving Method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05313598A true JPH05313598A (en) | 1993-11-26 |
| JP2756053B2 JP2756053B2 (en) | 1998-05-25 |
Family
ID=14710393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11738792A Expired - Fee Related JP2756053B2 (en) | 1992-05-11 | 1992-05-11 | AC Drive Type Plasma Display Panel Driving Method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2756053B2 (en) |
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| US5854540A (en) * | 1996-06-18 | 1998-12-29 | Mitsubishi Denki Kabushiki Kaisha | Plasma display panel driving method and plasma display panel device therefor |
| US6034482A (en) * | 1996-11-12 | 2000-03-07 | Fujitsu Limited | Method and apparatus for driving plasma display panel |
| KR20000034677A (en) * | 1998-11-30 | 2000-06-26 | 김영남 | Plasma Display Panel Driving Method |
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| US5854540A (en) * | 1996-06-18 | 1998-12-29 | Mitsubishi Denki Kabushiki Kaisha | Plasma display panel driving method and plasma display panel device therefor |
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