JPH053144B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device, particularly a MIS type (insulated gate type) field effect semiconductor device (hereinafter referred to as μ channel MIS.FET) having a microchannel type, and a semiconductor device in which a capacitor is connected to the MIS type field effect semiconductor device. There are suggestions.

The present invention includes a first layer made of a semiconductor or conductor of the same or different conductivity type on the surface of a semiconductor substrate of one conductivity type, a dielectric layer on the layer, and a conductor or semiconductor on the dielectric layer. After forming the second layer, these layers are selectively etched to form a convex shape on the surface of the semiconductor substrate, and the convex L of the first region is etched.
The corner part of the mold is used to make the height approximately match the first area and the width approximately match the thickness of the coating to be formed at the corner. The purpose is to form a triangular layer (simply called a triangular shape) as a gate electrode.

Furthermore, in the present invention, the impurity region provided in the same shape on the first region or the upper part of the substrate in contact with the first region is used as a region constituting the source or drain, and the triangular layer is used as the gate electrode. A MIS.FET is constructed by providing a second region of the same conductivity type as the first region as a drain or source in the upper part of the semiconductor below the other end of the layer, and in addition, this first region or The present invention relates to a method for manufacturing a semiconductor device having a 1Tr/cell structure in which capacitors are simultaneously provided in a region of .

Conventionally, the structure of a MIS.FET and a capacitor connected in series thereto is as shown in FIG. A drain or source 14 constituting the lower electrode of the capacitor was provided, and its lead 9, a capacitor insulator 15, and a counter electrode 7 were also provided.

Conventionally, MIS.FET has always formed a pair of source and drain regions 13 and 14 under both ends of a gate insulator 11 on the same plane on a semiconductor substrate.

Furthermore, this gate electrode 6 has a gate insulator 11
It was provided not only on the top but also over the top surface of the counter electrode 7 of the capacitor. This has self-alignment with one end of the source or drain 13 under one end 16 of the gate electrode and the drain or source 14 under the other end 18 of the gate electrode. However, the other end 17 of the gate electrode that is actually made is made larger than 18 to compensate for variations in mask alignment accuracy.
It is. However, in such a case, the channel length is 1 μm.
The following is impossible due to the photo-etching process, and in particular, due to the unevenness at the step portion 18, it was impossible to shorten the channel length because pattern breakage would occur.

The present invention reversely utilizes this step to create MIS.FET
A gate electrode is provided, and this electrode is formed without extending over the opposing electrode of the capacitor.

In the present invention, the width corresponding to the channel length of the layer functioning as a gate electrode can be made extremely small to 0.1 to 1 μm, and the thickness is 0.5 to 1 μm, which is a thick triangular or vertical square shape. It has a longitudinally longer cross-sectional structure than the gate electrode.

In addition, since it is long in the vertical direction, its strength is not sufficient as it is. To compensate for this strength, a first region is therefore provided along this layer. In addition, on the semiconductor under this first region,
It is characterized in that it is configured as part or all of the source or drain of the MIS.FET, and that a capacitor made of a layered insulator and conductor (semiconductor) is provided inside this region in series with the source or drain.

Therefore, the purpose of the semiconductor device of the present invention is to achieve high density for configuring its elements by proactively providing them in the height direction, instead of reducing the conventional lateral area by scaling. There is.

Examples of the present invention will be described below with reference to the drawings.

Example 1 FIG. 2 shows another embodiment of the invention.

That is, a semiconductor substrate 1 having a P-type conductivity is subjected to plasma nitriding at 800 to 1200°C, and a silicon nitride film with a thickness of 50 to 250 Å is first formed on the surface.
It was selectively removed with a buffer etchant by photolithography using a photomask. Furthermore, only the removed area is 5 to 15
The field insulating film 2 is heated and oxidized at 600 to 1100°C in steam pressurized to a thickness of 0.3 to 2 μm.
It was buried and formed to a thickness of . In addition, in order to flatten the top surface of this field insulator, 30 to 50
% Chemically, the nitride serving as a mask may be removed using a buffer etchant and a portion of the mask may be removed at the same time.

After this, in FIG. 2A, a first layer is placed on the semiconductor substrate 1 over the field insulator 2 on the right side.
formed an area of

In other words, this first region has 0.05~
A first layer 30 of semiconductor doped with a highly concentrated impurity of N-type conductivity to a thickness of 0.2 μm is further laminated on top of the first layer 30 of tantalum oxide, silicon nitride, titanium oxide, or a ferroelectric film. dielectric layer 31
was formed, and a second layer made of a conductor or semiconductor was formed as a counter electrode 32 on the upper surface thereof.

The height of this first region 3 is 0.5 to 2.5 μm,
The total area was determined based on the capacitance required in the design. The present invention is characterized in that the contact area with the semiconductor 1 is small in order to eliminate parasitic capacitance with the substrate, and a capacitor is provided across the field insulator.

Furthermore, by known photolithography,
The edges around that side were selectively removed while being careful not to side-etch so that vertical edge sides were exposed, leaving the first region 3. for example
Etching was performed by vertically applying a fluorine-based gas (for example, NF ₃ or CF ₄ ) to the substrate from above at a pressure of 0.001 to 0.1 torr, which was excited by a 2.45 GHz microwave. As a result, the side periphery is 85~85mm relative to the board surface.
I was able to make a clean cut almost perpendicular to 90 degrees. Thus, the dielectric layer 31, electrode 30, and counter electrode 32 of the capacitor all have the same shape, with the convex first
We were able to configure the following areas.

Further, the first layer and the second layer constituting the first region are not made of silicon doped with impurities, but are made of an intrinsic or multilayer film of an intrinsic semiconductor and a P or N type semiconductor, or a metal or a metal compound.
It may be Mo, W or a silicide thereof (Mo ₂ Si, W ₂ Si).

In addition, in order to provide this dielectric layer 31, the first layer 30 is made into a semiconductor layer, and oxygen or nitrogen is added at a high concentration to a predetermined portion from the upper surface of the first layer 30 to form an insulating film (dielectric layer) of silicon oxide or silicon nitride. may be formed.

In FIG. 2B, the upper surfaces of semiconductor substrate 1 and first region 3 were further oxidized or nitrided to form insulating film 4. In FIG. Of course, this insulating film 4 may be formed by a vapor phase method or a vacuum evaporation method. Further, if the first region 3 is a semiconductor or a conductor of a different type from the substrate, it will be an oxide or nitride of the semiconductor or a conductor, and it goes without saying that the first region 3 will be an insulating film of a different type from the insulating film on the surface of the substrate.

Furthermore, in FIG. 2B, the openings 41 and 42 are
A semiconductor or conductor film 5 for forming a triangular layer 6 was formed thereon. Thereafter, a second region 13 is formed by ion implantation using the side peripheral portion 8 of this coating 5.
was injected into the underlying substrate through this coating 5. This region was made to have the same conductivity type as the first layer 30.

Next, using anodic oxidation or selective oxidation, the remaining portions except for the electrodes/leads 9 and 45 were selectively oxidized vertically using a fourth photomask or photoresist to form an insulator 44 such as silicon oxide. At this time, triangular layers 6 and 8' are formed around the side of the first region 3. This layer 6 was then made to function as a gate electrode, and the other layer 8' was again oxidized and eliminated using the fifth photolithography technique. In the mask process, the gate electrode 6
At the same time, the leads 6, 9, and contacts 45 can be made to connect the gates, sources, and drains of other MIS.FETs on the same substrate.

Thus, as shown in FIG. 2C, the second region 13 and the first
The diffusion layer 14 below the region 3 may be formed by heat treatment. Then, a μ-channel MIS.FET could be manufactured in which the respective regions 13 and 14 or 3 were used as the source and drain, or the drain or the source, and the triangular layer 6 was used as the gate electrode.

In FIG. 2D, the third lead 10 is provided using a photomask using the interlayer insulator 36.

This MIS.FET uses the minority carriers of the substrate N13-P (channel forming area under the gate electrode) -
It had the structure N14 or 3.

However, N13- using multiple carriers on the board
N (channel formation region under gate electrode 6) - N14
Or it may be 3.

Alternatively, a C/MIS.FET structure may be used in which a plurality of C/MIS.FETs are provided relative to each other.

Furthermore, since the leads 5 and 9 were provided on the field insulator 2, it was extremely easy to integrate a plurality of MIS.FETs.

Assuming that FIG. 2E is an electrically equivalent circuit of FIG. , an upper counter electrode 32, and a dielectric layer 31, and this lower electrode is a μ-channel MIS.
By using the FET source or drain, it was possible to create a high-density memory cell (1Tr/cell).

Further, when mask aligning the first region using a photomask, most of the first region can be provided over the upper surface of the field insulator 2. Therefore, the width of the region where the diffusion layer 14 exists which can be substantially formed under the first region 3 is set to 0.3 to 3 μm.
It can be made extremely narrow.

Therefore, the parasitic capacitance between the layer 14 and the substrate could be extremely reduced. Furthermore, the gate electrode 6 and the source or drain 13 can be manufactured without any special process, and the electrodes and leads 5 and 9 can also be manufactured at the same time.
Further, on this upper surface, fifth and sixth electrodes are placed on the interlayer insulator 36
Photo etching can be performed using the photomasks 5 and 6, two-layer wiring can be performed in the X and Y directions,
A further feature is that only seven types of masks are required.

Example 2 FIG. 3 shows another embodiment of the invention.

FIG. 3 shows a further development of the second embodiment. That is, a second region 13 and a pair of first regions 3, 3' are provided symmetrically thereto.

A part of the region shown in FIG. 1 is provided over the field insulator 2, and the μ-channel MIS.FET is connected to the capacitor via the source or drain 13, gates 6, 6', drain or source 14, 14'. A first layer 30, 30' for the lower electrode, a dielectric layer 31, 31', a second layer 32 for the upper counter electrode,
32' was provided. 13,9 in the drawing
is a bit line, and 6 and 6' are word lines.
This is part of a memory system that has a structure in which two 1Tr/cells form a pair. With such a structure, the second region can be shared, and the dielectric layer 3
1 and 31' have a feature that a material having a high dielectric constant different from that of the gate insulating film, such as tantalum oxide or barium titanate, can be used.

In this embodiment, it is important to fabricate the gate electrodes 6, 6' not by the conventional etching method using a solution, but by using an etching method with very few side etches and taper etches, or which is unsatisfactory. in particular
Reactive gases for etching, such as silicon fluoride (NF ₃ ) and CF ₄ , are chemically activated by microwaves using 2.45 GHz, and the degree of vacuum is increased from 0.1 to
An attempt was made to completely eliminate side etching by flowing a fluorine shower made into plasma in a vacuum atmosphere of 0.001 torr, particularly 0.005 to 0.01 torr, in a vertical direction from the top surface of the substrate.

Furthermore, the outer periphery of the triangularly etched layer 6 is insulated by its oxide insulator 24. The thickness of this oxide is 0.01 ~
Further, an interlayer insulator 36 such as polyimide was formed on the outside thereof, and a third conductor was formed on the upper surface thereof.

All of the above embodiments are aimed at producing a 1Tr/cell RAM. However, in all of the processes of the present invention, μ-channel MIS.
can be formed without adding any extra photomask. This made it extremely convenient for creating memory systems or logic systems.

Further, the lower electrode, the upper electrode, and the first region of the capacitor may all be formed of a silicon family made of the same main component as the substrate to improve reliability. Further, in the second embodiment, leads such as A1 may be formed in multiple layers on the upper side with an interlayer insulator interposed therebetween.

In the present invention, a floating gate type nonvolatile memory may be constructed by electrically floating the gate electrode.

In the above embodiments, the material constituting the first region or the material constituting the triangular layer 6 is a material having the same main component as the substrate doped with impurities having P or N type conductivity, for example, silicon. It was marked as the center.

However, they may also be mixtures or compounds of silicon with Mo and W (Mo ₂ Si, W ₂ Si), and may also be multilayered structures of intrinsic, P-type or N-type semiconductors, or semiconductors such as silicon. Needless to say, it may have a multilayer structure of Mo, W, platinum, or a compound thereof.

Furthermore, the semiconductor substrate is made of single crystal silicon. but
It goes without saying that it may be a compound semiconductor such as GaAs or InP, or a polycrystalline, amorphous, or semi-amorphous semiconductor.

As is clear from the above embodiments, the present invention does not have a conventional structure in which a pair of sources and drains are separated from each other by a gate electrode, but the details thereof lean toward the first region that can constitute the source or drain. In this way, the gate electrode was mechanically reinforced, and its source or drain was provided on the semiconductor substrate. In addition, the other source and drain have a structure in which they are provided on the top of the semiconductor approximately in line with one end of the gate, and in addition to having this structural feature, the frequency response speed of 0.1 to 1μ is 1 to 10GHz. An extremely short channel (μ
A major feature is that MIS.FET can be implemented without using techniques such as electron beam exposure as an absolute requirement.

[Brief explanation of the drawing]

FIG. 1 shows a vertical cross-sectional view of a conventionally known MIS.FET. FIGS. 2 and 3 are longitudinal sectional views showing the manufacturing process and structure of an embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A step of forming a convex first region on one surface of a substrate having a semiconductor surface, and forming an L-shaped corner portion by the first region and the substrate surface;
a step of forming a layer made of a conductor or semiconductor covering the corner portion, and selectively oxidizing the layer to form a triangular or angular layer in the corner portion; A method for manufacturing a semiconductor device, comprising the step of converting a material other than the material into an oxide insulator. 2. Forming a first layer of a conductor or semiconductor on one surface of a substrate having a semiconductor surface, a dielectric layer on the layer, and a second layer of the conductor or semiconductor on the dielectric layer; selectively removing the layer to form a convex first region, forming an L-shaped corner portion by the first region and the substrate surface; a step of forming an insulating film to cover the region; a step of forming a layer made of a conductor or a semiconductor to cover the insulating film;
a step of selectively oxidizing the layer to form a triangular or angular layer in the corner portion and converting layers other than the triangular or angular layer into an oxide insulator; A method for manufacturing a semiconductor device, comprising the step of: forming the second region as a source or a drain on the semiconductor above the semiconductor so as to be spaced apart from each other and substantially coincident with one end of the electrode.