JPH0550855B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device, and particularly to a dynamic memory having excellent characteristics by increasing the capacity of a memory capacitor.

[Prior art and its problems]

BACKGROUND ART Conventionally, a so-called one-transistor/one-capacitor type memory cell, in which a memory cell is formed from one transistor and one capacitor, has been widely used because a large-capacity semiconductor memory can be easily formed. An example of this is shown in FIG. 1 as a plan view (FIG. 1a) and a sectional view taken along line a-a' (FIG. 1b).

That is, charge is accumulated in the capacitance formed by the gate electrode 102 and the semiconductor substrate provided through the gate insulating film 101, and this charge is used to turn on the switching transistor 103.
When set to "off", the extraction information is recognized on the bit line.

Therefore, in order to increase the noise margin of the signal and increase the reliability of operation, it is absolutely necessary to increase the capacity of the memory capacitor 104.

However, as the degree of integration of memories increases, memory cells become smaller and smaller, making it difficult to obtain sufficient capacitance with the conventional planar memory capacitor structure.

Therefore, a method has been proposed in which a trench is formed in a silicon substrate and an insulating film is provided also in this trench to increase the memory capacitance. As shown in Figure 2a, first a groove with a rectangular opening is formed in the capacitor formation area of the element formation area, and a thin oxide film is formed by thermal oxidation in the capacitor formation area including the inner wall of this groove. and form a capacitor. As a result, the capacitance of the capacitor increases by the side wall portion of the trench, which has a great effect on improving the capacitance of dynamic memory cells that are becoming smaller.

However, in this method, when the trench is oxidized, as shown in b, the thickness of the oxide film at the corner of the trench bottom surface, tox ₂ , is thinner than the thickness of the oxide film 201 on the side wall of the trench, tox ₁ , and as a result, the oxide film of the capacitor is There were serious problems such as a significant deterioration in breakdown voltage and a significant decrease in the yield of memory cells.

[Purpose of the invention]

The present invention has been made in view of the above points,
In particular, by bringing the dielectric strength voltage of the trench capacitor close to that of the planar capacitor, a semiconductor device with excellent device characteristics, yield, and reliability is provided.

[Summary of the invention]

That is, in order to achieve the above object, the present invention
The angle formed by all two adjacent sides of the groove constituting the capacitor at the opening is greater than 90 degrees,
The present invention is a semiconductor device in which an opening is formed to have a polygonal shape of at least a pentagon or more.

〔Effect of the invention〕

According to the present invention, since the angle of the corner of the bottom surface of the groove constituting the capacitor can be made larger than a right angle, when a thermal oxide film is formed, the thickness of the oxide film at the corner does not become extremely thin. The withstand voltage of the oxide film approaches that of a planar capacitor, significantly improving device reliability and increasing product yield.

[Embodiments of the invention]

The manufacturing process for forming an embodiment of the present invention will be described below with reference to FIGS. 3a to 3e. As shown in FIG. 3A, a field oxide film 302 for element isolation is formed on a P-type silicon substrate 301 to a thickness of, for example, 1 μm, and then a thermal oxide film 303 is formed on the surface of the silicon substrate 301 to a thickness of, for example, 1000 Å. Next, the memory capacitor forming area except for the area where the groove is to be formed is covered with a resist 304. At this time, the shape of the groove-forming opening without resist becomes a polygon, such as a regular octagon, in which the angle formed by each adjacent side is greater than 90 degrees. This resist 304
The thermal oxide film 303 on the surface of the silicon substrate 301 is removed by etching with, for example, NH ₄ F using as a mask to expose the silicon surface 305.

Next, as shown in FIG. 3B, after removing the resist 304, the silicon substrate 301 is etched by reactive ion etching using, for example, Cl ₂ and H ₂ gases, using the thermal oxide film 303 as a mask. The etching depth of the silicon substrate is, for example, 2
Double it. Next, after removing the damaged layer when the substrate was etched, for example, As is diffused to form an N-type impurity layer 307 in the region where silicon is exposed on the sides and bottom of the trench.

Next, as shown in FIG. 3c, a resist 308 is covered except for the capacitor formation portion, and the thermal oxide film 303 is etched away using this as a mask. Next, using the resist 308 as a mask, ions of, for example, As are implanted to form an N-type impurity layer 309 that will become the lower electrode of the capacitor section.

Next, as shown in FIG. 3d, after removing the resist 308, the exposed silicon surface is treated with, for example, O ₂
A thermal oxide film 310 having a thickness of, for example, about 100 Å is formed by thermally oxidizing it in an atmosphere diluted with Ar gas. At this time, as shown in FIG. 4b, the thermal oxide film 31
0 does not become extremely thin. Next, a gate electrode 311 that will become a capacitor is formed using a gate electrode material such as polysilicon doped with phosphorus, and then thermal oxide films 310 and 303 are formed.
After removing the gate oxide film 3, the gate oxide film 3 is again thermally oxidized.
12, and also forms a gate electrode 313, a source,
A drain 314 and the like are formed (FIG. 3e).

As explained above, according to the present invention, the angle θ in FIG. 2a can be made larger than 90 degrees, and as a result, as shown in FIG. 2b, an extreme difference in film thickness at the bottom corner portion does not occur. That is, as shown in FIG. 4b, an oxide film is formed at the bottom corner. As a result, the oxide film breakdown voltage of the capacitor approaches the oxide film breakdown voltage of the planar capacitor (FIG. 1), and the reliability of the device is significantly improved compared to the conventional method, resulting in improved product yield.

In this embodiment, a P-type substrate is used, but an N-type substrate may also be used, in which case the impurity layer will be of the opposite P-type. In addition, as a method for forming a thin oxide film on the silicon surface, a dry method other than the method described in this example can be used.
In addition to O ₂ oxidation, HCl oxidation, and wet oxidation, so-called oxidation methods may also be used.

Furthermore, after oxidizing the trench, a silicon nitride film of about 50 Å may be deposited by, for example, vapor phase growth, and a multilayer film may be used as the insulating film of the capacitor.

Furthermore, as shown in Figure 5, by making the bottom of the groove polygonal rather than flat, the uniformity of the oxide film at the bottom of the groove is increased, which further improves device reliability and improves product yield. It is clear from the results of the present invention that the results are significantly improved.

[Brief explanation of the drawing]

FIGS. 1a and 1b are plan views illustrating a dynamic memory cell using one capacitor and one transistor, respectively, and a cross-sectional view taken along line a-a', and FIG. 2 is a diagram illustrating a conventional thin capacitor. FIG. 3 is a process sectional view for explaining one embodiment of the present invention, FIG. 4 is a diagram for explaining the characteristics of the groove-type capacitor of the present invention, and FIG. 5 is a diagram for explaining another embodiment of the present invention. FIG.

Claims (1)

[Claims] 1 In a dynamic memory cell that stores information by accumulating charge in an MIS capacitor, an insulating region for isolation between elements is formed on a semiconductor substrate, an element region is formed surrounded by this insulating region, and this element The angle formed by all two sides adjacent to the semiconductor substrate of the region is greater than 90 degrees,
A semiconductor device characterized in that a groove having a polygonal opening of pentagon or more is formed, and a capacitor insulating film and then a capacitor electrode are formed in the groove.