JPH0563139A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device having a high noise immunity for a power device in which a power chip and its control circuit component are mounted on the same substrate. [Structure] For a semiconductor device in which a power insulating chip 2 and electronic components 3 constituting a control circuit thereof are distributed and mounted on a substrate using a metal insulating substrate 1 as a circuit substrate, a control circuit component mounting area on the metal insulating substrate is provided. Substrate insulation layer 1b
Of the metal base 1 in which the thickness D of the substrate is thicker than the insulating layer thickness d of the power chip mounting region, and the insulating layer of the substrate is a dielectric.
Regarding the capacitance between a and the conductor pattern 1c, the capacitance in the mounting area of the control circuit component is made smaller than the capacitance in the mounting area of the power chip.
As a result, the pulse current flowing through the control circuit due to the external noise is reduced and the noise immunity is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a power device such as a power transistor module used in, for example, an inverter device, and in particular, a metal insulating substrate is used as a circuit board, on which the power chip and its control circuit are provided. The present invention relates to a semiconductor device in which electronic components constituting the above are distributed and mounted.

[0002]

2. Description of the Related Art First, the structure of a conventional semiconductor device is shown in FIG. In the figure, reference numeral 1 denotes a metal base 1a such as aluminum and an insulating layer 1b such as epoxy resin.
A metal insulating substrate on which a conductor pattern (copper foil) 1c is formed, 2 is a power chip such as a power transistor, 3 is various electronic parts constituting a control circuit of the power chip 2, and 4 is Power chip 2 and conductor pattern 1
Bonding wires 5 for connecting to the c are packages, and the power chip 2 and the electronic component 3 are distributed on one metal insulating substrate 1 and soldered to the conductor pattern 1c.

[0003]

Such a power device is required to have a high noise immunity so that it does not malfunction with respect to noise intruding from a commercial power source or the like when it is used by incorporating it in an inverter device or the like. On the other hand, a noise test is generally carried out as a method for evaluating the noise resistance of a power device product. This noise test is performed by applying a high frequency pulse voltage between the input terminal and ground.

By the way, when a noise test is conducted on the semiconductor device having the conventional structure shown in FIG. 3, a pulse voltage is applied between the metal base 1a (ground side) of the metal insulating substrate 1 and the conductor pattern 1c. Along with the application, a capacitance C having the insulating layer 1b as a dielectric causes a pulse current represented by C × dV / dt to flow. In this case, an epoxy resin having a high dielectric constant is generally used for the insulating layer 1b of the metal insulating substrate 1 described above, and the thickness of the insulating layer 1b is usually about 85 to 150 μm in order to ensure high heat conductivity. Since it is extremely thin, the pulse current also becomes large. Moreover, since this pulse current also flows through the conductor pattern 1c to the electronic components that form the control circuit section, if the current is large, the conductor pattern 1
The voltage drop of c may break the voltage balance of the control circuit and cause the circuit to malfunction.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device for the above-mentioned semiconductor device, in which the structure of a circuit board is improved to ensure a high noise immunity. And

[0006]

According to the present invention, the capacitance between the metal base having the insulating layer of the substrate as a dielectric and the conductive pattern is the capacitance of the mounting area of the control circuit component of the power chip. This is achieved by configuring the circuit board so that it is smaller than the capacitance of the mounting area. Here, as a specific means for reducing the capacitance with respect to the mounting region of the control circuit component, the insulating layer thickness of the mounting region of the control circuit component on the metal insulating substrate is made thicker than the insulating layer thickness of the power chip mounting region. Alternatively, there is a configuration in which the control circuit component is mounted on a conductor pattern of a ceramic substrate and the ceramic substrate is aligned with the power chip and laminated on a metal insulating substrate.

[0007]

With the above structure, the thickness of the insulating layer (dielectric) interposed between the metal base of the circuit board and the conductor pattern is thicker in the mounting area of the control circuit component than in the power chip mounting area. The capacitance is reduced by that amount and the current flowing through the circuit board is reduced when the pulse voltage is applied. Therefore, malfunction of the control circuit due to external noise is less likely to occur, and noise immunity of the power device is improved. Since the electronic components of the control circuit generate less heat when energized as compared with the power chip, there is no problem even if the insulating layer of the circuit board is thick.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In each embodiment, the same members corresponding to those in FIG. 3 are designated by the same reference numerals. Embodiment 1: FIG. 1 shows an embodiment corresponding to claim 2 of the present invention. In this embodiment, with respect to the metal insulating substrate 1, an electronic component 3 that constitutes a control circuit of the power chip 2 is used.
The thickness D of the insulating layer (epoxy resin) 1b in the mounting area is larger than the thickness d of the insulating layer in the mounting area of the power chip 2. As a result, in the mounting area of the electronic component 3 of the control circuit, the capacitance between the metal base 1a using the insulating layer 1b as a dielectric and the conductor pattern 1c becomes smaller than the capacitance of the mounting area of the power chip 2, and the external The resistance to noise is improved.

Embodiment 2 FIG. 2 shows an embodiment corresponding to claim 3 of the present invention. In this example, first,
An electronic component 3 forming a control circuit of a power device is mounted on a conductor pattern 6a of a ceramic substrate 6 prepared separately from the metal insulating substrate 1, the ceramic substrate 6 is arranged on the power chip 2 and laminated on the metal insulating substrate 1, and bonded. It is fixed by the agent 7. As described above, the capacitance of the mounting area of the control circuit component 3 is the same as the capacitance of the mounting area of the power chip 2 because the electronic component 3 is mounted on the ceramic substrate 6 on the metal insulating substrate 1. Is smaller than

[0010]

As described above, according to the configuration of the present invention, in the circuit board of the semiconductor device, the layer thickness of the board insulating layer in the mounting area of the control circuit component is made thicker than the mounting area of the power chip. With this configuration, while ensuring high heat dissipation to the power chip, in the mounting area of the control circuit parts, the capacitance between the metal base with the insulating layer as a dielectric and the conductor pattern is better than that of the conventional structure. Since the size becomes smaller, the resistance to external noise can be improved and the reliability of the operating characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a configuration cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view showing the configuration of a second embodiment of the present invention.

FIG. 3 is a sectional view showing the configuration of a conventional semiconductor device.

[Explanation of symbols]

 1 Metal Insulation Substrate 1a Metal Base 1b Insulation Layer 1c Conductor Pattern 2 Power Chip 3 Electronic Component 6 Ceramic Substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H02M 7/48 Z 9181-5H H05K 1/18 S 9154-4E

Claims (3)

[Claims] 1. A semiconductor device in which a metal insulating substrate is used as a circuit substrate and electronic components constituting a power chip and its control circuit are distributed and mounted on the substrate, and a metal base having an insulating layer of the substrate as a dielectric is provided. A semiconductor device, wherein a circuit board is configured such that a capacitance in a mounting area of a control circuit component is smaller than a capacitance in a mounting area of a power chip with respect to a capacitance between the conductor pattern. 2. The semiconductor device according to claim 1, wherein the thickness of the insulating layer in the mounting region of the control circuit component on the metal insulating substrate is larger than the thickness of the insulating layer in the power chip mounting region. 3. The semiconductor device according to claim 1, wherein the control circuit component is mounted on a conductor pattern of a ceramic substrate, and the ceramic substrate is arranged side by side with a power chip and laminated on a metal insulating substrate.