JPH0565078B2 - - Google Patents

Info

Publication number
JPH0565078B2
JPH0565078B2 JP62242047A JP24204787A JPH0565078B2 JP H0565078 B2 JPH0565078 B2 JP H0565078B2 JP 62242047 A JP62242047 A JP 62242047A JP 24204787 A JP24204787 A JP 24204787A JP H0565078 B2 JPH0565078 B2 JP H0565078B2
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor mounting
circuit pattern
layer
etching resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62242047A
Other languages
Japanese (ja)
Other versions
JPS6484698A (en
Inventor
Munetoshi Yamada
Tooru Higuchi
Takeshi Kano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62242047A priority Critical patent/JPS6484698A/en
Publication of JPS6484698A publication Critical patent/JPS6484698A/en
Publication of JPH0565078B2 publication Critical patent/JPH0565078B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention] 【技術分野】【Technical field】

本発明は半導体実装用凹部を有してチツプキヤ
リヤ、ピングリツドアレイなどのパツケージ用基
板として公的に採用される多層回路基板の製造方
法に関する。
The present invention relates to a method for manufacturing a multilayer circuit board having recesses for semiconductor mounting and which is publicly adopted as a board for packages such as chip carriers and pin grid arrays.

【背景技術】[Background technology]

本発明者等は既に、第3図a,bに示すように
半導体実装用のマトリツクス回路基板2の半導体
実装用回路パターン1の露出部分1aにエツチン
グレジスト層3を形成し、半導体実装用回路パタ
ーン形成面2aに回路間凹凸吸収用絶縁層13を
設けた後、貫通部4を有する回路基板5を配置し
て加熱加圧一体化させて半導体実装用凹部10を
形成する多層回路基板の製造方法を開発している
が、加熱加圧するので、回路間凹凸吸収用絶縁層
13が溶融してしまい半導体実装用凹部10へと
流入してボンデイング部10aやダイ部10bに
付着してワイヤーボンデイング及びダイボンデイ
ングに悪影響を及ぼしてしまうという問題があつ
た。
The present inventors have already formed an etching resist layer 3 on the exposed portion 1a of the semiconductor packaging circuit pattern 1 of the semiconductor packaging matrix circuit board 2, as shown in FIGS. 3a and 3b, and etched the semiconductor packaging circuit pattern. A method for producing a multilayer circuit board, in which after providing an insulating layer 13 for absorbing unevenness between circuits on a forming surface 2a, a circuit board 5 having a through portion 4 is placed and integrated under heat and pressure to form a recess 10 for semiconductor mounting. However, since heating and pressurization is applied, the insulating layer 13 for absorbing irregularities between circuits melts and flows into the semiconductor mounting recess 10 and adheres to the bonding part 10a and die part 10b, causing wire bonding and die There was a problem in that it had a negative effect on bonding.

【発明の目的】[Purpose of the invention]

本発明は上記事情に鑑みて為されたものであ
り、その目的とするところは、半導体実装用凹部
を有してチツプキヤリヤ、ピングリツドアレイな
どのパツケージ用基板として好適に採用される多
層回路板の製造方法において、回路間凹凸吸収用
絶縁層の樹脂分が流動してボンデイング部やダイ
部へ付着することがなく、ワイヤーボンデイング
及びダイボンデイングに悪影響を及ぼすことがな
いようにすることにある。
The present invention has been made in view of the above circumstances, and its object is to provide a multilayer circuit board having recesses for semiconductor mounting and suitable for use as substrates for packages such as chip carriers and pin grid arrays. In the manufacturing method, the purpose is to prevent the resin component of the insulating layer for absorbing unevenness between circuits from flowing and adhering to the bonding part and the die part, and thereby preventing the wire bonding and die bonding from being adversely affected.

【発明の開示】[Disclosure of the invention]

本発明の多層回路基板の製造方法は、半導体実
装用のマトリツクス回路基板2の半導体実装用回
路パターン形成面2aに貫通部4を有する回路基
板5を積層一体化する多層回路基板の製造方法に
おいて、半導体実装用凹部10のボンデイング部
10aとダイ部10bをエツチングレジスト層3
で覆い、マトリツクス回路基板2の半導体実装用
回路パターン形成面2a乃至は回路基板5の内層
回路パターン形成面5aのエツチングレジスト層
3形成部分以外に回路間凹凸吸収用絶縁層13を
設け、この回路間凹凸吸収用絶縁層13の表面を
平滑にした後、接着剤により積層一体化させ、次
いで、孔開けした後スルホールめつき12を施し
てスルホール6を設け、最外層回路パターン7を
形成した後半導体実装用凹部10のエツチイング
レジスト層3を除去することを特徴とするもので
あり、この構成により上記目的が達成されたもの
である。 以下本発明を添付の図面に基づいて説明する。 半導体実装用のマトリツクス回路基板2は、ア
ルミナ、シリコンカーバイドなどのセラミツク、
ガラスエポキシ樹脂基板、ガラスポリイミド樹脂
基板、紙エポキシ樹脂基板、ガラストリアジン樹
脂基板などの無機質系基板あるいは有機質系基板
に感光性樹脂を用いたフオトエツチング方法や導
電ペーストをスクリーン印刷するといつた通常の
方法により半導体実装用回路パターン1が形成さ
れたものである。このマトリツクス回路基板2の
半導体実装用回路パターン1を積層した後に露出
する回路パターン部分1aにはエツチングレジス
ト層3が形成される。このエツチングレジスト層
3としては金、ニツケル、半田等の金属あるいは
電着塗装が可能な樹脂により形成される。又、こ
の実施例では、マトリツクス回路基板2の片面に
は回路パターンは形成されていなく、金属箔9が
貼着されている。尚、マトリツクス回路基板2を
複数のプリント配線基板で形成してもよい。この
マトリツクス回路基板2の半導体実装用回路パタ
ーン形成面2aには回路間凹凸吸収用絶縁層層1
3が設けられる。この回路間凹凸吸収用絶縁層層
13としては有機絶縁物のめつきレジストが採用
される。例えば、液状耐めつき液性ソルダーレジ
スト、フイルム状耐めつき液性ソルダーレジスト
又はこれらの組み合わせが採用できる。この回路
間凹凸吸収用絶縁層13はその表面が第2図に示
すように加圧されて平滑化されている。加圧する
場合に加熱してもよい。又、この回路間凹凸吸収
用絶縁層13の平滑化された表面をサンドブラス
トなどの物理的手段又は化学的処理により粗面化
させて、接着性を向上させるのが好ましい。粗面
化は回路間凹凸吸収用絶縁層の表面に金属箔をそ
の粗面側で配置して加圧するようにしてもよい。 マトリツクス回路基板2に積層一体化させる回
路基板5はプリント配線基板であり、その片面に
内層回路パターン8が形成され、他面は銅箔のよ
うな金属箔9のままの回路未形成面5bとなつた
ものであり、半導体実装用凹部10を形成するた
めの貫通部4が穿孔されている(第1図a参照)。 マトリツクス回路基板2の半導体実装用回路パ
ターン形成面2aに形成された回路間凹凸吸収用
絶縁層13の表面に接着剤を塗布等して回路基板
5をその回路パターン未形成面5bが最外面とな
るように、積層一体化される(第1図b参照)。
接着剤としては、エポキシ、ポリイミド等の液状
接着剤とか、エポキシ等の接着剤フイルム、ある
いはエポキシ、ポリミド等のガラス弐の含浸プリ
プレグ等が採用され、この接着剤はマトリツクス
回路基板2と回路基板5の接着面の略全面に設け
られる。 次に、内層回路パターン8に合わせてドリル加
工をした後、スルホールめつき12を施し、スル
ホール6、最外層回路パターン7を形成し、樹脂
汚染物及び半導体実装用凹部10のエツチングレ
ジスト層3を除去しボンデイング部10a及びダ
イ部10bを露出させて半導体実装用凹部10を
有する多層回路Aが製造される。 この多層回路基板Aの半導体実装用凹部10の
ボンデイング10a、ダイ部10bには回路間凹
凸吸収用絶縁層13の樹脂が付着していなく、ワ
イヤーボンデイング及びダイボンデイングに悪影
響が与えられることなく、半導体が実装されチツ
プキヤリヤ、ピングリツドアレイとして実用に供
される。
The method for manufacturing a multilayer circuit board of the present invention is a method for manufacturing a multilayer circuit board in which a circuit board 5 having a through portion 4 is laminated and integrated on a semiconductor mounting circuit pattern forming surface 2a of a matrix circuit board 2 for semiconductor mounting. The bonding part 10a and the die part 10b of the recess 10 for semiconductor mounting are etched with the etching resist layer 3.
An insulating layer 13 for absorbing unevenness between circuits is provided on the semiconductor mounting circuit pattern forming surface 2a of the matrix circuit board 2 or the inner layer circuit pattern forming surface 5a of the circuit board 5, except for the portion where the etching resist layer 3 is formed. After smoothing the surface of the insulating layer 13 for absorbing unevenness, it is laminated and integrated with an adhesive, and then, after drilling holes, through hole plating 12 is performed to provide through holes 6, and after forming the outermost layer circuit pattern 7. This structure is characterized in that the etching resist layer 3 of the semiconductor mounting recess 10 is removed, and with this structure, the above object is achieved. The present invention will be explained below based on the accompanying drawings. The matrix circuit board 2 for semiconductor mounting is made of ceramic such as alumina, silicon carbide, etc.
Conventional methods such as photo-etching using photosensitive resin or screen printing conductive paste on inorganic or organic substrates such as glass epoxy resin substrates, glass polyimide resin substrates, paper epoxy resin substrates, and glass triazine resin substrates. A circuit pattern 1 for semiconductor mounting is thus formed. An etching resist layer 3 is formed on the circuit pattern portion 1a of the matrix circuit board 2 that is exposed after the semiconductor mounting circuit pattern 1 is laminated. The etching resist layer 3 is made of metal such as gold, nickel, or solder, or a resin that can be electrodeposited. Further, in this embodiment, no circuit pattern is formed on one side of the matrix circuit board 2, but a metal foil 9 is pasted thereon. Incidentally, the matrix circuit board 2 may be formed of a plurality of printed wiring boards. On the semiconductor mounting circuit pattern forming surface 2a of this matrix circuit board 2, an insulating layer layer 1 for absorbing unevenness between circuits is formed.
3 is provided. As this insulating layer 13 for absorbing unevenness between circuits, a plating resist made of an organic insulator is employed. For example, a liquid solder resist with a liquid-like plating resistance, a liquid solder resist with a film-like plating resistance, or a combination thereof can be used. The surface of this insulating layer 13 for absorbing unevenness between circuits is pressed and smoothed as shown in FIG. Heating may be applied when pressurizing. Further, it is preferable that the smoothed surface of the insulating layer 13 for absorbing unevenness between circuits is roughened by physical means such as sandblasting or chemical treatment to improve adhesion. The roughening may be achieved by placing a metal foil on the rough surface side of the insulating layer for absorbing inter-circuit irregularities and applying pressure. The circuit board 5 to be laminated and integrated with the matrix circuit board 2 is a printed wiring board, and the inner layer circuit pattern 8 is formed on one side, and the other side is a metal foil 9 such as copper foil on which no circuit is formed 5b. A through hole 4 for forming a recess 10 for semiconductor mounting is bored (see FIG. 1a). An adhesive is applied to the surface of the insulating layer 13 for absorbing unevenness between circuits formed on the circuit pattern forming surface 2a for semiconductor mounting of the matrix circuit board 2, so that the circuit board 5 is arranged so that the circuit pattern-free surface 5b is the outermost surface. They are laminated and integrated (see Figure 1b).
As the adhesive, a liquid adhesive such as epoxy or polyimide, an adhesive film such as epoxy, or a prepreg impregnated with glass 2 such as epoxy or polyimide is used. This adhesive is used to bond the matrix circuit board 2 and the circuit board 5. It is provided on almost the entire surface of the adhesive surface. Next, after drilling according to the inner layer circuit pattern 8, through hole plating 12 is performed to form the through holes 6 and the outermost layer circuit pattern 7, and the etching resist layer 3 of the resin contaminants and semiconductor mounting recess 10 is removed. By removing and exposing the bonding part 10a and the die part 10b, a multilayer circuit A having a semiconductor mounting recess 10 is manufactured. The resin of the insulating layer 13 for absorbing unevenness between circuits is not attached to the bonding 10a of the recess 10 for semiconductor mounting and the die part 10b of this multilayer circuit board A, so that wire bonding and die bonding are not adversely affected. was implemented and put into practical use as a chip carrier and pin grid array.

【発明の効果】【Effect of the invention】

本発明にあつては、半導体実装用凹部を有する
信頼性の高い多層回路基板を安価に製造できるの
は勿論のこと、半導体実装用凹部のボンデイング
部とダイ部をエツチングレジスト層で覆い、マト
リツクス回路基板の半導体実装用回路パターン形
成面乃至は回路基板の内層回路パターン形成面の
エツチングレジスト層形成部分以外に回路間凹凸
吸収用絶縁層を設け、この回路間凹凸吸収用絶縁
層の表面を平滑にした後、接着剤により積層一体
化させ、次いで、孔開けした後スルホールめつき
を施してスルホールを設け、最外層回路パターン
を形成した後半導体実装用凹部のエツチイングレ
ジスト層を除去する常温常圧で積層一体化でき、
従つて、回路間凹凸吸収用絶縁層の樹脂分が半導
体実装用凹部のボンデイング及びダイ部には回路
間凹凸吸収用絶縁層の樹脂が付着していなく、ワ
イヤーボンデイング及びダイボンデイングに悪影
響を与えられることなく半導体を実装することが
できる。
In the present invention, not only can a highly reliable multilayer circuit board having a recess for semiconductor mounting be manufactured at low cost, but also the bonding part and the die part of the recess for semiconductor mounting can be covered with an etching resist layer to form a matrix circuit. An insulating layer for absorbing unevenness between circuits is provided on a surface of the board on which a circuit pattern for semiconductor mounting is formed or an inner layer circuit pattern is formed on the surface of the circuit board other than the area where the etching resist layer is formed, and the surface of the insulating layer for absorbing unevenness between circuits is smoothed. After that, they are laminated and integrated with an adhesive, and then, after drilling holes, through hole plating is applied to provide through holes, and after forming the outermost layer circuit pattern, the etching resist layer in the recess for semiconductor mounting is removed. Can be laminated and integrated with
Therefore, the resin of the insulating layer for absorbing unevenness between circuits does not adhere to the bonding and die parts of the recess for semiconductor mounting, which adversely affects wire bonding and die bonding. Semiconductors can be mounted without any problems.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,b,c,dは本発明の一実施例の各
工程を示す説明図、第2図a,bは同上の工程に
おける回路間凹凸吸収用絶縁層の平滑化工程を示
す説明図、第3図a,bは本発明者等が既に開発
している多層回路基板の製造方法を示す説明図で
あつて、Aは多層回路基板、2はマトリツクス回
路基板、2aは半導体実装用回路パターン形成
面、3はエツチイングレジスト層、4は貫通部、
5は回路基板、5aは内層回路パターン形成面、
10は半導体実装用凹部、10aはボンデイング
部、10bはダイ部、13は回路間凹凸吸収用絶
縁層である。
Figures 1 a, b, c, and d are explanatory diagrams showing each process of an embodiment of the present invention, and Figures 2 a and b are explanatory diagrams showing a smoothing process of the insulating layer for absorbing unevenness between circuits in the same process. Figures 3a and 3b are explanatory diagrams showing a method for manufacturing a multilayer circuit board that the present inventors have already developed, in which A is a multilayer circuit board, 2 is a matrix circuit board, and 2a is for semiconductor mounting. A circuit pattern forming surface, 3 an etching resist layer, 4 a penetration part,
5 is a circuit board, 5a is an inner layer circuit pattern forming surface,
10 is a concave portion for semiconductor mounting, 10a is a bonding portion, 10b is a die portion, and 13 is an insulating layer for absorbing unevenness between circuits.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体実装用のマトリツクス回路基板の半導
体実装用回路パターン形成面に貫通部を有する回
路基板を積層一体化する多層回路基板の製造方法
において、半導体実装用凹部のボンデイング部と
ダイ部をエツチングレジスト層で覆い、マトリツ
クス回路基板の半導体実装用回路パターン形成面
乃至は回路基板の内層回路パターン形成面のエツ
チングレジスト層形成部分以外に回路間凹凸吸収
用絶縁層を設け、この回路間凹凸吸収用絶縁層の
表面を平滑にした後、接着剤により積層一体化さ
せ、次いで、孔開けした後スルホールめつきを施
してスルホールを設け、最外層回路パターンを形
成した後半導体実装用凹部のエツチイングレジス
ト層を除去することを特徴とする多層回路基板の
製造方法。
1. In a method for manufacturing a multilayer circuit board in which circuit boards having through-holes are laminated and integrated on the semiconductor mounting circuit pattern forming surface of a matrix circuit board for semiconductor mounting, the bonding part and the die part of the recess for semiconductor mounting are formed using an etching resist layer. An insulating layer for absorbing unevenness between circuits is provided on the surface of the matrix circuit board on which the circuit pattern for semiconductor mounting is formed, or on the inner layer circuit pattern forming surface of the circuit board, in addition to the portion where the etching resist layer is formed. After smoothing the surface, they are laminated and integrated with adhesive, and then holes are formed and through-hole plating is applied to form through holes.After forming the outermost layer circuit pattern, the etching resist layer of the recess for semiconductor mounting is formed. A method for manufacturing a multilayer circuit board, characterized by removing the multilayer circuit board.
JP62242047A 1987-09-26 1987-09-26 Manufacture of multilayer circuit board Granted JPS6484698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62242047A JPS6484698A (en) 1987-09-26 1987-09-26 Manufacture of multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62242047A JPS6484698A (en) 1987-09-26 1987-09-26 Manufacture of multilayer circuit board

Publications (2)

Publication Number Publication Date
JPS6484698A JPS6484698A (en) 1989-03-29
JPH0565078B2 true JPH0565078B2 (en) 1993-09-16

Family

ID=17083480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62242047A Granted JPS6484698A (en) 1987-09-26 1987-09-26 Manufacture of multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS6484698A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5235211A (en) * 1990-06-22 1993-08-10 Digital Equipment Corporation Semiconductor package having wraparound metallization
CN114080146B (en) * 2021-11-02 2023-12-05 中国电子科技集团公司第三十八研究所 Low-temperature pressureless sensor metal shell sealing method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967686A (en) * 1982-10-12 1984-04-17 イビデン株式会社 Printed circuit board and method of producing same
JPS6167289A (en) * 1984-09-10 1986-04-07 エルナ−株式会社 Method of producing printed circuit board
JPS6175596A (en) * 1984-09-20 1986-04-17 イビデン株式会社 Manufacture of through hole multilayer circuit board
JPS61154096A (en) * 1984-12-26 1986-07-12 住友ベークライト株式会社 Manufacture of multilayer printed wiring board

Also Published As

Publication number Publication date
JPS6484698A (en) 1989-03-29

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