JPH06112812A - Binary counter - Google Patents

Abstract

PURPOSE:To conduct a test with two clock signals independently of a bit number through the provision of the test mode when the operation test of a binary counter is implemented. CONSTITUTION:Selector circuits 5-7 select a clock input signal CLK as an output signal by setting a select signal S to a high level. Thus, D type flip-flop circuits 1-4 output a high level at the falling of a 1st clock of all signals CLK and output a low level at the falling of a 2nd clock. Furthermore, outputs of the flip-flop circuits 1-4 are inputted to an AND gate 9 and its output is outputted from a terminal 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary counter, and more particularly to a binary counter with a test mode.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram of a conventional 4-bit asynchronous binary counter. In FIG. 5, the present binary counter has D-type flip-flops 60 to 63. The Q outputs of the D-type flip-flops 60 to 62 are input to the clock inputs of the D-type flip-flops 61 to 63 in the next stage, and also output from the output terminals 51 to 54. The output of Q (inverted value) is fed back to the data input (D).

Referring to the timing diagram of FIG. 6, FIG.
The operation of will be described. A clock signal (CL
K) is input to the C input of the first bit D-type flip-flop 60, its Q output is output from the Q output as a signal in synchronization with the falling edge of CLK, and the C bit of the second-type D-type flip-flop 61 is output. Input and output terminal 5 at the same time
It is output from 1.

At the second bit, since the Q output of the previous stage is input, it is input to the C input of the D-type flip-flop 62 of the third bit as a signal synchronized with the falling edge of the signal at the output terminal 51, and at the same time, the output terminal 52 Will be output.

Similarly, data as shown in the timing chart of FIG. 6 is output to the outputs of the output terminals 53 and 54, and the operation of the binary counter can be confirmed by checking the output terminals 51 to 54. .

However, with such a configuration, 2 n clocks are required until "1" is output to the n-bit Q output of the D-type flip-flop.

[0007]

As described above, the conventional n-bit binary counter requires 2n clocks to test its operation, and the test time increases as the number of bits increases. There was a drawback that it would increase.

An object of the present invention is to solve the above-mentioned drawbacks and to provide a binary counter with a shorter test time.

[0009]

The structure of the binary counter of the present invention has an n-bit D-type flip-flop, and the Q output of each bit of the n-bit D-type flip-flop is used as one input, Further, it has n-1 selectors having the clock signal as the other input, has an input terminal of a select signal for controlling the selector, and inputs the output of the selector to the D-type flip-flop of the next stage, When the test mode is selected by the select signal, the clock signal is input to each input of the n-bit D flip-flop.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a binary counter according to the first embodiment of the present invention. In FIG. 1, for simplicity, 4
A binary counter of bits will be described as an example.

In FIG. 1, in the present embodiment, D-type flip-flops 1 to 4 constituting a binary counter and D-type flip-flops 1 to 1 of each bit by a select signal S are used.
The clock input (C) 4 has selectors 5, 6 and 7 for selecting whether to input the Q output of the previous stage or the signal from the clock signal (CLK) input terminal.
The Q outputs of the D-type flip-flops 1 to 4 are output from the output terminals 11 to 14, respectively.

The Q (inverted value) outputs of the D-type flip-flops 1 to 4 are fed back to the data (D) input. The selectors 5, 6 and 7 have the same circuit configuration, and have 2-input AND gates 71 and 72 and an OR gate 73 as shown in FIG.

Next, referring to the timing chart of FIG.
The operation of FIG. 1 will be described. When the select signal S is low level, the selectors 5 to 7 are D-type flip-flops 1 to 1 of each stage.
Q output of 3 is selected. Therefore, in this case, the operation of the normal binary counter is performed as in the conventional example.

Next, when the select signal S is set to the high level, the test mode is set, the selectors 5 to 7 select the clock input signal CLK, and the D-type flip-flops 1 to 4 are selected.
Supply the same clock to. When a clock is input, each D-type flip-flop 1-
The Q output of 4 becomes high level all at once. Then, at the next falling edge of the clock, Q of each D-type flip-flop 1 to 4 is
The output outputs low level all at once. With the above operation, the operation of the D-type flip-flop that constitutes the binary counter can be tested with only two clocks.

FIG. 3 is a binary diagram of the second embodiment of the present invention.
It is a circuit diagram which shows a counter. In FIG. 3, the present embodiment is different from the first embodiment in that the AND gate 9 takes the logical AND of the Q outputs of the D-type flip-flops 1 to 4, and only the output terminal 14 is provided via the selector 8. The point is that you can check the operation.

Next, the operation of FIG. 3 will be described with reference to the timing chart of FIG. First, when the select signal S is low level, the normal binary counter operation is performed as in the case of the first embodiment.

Next, when the select signal S is set to the high level, the test mode is set, the selectors 5 to 7 select the clock input signal CLK, and the same clock is supplied to each of the D-type flip-flops 1 to 4. When the clock signal (CLK) is input, the Q outputs of the D-type flip-flops 1 to 4 simultaneously become high level at the falling edge of the clock.

Here, the AND gate 9 ANDs the Q outputs of the D-type flip-flops 1 to 4 to obtain an AND.
The output of the gate 9 also becomes high level, and the high level is output from the output terminal 14 through the selector 8.

Then, at the next falling edge of the clock, the Q outputs of the D-type flip-flops 1 to 4 simultaneously output a low level. Here, the AND output of the Q outputs of the D-type flip-flops 1 to 4 is ANDed by the AND gate 9, and the output of the AND gate 9 also becomes low level, and the low level is output from the output terminal 14 through the selector 8. Thus, in the second embodiment, the operation of the binary counter can be tested only from the output of the output terminal 14. The selector may be the circuit of FIG.

[0020]

As described above, according to the present invention, in the test mode, the same clock is applied to the clock inputs of the D-type flip-flops in each stage, so that the operation test of the binary counter can be performed with two clocks. It can be carried out.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a binary counter according to a first embodiment of the present invention.

2 is a timing diagram of the first embodiment of FIG. 1. FIG.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a timing diagram of the second embodiment of FIG.

FIG. 5 is a circuit diagram of a conventional binary counter.

FIG. 6 is a timing diagram of FIG.

FIG. 7 is a circuit diagram showing the selector shown in FIGS. 1 and 3;

[Explanation of symbols]

 1-4, 60-, 63 D-type flip-flop 5-8 Selector 9, 71, 72 AND gate 11-14, 51-53 Output terminal 73 OR gate S Select signal CLK Clock signal

Claims (2)

[Claims] 1. An n-bit D-type flip-flop having n-1 number of bits, wherein the Q output of each bit of the n-bit D-type flip-flop is one input and the clock signal is the other input. A selector and an input terminal for a select signal for controlling the selector; an output of the selector is input to the D-type flip-flop of the next stage; and when the test mode is selected by the select signal, the n-bit D A binary counter characterized in that the clock signal is inputted to each input of a flip flop. 2. The binary counter according to claim 1, further comprising an AND gate having each Q output of the D-type flip-flop as an input, and outputting the output through a selector.