JPH06124591A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] In a semiconductor memory device having a built-in memory circuit, the memory state of the memory circuit is uniquely determined to be "1" or "0" by turning on the power supply. [Structure] In a semiconductor memory circuit using a plurality of logic inversion circuits composed of PMOS transistors and NMOS transistors, the threshold value VTH of the second PMOS transistor 11 forming the second logic inversion circuit 12 is set to the first logic inversion circuit 7. Is set lower than that of the first PMOS transistor 1a constituting [Effect] By applying to a semiconductor memory circuit such as a memory, it is possible to configure a clear circuit that makes the stored content "1" or "0" when the power is turned on without increasing the number of transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a function of determining initial memory contents when power is turned on.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing, for example, a conventional semiconductor memory device, in which 1a is a first PMOS.
Transistors 2 are high-potential-side power supplies connected to the source of the first PMOS transistor 1a, and 3a is the first PM.
The NMOS transistors 4 connected to the drain of the OS transistor 1a are low-potential-side power supplies connected to the source of the NMOS transistor 3a. The first PMOS transistor 1a and the NPMOS transistor 3a constitute the first logic inversion circuit 7. Has been done. Further, 6 indicates the input of the first logic inverting circuit 7, and 5 indicates the output thereof.

Reference numeral 8 denotes the first PMOS transistor 1 between the high potential side power source 2 and the low potential side power source 4.
a, the second PMOS as well as the NMOS transistor 3a
A second logic inverting circuit constituted by connecting the transistor 1b and the NMOS transistor 3b is shown, 10 is its input, 9 is its output, and the input 5 receives the output 5 of the first logic inverting circuit 7. The output 9 is connected to the input 6 of the first logic inverting circuit 7.

Next, the operation will be described. When the power source is not turned on, the high potential side power source 2 is kept at the same potential as the low potential side power source 4. Next, when the power source is turned on, electric charges are supplied to the high potential side power source 2 and a potential difference is generated between the low potential side power source 4 and the high potential side power source 2.

When electric charges are supplied from the high-potential-side power supply 2 to the output 5 of the first logic inverting circuit 7 through the first PMOS transistor 1a of the first logic inverting circuit 7, the output 5 becomes high potential. Therefore, the output 9 of the second logic inversion circuit 8 has a low potential.

On the contrary, when electric charge is supplied from the high-potential-side power source 2 to the output 9 of the second logic inverting circuit 8 through the first PMOS transistor 1b of the second logic inverting circuit 8, the output 9 becomes high potential. Therefore, the output 5 of the first logic inversion circuit 7 becomes a low potential.

As described above, either the high or low output potential is held by the logic inversion circuits 7 and 8, and this is output as the output OUT until the potential level of the input 6 is rewritten by the external input IN.

Also, from the high potential side power source 2 through the first PMOS transistor 1a of the first logic inverting circuit 7 and the first PMOS transistor 1b of the second logic inverting circuit 8, the first logic inverting circuit 7 and the first logic inverting circuit 7 are provided. When charges are simultaneously supplied to the respective outputs 5 and 9 of the logic inversion circuit 8 of No. 2, neither of the outputs 5 and 9 can have a high potential, and an intermediate potential, that is, an indefinite state.

[0009]

Since the conventional semiconductor memory device is constructed as described above, the output value of the logic inversion circuit becomes indefinite when the power is turned on, and the high potential and the low potential are generated depending on the state at that time. There is a problem in that the output value is not uniquely determined, and when it is used as a system, it is necessary to add a logic circuit for determining the output value and to perform initial operations such as resetting and writing. .

The present invention has been made in order to solve the above problems, and the contents stored at the time of power-on without adding a logic circuit for determining an output value and performing initial operations such as resetting and writing. It is an object of the present invention to obtain a semiconductor memory device capable of determining.

[0011]

In a semiconductor memory device according to the present invention, a PMOS transistor connected to a high potential power source side, which constitutes each logic inversion circuit, has a switching speed, particularly a threshold VTH or a current gain (β). ) Are different from each other, and the stored contents can be determined when the power is turned on.

Further, a load circuit is provided at the output stage of the logic inversion circuit on the front side or the rear side, and the circuit output of one of the logic inversion circuits is delayed so that the stored contents can be determined when the power is turned on. is there.

[0013]

According to the present invention, since the PMOS transistors forming the respective logic inversion circuits have different switching operations, the contents stored by the output of the logic inversion circuit having the PMOS transistor having a high switching speed when the power is turned on are stored. Will be decided.

Further, since the load circuit is provided at the output stage of the logic inversion circuit at the front stage or the rear stage side, even if the switching operation points of the PMOS transistors of each logic inversion circuit are the same, the charge accumulation time is different and therefore the power is turned on. Sometimes the memory content is decided.

[0015]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit configuration diagram showing a semiconductor memory device according to a first embodiment of the present invention. The same reference numerals as those in FIG. 4 denote the same or corresponding portions, and 12 denotes a transistor characteristic, particularly its threshold value VTH. First PM configuring the logic inversion circuit 7
The second logic inversion circuit has the second PMOS transistor 11 set to be lower than the threshold value of the OS transistor 1a.

Next, the operation will be described. When the power is not turned on, the high-potential-side power source 2 is kept at the same potential as the low-potential-side power source 4. Next, when the power source is turned on, electric charges are supplied to the high potential side power source 2 and a potential difference is generated between the low potential side power source 4 and the high potential side power source 2.

Here, from the high potential side power source 2 to the first PMO
S-transistor 1a and second PMOS transistor 1
When electric charges are simultaneously supplied to the respective outputs 5 and 9 of the first logic inverting circuit 7 and the second logic inverting circuit 12 through 1, the threshold value V of the second PMOS transistor 11 is increased.
Since TH is set lower than that of the first PMOS transistor 1 of the first logic inversion circuit 7, the second PMOS
The switching operation of the transistor 11 is the first PMOS
It operates faster than the switching operation of the transistor 1a,
Since the charge is quickly supplied to the output 9 of the second logic inverting circuit 12 through the second PMOS transistor 11 of the second logic inverting circuit 12, the output 9 of the second logic inverting circuit 12 is output.
Has a high potential, and the output 5 of the first logic inverting circuit 7 has a low potential. Then, as described above, the logic inversion circuit 7
And 12 hold the high potential output, and the external input IN
This is output as the output OUT until the potential level of the input 6 is rewritten by.

As described above, according to the present embodiment, the second PMOS transistor 1 forming the second logic inversion circuit 12 is formed.
The threshold value VTH of 1 is set to the first
Since it is set to be lower than the threshold value of the PMOS transistor 1a, even if electric charges are simultaneously supplied from the high potential power source 2 to the first and second logic inversion circuits 7 and 12, the second PMOS
Since the transistor 11 performs a switching operation earlier and the output 9 is supplied with charges earlier and becomes a high potential, by applying this to a semiconductor memory device such as a memory, the number of transistors can be uniquely increased. It is possible to realize a clear circuit that clears the stored contents to "1" or "0" when the power is turned on.

In the above embodiment, the threshold value of the second PMOS transistor 11 of the second logic inverting circuit 12 is set to the first PMOS transistor 1a of the first logic inverting circuit 7.
By setting it lower than the threshold value of, it is possible to prevent the outputs 7 and 9 of the circuits 7 and 12 from becoming indefinite.
The threshold of the PMOS transistor 11 of
It may be set higher than the transistor 1a. In this case, since the first PMOS transistor 1a forming the first logic inversion circuit 7 switches quickly, the output 5 of the circuit 7 becomes high potential, Since the output 9 of the second logic inversion circuit 12 has a low potential, the same effect as that of the above-described embodiment is obtained.

Example 2. A semiconductor memory device according to the second embodiment of the present invention will be described below with reference to the drawings. In the above-described embodiment, the threshold value of the PMOS transistor forming the first logic inversion circuit and the threshold value of the PMOS transistor forming the second logic inversion circuit are set to be different from each other. The current gain β (= μ · W · ε / (L · t) of the PMOS transistor 1a forming the circuit 7;
μ: mobility, W: channel width, ε: gate insulating film dielectric constant, L: effective channel length, t: gate insulating film thickness). That is, in FIG. 2, 14 is the first P that constitutes the first logic inversion circuit 7.
It is a second logic inversion circuit having a second PMOS transistor 13 having a current gain β larger than that of the MOS transistor 1a.

Next, the operation will be described. When the power is not turned on, the high-potential-side power source 2 is kept at the same potential as the low-potential-side power source 4. Next, when the power is turned on, electric charges are supplied to the high potential side power source 2, and a potential difference is generated between the low potential side power source 4 and the high potential side power source 2.

Here, from the high potential side power source 2 to the first PMOS
Transistor 1a and second PMOS transistor 13
Through the first logic inverting circuit 7 and the second logic inverting circuit 14, respectively, charges are about to be simultaneously supplied, but the current gain β of the second PMOS transistor 13 is equal to the first logic. Since it is set larger than that of the first PMOS transistor 1a of the inverting circuit 7, the switching operation of the second PMOS transistor 13 is faster than the switching operation of the first PMOS transistor 1a, and the second logic inversion is performed. First P of circuit 14
The second logic inversion circuit 1 through the MOS transistor 13
The electric charge is quickly supplied to the output 9 of the fourth logic inversion 4, the output 9 of the second logic inversion circuit 14 becomes high potential, and the output 5 of the first logic inversion circuit 7 becomes low potential. And the logic inversion circuits 7 and 14
Holds the high potential output, and outputs OUT until the potential level of the input 6 is rewritten by the external input IN.
Will be output as.

As described above, according to this embodiment, the PMOS transistor 13 forming the second logic inversion circuit 14 is
Since the one having the current gain β smaller than that of the PMOS transistor 1a forming the first logic inverting circuit 7 is used, the electric charge is first supplied to the output 9 of the second logic inverting circuit 14 after the power is turned on, and Since the output 9 of the circuit 14 has a high potential, it is possible to prevent the output from becoming indefinite without separately providing a circuit for the initial operation, and the output value is uniquely determined.

In this embodiment, the current gain β of the second PMOS transistor 13 which constitutes the second logic inverting circuit 14 is set to the first PM which constitutes the first logic inverting circuit 7.
Although the current gain β of the OS transistor 1a is made larger, the current gain β of the first PMOS transistor 1a may be made larger than the current gain β of the second PMOS transistor 13 on the contrary. in case of,
The output 9 of the second logic inversion circuit 13 becomes a low potential,
The output 5 of the logic inverting circuit 7 has a high potential, and the logic is inverted with respect to the above-mentioned embodiment, but the same effect is obtained.

Example 3. A semiconductor memory device according to the third embodiment of the present invention will be described below with reference to the drawings. In each of the above embodiments, the characteristic of the transistor forming the logic inverting circuit is changed to give a difference in the output timing of the two logic inverting circuits. In this embodiment, however, the output stage of one logic inverting circuit is different. Is provided with a load circuit, and the speed at which the circuit output is transmitted to the input of the other logic inverting circuit is changed. That is, in FIG. 3, 15 is the first
Is an output resistance inserted in series to the output 5 of the logic inverting circuit 7, and 16 is an output capacitance connected between the output side end of the output resistance 15 and the low potential side power supply 4.

Next, the operation will be described. From the high-potential-side power supply 2 to the first and second first and second logic inversion circuits 7 and 8.
Charges are supplied to the outputs 5 and 9 of the first logic inverting circuit 7 and the second logic inverting circuit 8 through the PMOS transistors 1a and 1b, respectively, according to the charge supply time of the circuit, that is, the time constant of the circuit. . However, since the output 5 of the first logic inverting circuit 7 has a load including the output resistor 15 and the output capacitance 16, the second logic inverting circuit having a smaller time constant than the output 5 of the first logic inverting circuit 7 is provided. To the output 9 of the first PMOS transistor 1b of the second logic inversion circuit 8.
The electric charge is quickly supplied through the output, so that the output 9 of the second logic inverting circuit 8 first becomes high potential and the output 5 of the first logic inverting circuit 7 becomes low potential. And the logic inversion circuit 7
High potential output is held by and 8 and external input IN
This is output as the output OUT until the potential level of the input 6 is rewritten by.

As described above, according to the present embodiment, since the output 5 of the first logic inverting circuit 7 is provided with the load consisting of the resistor 15 and the capacitor 16, the output 9 of the second logic inverting circuit 8 is better. It becomes possible to prevent the output from becoming indefinite without a separate circuit for initial operation.
Moreover, the output value is uniquely determined.

In the third embodiment, the output 5 of the first logic inverting circuit 7 is provided with the circuit consisting of the output resistor 15 and the output capacitance 16 as a load, but the second logic inverting circuit 8 is used.
A circuit including an output resistor 15 and an output capacitance 16 may be provided as a load at the output 9 of the second logic inversion circuit 8 and the time constant of the second logic inversion circuit 8 may be set to be larger than that of the first logic inversion circuit 7. In this case, the output 9 of the second logic inverting circuit 8 has a low potential and the output 5 of the first logic inverting circuit 7 has a high potential, and the logic is inverted to that of the above embodiment, but the same effect is obtained.

The above embodiments may be used in combination. For example, by combining the first embodiment and the third embodiment, the PMOS transistor forming the logic inversion circuit on the rear side is connected to the logic on the front side. It is also possible to use a transistor having a threshold value lower than that of the PMOS transistor forming the inverting circuit and to provide a load circuit at the output stage of the logic inverting circuit on the preceding stage side.

In the third embodiment, the output resistor 15 and the output capacitor 16 are provided as the load circuit at the output 5 of the first logic inverting circuit 7, but either the resistor or the capacitor may be used. Good.

[0031]

As described above, according to the semiconductor memory device of the present invention, the high-potential-side PMOS transistors forming the two logic inversion circuits have different PMOS transistors having different transistor characteristics, particularly threshold VTH or current gain β. Since a transistor is used, PM with low threshold or high current gain
The output of the logic inversion circuit having the OS transistor becomes higher in potential first, and the stored contents can be determined when the power is turned on without adding a logic circuit for determining the output value and performing initial operations such as resetting and writing. There is an effect that can be done.

Further, since a load circuit composed of capacitors and resistors having different load capacities is provided at the output of either or both of the logic inverting circuits, the logic inverting circuit without a load or with a small load quickly becomes a high potential. In addition, it is possible to determine the stored contents when the power is turned on without adding a logic circuit for determining the output value and without performing initial operations such as resetting and writing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

 1a First PMOS transistor 2 High potential side power supply 3a, 3b NMOS transistor 4 Low potential side power supply 5 Output of first logic inverting circuit 6 Input of first logic inverting circuit 7 First logic inverting circuit 8 Second Logic inversion circuit 9 Output of second logic inversion circuit 10 Input of second logic inversion circuit 11 Second PMOS transistor with low threshold value 12 Second logic inversion circuit 13 Second PMOS transistor with large current gain β 14 Second logic inversion circuit 15 Output resistance 16 Output capacitance

Claims (4)

[Claims] 1. A plurality of logic inverting circuits composed of transistors connected in an inverter between a high-potential-side power supply and a low-potential-side power supply, and the output of the preceding logic inverting circuit is connected to the input of the following logic inverting circuit. In the semiconductor memory device in which the output of the logic inversion circuit of the subsequent stage is connected to the input of the logic inversion circuit of the previous stage, the switching speed of the transistors connected to the power supply side, which constitute each of the logic inversion circuits, is Unlike the latter stage, the semiconductor memory device is characterized in that the stored contents can be determined when the power is turned on. 2. The semiconductor memory device according to claim 1, wherein the threshold value of the transistor is different between the former stage and the latter stage. 3. The semiconductor memory device according to claim 2, wherein the current gain of the transistor is different between the former stage and the latter stage. 4. A plurality of logic inverting circuits composed of transistors connected in an inverter between a high-potential side power source and a low-potential side power source, and the output of the preceding logic inverting circuit is connected to the input of the following logic inverting circuit. In the semiconductor memory device in which the output of the logic inversion circuit in the subsequent stage is connected to the input of the logic inversion circuit in the previous stage, load circuits having different load capacitances are provided in either or both of the output stages of the preceding and subsequent logic inversion circuits. A semiconductor memory device, wherein the semiconductor memory device is provided such that the output time of the logic inversion circuit of the preceding stage and that of the succeeding stage differ, and the initial memory contents can be determined when the power is turned on.