JPH061792B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH061792B2 JPH061792B2 JP57233901A JP23390182A JPH061792B2 JP H061792 B2 JPH061792 B2 JP H061792B2 JP 57233901 A JP57233901 A JP 57233901A JP 23390182 A JP23390182 A JP 23390182A JP H061792 B2 JPH061792 B2 JP H061792B2
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- film
- cut
- fuse
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
- H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
- H10W20/494—Fuses, i.e. interconnections changeable from conductive to non-conductive changeable by the use of an external beam, e.g. laser beam or ion beam
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 (1) 発明の技術分野 本発明は半導体装置の製造方法、詳しくは多結晶シリコ
ン（ポリシリコン）によって形成されるヒューズの製造
方法に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a fuse formed of polycrystalline silicon (polysilicon).
(2) 技術の背景 例えば読出し専用メモリ(ROM)において、冗長性構造を
用意しておき、ユーザーの要求に応じて冗長性構造の特
定素子の接続をオンまたはオフにすることによりプログ
ラミングをなすことが行われ、かかる接続の切断のため
にポリシリコンのヒューズが用いられる。(2) Background of technology For example, in a read-only memory (ROM), a redundancy structure is prepared, and programming is performed by turning on or off the connection of a specific element of the redundancy structure according to the user's request. And a polysilicon fuse is used to disconnect such a connection.
第１図にかかるポリシリコンヒューズが断面図で示さ
れ、同図において、１は半導体基体、1aは二酸化シリコ
ン(SiO2)膜、２はポリシリコン層、３はりん・シリケー
ト・ガラス(PSG)膜を示す。ポリシリコン層２の切断す
べき部分にレーザビーム４を照射すると、図に点線で囲
った部分2aのポリシリコンが溶融・蒸発し、蒸発したポ
リシリコンは図に点線で囲む部分3aのＰＳＧを突き破っ
て図に矢印Ｉで示す如くに飛散し、部分2aと3aとは空隙
となり、ポリシリコン層２は切断され、ヒューズ膜とし
ての機能を果たすことになる。A polysilicon fuse according to FIG. 1 is shown in a cross-sectional view, in which 1 is a semiconductor substrate, 1a is a silicon dioxide (SiO 2 ) film, 2 is a polysilicon layer, 3 is phosphorus silicate glass (PSG). The membrane is shown. When the portion of the polysilicon layer 2 to be cut is irradiated with the laser beam 4, the polysilicon in the portion 2a surrounded by the dotted line in the figure is melted and evaporated, and the evaporated polysilicon penetrates the PSG in the portion 3a surrounded by the dotted line in the figure. As shown by the arrow I in the figure, the portions 2a and 3a become voids, the polysilicon layer 2 is cut, and functions as a fuse film.
(3) 従来技術と問題点 上記したポリシリコンヒューズにおいて、部分2aの蒸発
したポリシリコンは、ＰＳＧ膜３の上に飛び散って外観
を害するだけでなく、ＰＳＧ膜３を突き破るのであるか
らＰＳＧ膜３を損傷することもあり（きれいでない切
断）、更には他の素子の上に落ちて当該素子の機能を損
なうこともある。また、ポリシリコン層２のどの部分が
切断されるかはレーザビーム４がどこにくるかによって
決定され、レーザビーム４が正しい位置に照射されない
ときは、ポリシリコン層の切断したいところが切断され
ず、切断してはならないところが切断されることにな
り、切断部分が正確に局所化されない問題がある。(3) Conventional Technology and Problems In the above-described polysilicon fuse, the evaporated polysilicon in the portion 2a not only scatters on the PSG film 3 and impairs its appearance, but also penetrates the PSG film 3 so that the PSG film 3 Can be damaged (unclean cuts) and even fall onto other elements, impairing their function. Further, which part of the polysilicon layer 2 is cut is determined by where the laser beam 4 comes. When the laser beam 4 is not irradiated to the correct position, the part of the polysilicon layer to be cut is not cut, and the cutting is performed. There is a problem that the cut portion is not accurately localized because the portion that should not be cut is cut.
(4) 発明の目的 本発明は上記従来の問題点に鑑み、製造が容易で、切断
部分を局所化することができ、きれいな切断がなされ、
保護膜に影響を与えることのないポリシリコンヒューズ
の製造方法を提供することを目的とする。(4) Object of the present invention, in view of the above-mentioned conventional problems, easy manufacturing, it is possible to localize the cut portion, a clean cut is made,
An object of the present invention is to provide a method for manufacturing a polysilicon fuse that does not affect the protective film.
(5) 発明の構成 そしてこの目的は本発明によれば、半導体基板上に酸化
シリコンを含む第１の絶縁膜を形成する工程と、該絶縁
膜上に多結晶シリコンからなるヒューズ膜パターンを形
成し、切断すべき部分に凹部を形成して他の部分よりも
薄くなるよう形成する工程と、該ヒューズ膜パターンを
含む前記第１の絶縁膜上に、酸化シリコンを含む第２の
絶縁膜を、前記凹部に埋め込むように形成する工程と、
前記ヒューズ膜の前記切断すべき部分にエネルギービー
ムを照射し当該部分の多結晶シリコンを溶融させ、この
溶融した多結晶シリコンを当該切断すべき部分の両側の
多結晶シリコンに吸い込ませて前記ヒューズ膜パターン
を切断する工程とを有することを特徴とする半導体装置
の製造方法を提供することによって達成される。(5) Structure of the Invention According to the present invention, there is provided a step of forming a first insulating film containing silicon oxide on a semiconductor substrate, and forming a fuse film pattern made of polycrystalline silicon on the insulating film. Then, a step of forming a concave portion in a portion to be cut so as to be thinner than other portions, and forming a second insulating film containing silicon oxide on the first insulating film including the fuse film pattern. And a step of forming so as to be embedded in the recess,
The fuse film is irradiated by irradiating the portion of the fuse film to be cut with an energy beam to melt the polycrystalline silicon in the portion and sucking the melted polycrystalline silicon into the polycrystalline silicon on both sides of the portion to be cut. And a step of cutting the pattern.
(6) 発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Embodiments of the Invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図(a)に示される如く、半導体基体１の上のSiO2膜1
a上のポリシリコン層（ヒューズ膜）２にレーザビーム
４を照射すると（なお第２図以下において既に図示した
部分と同じ部分は同一符号を付して表示する）、溶融し
たポリシリコンはSiO2膜1aとのぬれが悪いために、SiO2
膜1aの上に拡がることなく、第２図(b)に符号2bを付し
て示すポリシリコン球状体となる。なお、同図(b)に示
す状態は、同図(c)に平面図で示される。As shown in FIG. 2 (a), the SiO 2 film 1 on the semiconductor substrate 1
When the polysilicon layer (fuse film) 2 on a is irradiated with the laser beam 4 (the same parts as those already shown in FIG. 2 and subsequent figures are designated by the same reference numerals), the melted polysilicon is SiO 2 Due to poor wetting with the film 1a, SiO 2
Without spreading on the film 1a, it becomes a polysilicon sphere shown by reference numeral 2b in FIG. 2 (b). The state shown in FIG. 7B is shown in a plan view in FIG.
他方、ポリシリコンが第３図(a)の断面図で示す如きブ
ロック2cであったとすると、上方からレーザビームを照
射しブロック2cの表面のポリシリコンを溶融すると、溶
融したポリシリコンは同図(b)に太線2dで示す如くブロ
ック2cの全表面上に拡がる。On the other hand, assuming that the polysilicon is the block 2c as shown in the sectional view of FIG. 3 (a), when the laser beam is irradiated from above to melt the polysilicon on the surface of the block 2c, the melted polysilicon is It spreads over the entire surface of the block 2c as indicated by the thick line 2d in b).
以上は本発明者が実験によって確認した事実であり、本
願発明は上述したところを応用するものである。The above is the fact that the present inventor has confirmed by experiments, and the present invention applies the above.
本発明の第１実施例は第４図に断面図で示され、同図に
おいて、１は半導体基板、1aは0.6μｍの厚さのSiO
2膜、２は0.4μｍの厚さのポリシリコン層（ヒューズ
膜）で、切断すべきところは通常のエッチング技術で凹
部2eとして形成する。従って、凹部2eにおいて、底部2f
のポリシリコンの厚さは他の部分の厚さの1/4〜1/3程度
と薄くなっている。ポリシリコン層２の上には例えば化
学気相成長法（CVD法）で保護膜としてのＰＳＧ膜３を
2.0μｍの厚さに成長する。A first embodiment of the present invention is shown in a sectional view in FIG. 4, in which 1 is a semiconductor substrate and 1a is SiO 2 having a thickness of 0.6 μm.
2 film, 2 is a thickness of the polysilicon layer of 0.4 .mu.m (fuse films), when it should be cut to form a recess 2e in the usual etching techniques. Therefore, in the recess 2e, the bottom 2f
The thickness of polysilicon is as thin as 1/4 to 1/3 of the thickness of other parts. A PSG film 3 as a protective film is formed on the polysilicon layer 2 by, for example, a chemical vapor deposition method (CVD method).
Grow to a thickness of 2.0 μm.
かかるポリシリコンヒューズに図示の如くレーザビーム
４を照射すると、ポリシリコン層２の底部2fは他の部分
よりも膜厚が薄いから、熱容量が小さいためより早く加
熱され、しかも膜厚の薄い方が、ポリシリコン層に沿っ
ての熱伝導が小さいため、その熱は、膜厚の大なる他の
部分に発生した熱よりも逃げ難く、その結果底部2fのポ
リシリコンは溶融する。When such a polysilicon fuse is irradiated with the laser beam 4 as shown in the drawing, the bottom portion 2f of the polysilicon layer 2 has a smaller film thickness than other portions, so that it is heated more quickly because of its small heat capacity, and the thinner the film thickness is. Since the heat conduction along the polysilicon layer is small, the heat is less likely to escape than the heat generated in other portions having a large film thickness, and as a result, the polysilicon at the bottom 2f is melted.
上記の如くに溶融したポリシリコンは、第２図と第３図
を参照して説明した如く、SiO2膜1aに対してはぬれが悪
く、またＰＳＧ層３に対しても、ＰＳＧはりんを含むSi
O2とみなすことができるのでぬれが悪いのに対して、両
側のポリシリコン部分についてはぬれが良いから、底部
2fの両側のポリシリコン層にきれいに吸い込まれ、その
結果、底部2fは第５図に見られる如く消滅してポリシリ
コンがあったところは空洞５となり、ポリシリコン層２
は凹部2eが形成された部分で完全に切断される。このこ
とは顕微鏡を用いる目視で本発明者によって確認され
た。As described above with reference to FIGS. 2 and 3, the polysilicon melted as described above does not wet the SiO 2 film 1a well, and the PSG layer 3 does not contain phosphorus. Including Si
Since it can be regarded as O 2 , it has poor wettability, while the polysilicon parts on both sides have good wettability, so the bottom part
It is sucked into the polysilicon layers on both sides of 2f cleanly, and as a result, the bottom 2f disappears as shown in FIG.
Is completely cut at the portion where the recess 2e is formed. This was confirmed by the present inventors by visual inspection using a microscope.
上記したポリシリコンの切断においては、溶融した底部
2fのポリシリコンがポリシリコン層２の他の部分に吸い
込まれるだけであるから、ＰＳＧ膜３にはなんら影響を
及ぼさないことが確かめられた。In the above polysilicon cutting, the molten bottom
It was confirmed that the PSG film 3 is not affected at all because the 2f polysilicon is only sucked into the other part of the polysilicon layer 2.
また、レーザビーム４の照射にずれがあっても、ポリシ
リコン層は切断すべきところ、すなわち凹部2eが形成さ
れたところで確実に切断されることも確認された。It was also confirmed that even if the irradiation of the laser beam 4 is deviated, the polysilicon layer is surely cut where it should be cut, that is, where the recess 2e is formed.
なお、第１実施例においては従来の技術に凹部2eのエッ
チングが加わるだけであり、特に難しい工程を必要とす
ることなく製造されうる。In addition, in the first embodiment, only the etching of the recess 2e is added to the conventional technique, and it can be manufactured without requiring a particularly difficult process.
(7) 発明の効果 以上、詳細に説明したように、本発明によれば、ポリシ
リコン層の薄い部分または狭い部分が選択的に表面張
力、すなわちポリシリコンのSiO2膜上でのぬれの悪さに
援けられて溶断されるので、切断部分の局所化が可能と
なり、きれいな切断が達成され、保護膜であるＰＳＧ膜
に影響を与えることのないポリシリコンヒューズが容易
な工程で製造されうる。(7) Effects of the Invention As described above in detail, according to the present invention, the thin portion or the narrow portion of the polysilicon layer is selectively surface tension, that is, the poor wettability of polysilicon on the SiO 2 film. Since it is melted by being blown by the substrate, the cut portion can be localized, a clean cut can be achieved, and a polysilicon fuse that does not affect the PSG film as the protective film can be manufactured in an easy process.
【図面の簡単な説明】 第１図は従来のポリシリコンヒューズの断面図、 第２図(a)はSiO2膜上のポリシリコン層を示す平面図、
同図(b)と(c)はSiO2膜上の溶融したポリシリコンを示す
断面図と平面図、 第３図(a)と(b)はレーザビーム照射の前と後におけるポ
リシリコンブロックの断面図、 第４図と第５図は本発明の第１実施例の断面図、であ
る。 １・・・半導体基体、 1a・・・SiO2膜、 ２・・・ポリシリコン層、 2e・・・凹部、 2f・・・凹部2eの底部、 2g・・・ポリシリコン条片、 2h・・・ポリシリコン条片の切断部分、 ３・・・ＰＳＧ膜、 ４・・・レーザビーム、 ５・・・空洞BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a conventional polysilicon fuse, FIG. 2 (a) is a plan view showing a polysilicon layer on a SiO 2 film,
3B and 3C are cross-sectional views and plan views showing the melted polysilicon on the SiO 2 film, and FIGS. 3A and 3B are polysilicon blocks before and after laser beam irradiation. Sectional views, FIGS. 4 and 5 are sectional views of a first embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... SiO 2 film, 2 ... Polysilicon layer, 2e ... Recess, 2f ... Recess 2e bottom, 2g ... Polysilicon strip, 2h ...・ Cut portion of polysilicon strip, 3 ... PSG film, 4 ... Laser beam, 5 ... Cavity
Claims (1)
絶縁膜を形成する工程と、 該絶縁膜上に多結晶シリコンからなるヒューズ膜パター
ンを形成し、切断すべき部分に凹部を形成して他の部分
よりも薄くなるよう形成する工程と、 該ヒューズ膜パターンを含む前記第１の絶縁膜上に、酸
化シリコンを含む第２の絶縁膜を、前記凹部に埋め込む
ように形成する工程と、 前記ヒューズ膜の前記切断すべき部分にエネルギービー
ムを照射し当該部分の多結晶シリコンを溶融させ、この
溶融した多結晶シリコンを当該切断すべき部分の両側の
多結晶シリコンに吸い込ませて前記ヒューズ膜パターン
を切断する工程とを有することを特徴とする半導体装置
の製造方法。1. A step of forming a first insulating film containing silicon oxide on a semiconductor substrate, a fuse film pattern made of polycrystalline silicon is formed on the insulating film, and a recess is formed at a portion to be cut. And forming a second insulating film containing silicon oxide on the first insulating film including the fuse film pattern so as to be embedded in the recess. The fuse is irradiated by irradiating the portion of the fuse film to be cut with an energy beam to melt the polycrystalline silicon in the portion, and sucking the melted polycrystalline silicon into the polycrystalline silicon on both sides of the portion to be cut. And a step of cutting a film pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57233901A JPH061792B2 (en) | 1982-12-29 | 1982-12-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57233901A JPH061792B2 (en) | 1982-12-29 | 1982-12-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59124741A JPS59124741A (en) | 1984-07-18 |
| JPH061792B2 true JPH061792B2 (en) | 1994-01-05 |
Family
ID=16962351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57233901A Expired - Lifetime JPH061792B2 (en) | 1982-12-29 | 1982-12-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061792B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100442868B1 (en) * | 2002-01-23 | 2004-08-02 | 삼성전자주식회사 | Forming method of fuse in semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2625089A1 (en) * | 1976-06-04 | 1977-12-15 | Bosch Gmbh Robert | ARRANGEMENT FOR SEPARATING CONDUCTOR TRACKS ON INTEGRATED CIRCUITS |
| JPS5834947B2 (en) * | 1980-10-24 | 1983-07-29 | 株式会社東芝 | Fuse blowing type semiconductor device and its manufacturing method |
-
1982
- 1982-12-29 JP JP57233901A patent/JPH061792B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59124741A (en) | 1984-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0041776B1 (en) | Method of manufacturing a semiconductor device comprising an isolation structure | |
| EP0083211B1 (en) | Semiconductor device with fuse | |
| JPH04267366A (en) | Thin-film resistance and its manufacture | |
| JPH0719842B2 (en) | Redundant circuit of semiconductor device | |
| EP0189598B1 (en) | Method for manufacturing a semiconductor device | |
| JPS584819B2 (en) | Hand tie souchi | |
| JPH061792B2 (en) | Method for manufacturing semiconductor device | |
| JPS6098655A (en) | Semiconductor device | |
| JP2766912B2 (en) | Manufacturing method of integrated circuit device | |
| JPH0440858B2 (en) | ||
| JPH0691092B2 (en) | Wiring layer flattening method | |
| JP2002076129A (en) | Semiconductor device and manufacturing method thereof | |
| JPS63275142A (en) | Manufacture of semiconductor device | |
| JPS59956A (en) | Semiconductor device with polysilicon fuse | |
| JPH0153509B2 (en) | ||
| JPS5929439A (en) | Insulating isolation method for semiconductor device | |
| JPH09232116A (en) | Semiconductor device and manufacture thereof | |
| JPS6143855B2 (en) | ||
| JPS6134257B2 (en) | ||
| JPS6336517A (en) | Manufacture of thin single-crystal semiconductor film | |
| JPS634620A (en) | Manufacture of semiconductor device | |
| JPS6139736B2 (en) | ||
| JPS61102722A (en) | Manufacture of semiconductor device | |
| JPH0722120B2 (en) | Method for manufacturing semiconductor device | |
| JPS637463B2 (en) |