JPH06187787A - Semiconductor memory and control method for operation of its pipe line - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor memory device that realizes a rational pipeline operation and a pipeline operation control method thereof. [Structure] The circuit from the start to the end of memory access is divided into a plurality of stages, and a latch circuit for taking in the output signal of the preceding circuit at the edge of a clock pulse is provided, and the above-mentioned latch circuit is provided corresponding to the signal propagation delay time in the preceding circuit Delay the clock pulse supplied to. [Effect] Since the signal propagation delay time between the circuits can be substantially set and distributed for each circuit stage by the delay of the clock pulse, the operation speed can be increased without sacrificing the degree of integration and power consumption. Can be planned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a pipeline operation control method thereof, and for example, a memory cell is constituted by a CMOS (complementary MOS) circuit and E
The present invention relates to a high-speed static RAM having an input / output interface compatible with CL (emitter coupled logic) and a technique effectively applied to a pipeline operation control method thereof.

[0002]

2. Description of the Related Art Bipolar transistor and CMOS
There is a high-speed, large-capacity static RAM that makes full use of logic gates, drivers, sense amplifiers, etc. that combine (complementary MOS). Regarding such a static RAM, for example, there are pages 199 to 209 of "Nikkei Electronics" dated March 10, 1986.

[0003]

The inventors of the present application have studied a memory access by a pipeline method in order to increase the speed of the static RAM as described above. That is, as shown in FIG. 7, the circuit for performing memory access is divided into four stages, and the latch circuits 2A to 2C are provided at the subsequent stage of the address buffer 1A, the output buffer 4A of the decoder 3 and the subsequent stage of the sense amplifier 9, respectively. Is provided, and the output signal of the preceding stage is held by the edge of the clock pulse CLK. As a result, memory access is performed by the four cycles T1 to T4 of the clock pulse CLK.

In such a static RAM, if pipeline operation is performed with a cycle time of 4 ns, for example, the signal propagation delay time between the latch circuits must be shorter (faster) than 4 ns. However, in the conventional static RAM described above, it is extremely difficult to set the signal delay time between the final decoder circuit, the memory cell, the data line, and the sense amplifier within 4 ns.

Therefore, it is conceivable to insert a latch circuit in the main word driver 5 or the sub word driver 6 in the middle of the signal path as described above. But,
The main word driver and the sub word driver need to be formed in conformity with a narrow pitch corresponding to the layout of the memory cell, and the number thereof becomes huge, which is also disadvantageous in terms of chip size and power consumption. Therefore, in order to perform the pipeline operation with the above configuration, the cycle time is determined by the signal path having the longest signal propagation delay time.

An object of the present invention is to provide a semiconductor memory device which realizes a rational pipeline operation and a pipeline operation control method thereof. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the circuit from the start to the end of the memory access is divided into a plurality of stages, and a latch circuit that captures the output signal of the preceding circuit at the edge of the clock pulse is provided, and the above-mentioned latch circuit corresponds to the signal propagation delay time in the preceding circuit. Delay the supplied clock pulse.

[0008]

According to the above-mentioned means, the signal propagation delay time between the respective circuits can be substantially set and distributed for each circuit stage by the delay of the clock pulse, so that the integration degree and the power consumption are sacrificed. It is possible to speed up the operation without doing so.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 shows a block diagram of an embodiment of a static RAM to which the present invention is applied. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known Bi-CMOS manufacturing technique.

X-system address signal A consisting of a plurality of bits
X0 to AXi are input to the X system address buffer XB. The address signal taken into the address buffer XB is converted into a CMOS level by the built-in level conversion circuit. The address signal converted to the CMOS level is held in the latch circuit.

The address signal held in the latch circuit is decoded by the X-system decoder circuit XD, and a word line selection signal is formed here. X series Tegoda circuit X
As will be described later, D is divided into a predecoder, a subword driver, etc., and a latch circuit is provided at the output part of the predecoder. The word line selection signal is transmitted to the word driver WD, although not particularly limited. By providing such a word driver WD, a large number of memory cells are coupled to each other so that a word line having a relatively large load capacitance can be switched between high speed and low speed.

A Y-system address signal A consisting of a plurality of bits
Y0 to AYj are input to the Y system address buffer YB. The address signal taken into the address buffer XB is converted into a CMOS level by the built-in level conversion circuit. The address signal converted to the CMOS level is held in the latch circuit.

The address signal held in the latch circuit is decoded by the Y-system decoder circuit YD, and the selection signal of the data line, in other words, the selection signal of the column switch is formed here. The selection signal of the column switch is transmitted to the Y selector (column switch) YS to connect the selected data line to the common data line.

The memory array MARY is constructed by arranging in a matrix static type memory cells of CMOS structure as described later. That is, in the figure, memory cells are arranged in a grid pattern at the intersections of the complementary data lines extending in the vertical direction and the word lines extending in the horizontal direction. It should be understood that the memory array MARY also includes a data line load circuit as described later. The word line may be composed of a main word line and a sub word line in order to speed up the operation of selecting the word line. That is, the load is lightened by dividing the word line to reduce the number of memory cells connected as a sub word line. Then, the sub-word line may be selected by combining the selection signal of the main word line and the selection signal of the column system.

Although not shown in the drawing, the read signal of the common data line is supplied to the input of the sense amplifier SA via a preamplifier, and is amplified here with high stability and at high speed. The amplified output signal of the sense amplifier SA is held in the latch circuit. The output signal of the latch circuit is sent from the data output terminal DO through the data output circuit OB. The read signal output from the data output terminal DO is an ECL level signal. Therefore, the sense amplifier SA performs the level conversion operation to form the ECL level output signal, and the latch circuit is also configured by the ECL circuit correspondingly.

ECL supplied from the data input terminal DI
The write data of the level is supplied to the input of the data input circuit IB. The write signal taken in through the data input circuit IB is converted into the CMOS level and held in the latch circuit provided in the subsequent stage.
The output signal of this latch circuit is transmitted to the input of the write amplifier WA. The write amplifier WA has a dummy latch circuit adapted to the transmission path of the address signal,
The write signal is output to the common data line with a delay of one cycle. As a result, the data write operation is performed in accordance with the memory cell selection cycle.

The timing control circuit TG receives the chip enable signal CEB and the write enable signal WEB, and activates the internal signal CE that activates the decoder circuits XD and YD, the operation signal SAC of the sense amplifier SA, and the write amplifier WA. An operation signal WE to be activated and an operation signal OE to activate the data line output circuit OB are formed. Since the control signal is input in one-to-one correspondence with the address, a latch circuit is also provided in the timing control circuit, and the various control signals are output according to each clock cycle.

FIG. 4 shows a concrete circuit diagram of one embodiment of the memory array section of the static RAM and its peripheral circuits. In the figure, P-channel MOS
The FET has an N-channel MOSFET by adding an arrow to its channel portion (back gate portion).
Distinguished from T. Since the input / output interface of the static RAM of this embodiment is made compatible with the ECL circuit, the negative power supply voltage VEE is used with respect to the ground potential of the circuit.

In memory array MARY, two memory cells connected to complementary data lines D0 and D0B are shown as a representative. Each of the memory cells MC has the same configuration as each other, and as its one specific circuit is representatively shown, the gate and the drain are cross-connected to each other and the source is coupled to the negative voltage of the circuit. Channel type storage MOSFETs Q1 and Q2 and the above-mentioned MOSFE
High resistance R1, made of a poly (polycrystalline) silicon layer provided between the drains of TQ1 and Q2 and the ground potential of the circuit
R2 and. N-channel type transmission gate MOSFETs Q3 and Q4 are provided between the common connection point of the MOSFETs Q1 and Q2 and the complementary data lines D0 and D0B.

The gates of the transmission gate MOSFETs Q3, Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines W0, Wn etc. shown by way of example, and the memories arranged in the same column. The input / output terminals of the cell are connected to a pair of complementary data lines (also referred to as complementary bit lines or complementary digit lines) D0 and D0B which are exemplarily shown as the representative.

In the memory cell MC, the MOSFET Q
1, Q2 and resistors R1, R2 form a kind of flip-flop circuit, but the operating point in the information holding state is quite different from that of the flip-flop circuit in the ordinary sense. That is, in the memory cell MC, in order to reduce the power consumption thereof, the resistance R1 of the memory cell MC is
MOSFETQ when ETQ1 is turned off
It has a remarkably high resistance value such that the gate voltage of 2 can be maintained at a voltage slightly higher than its threshold voltage. Similarly, the resistance R2 is also set to a high resistance value. In other words, the resistors R1 and R2 are made high enough to compensate the drain leak currents of the MOSFETs Q1 and Q2. The resistors R1 and R2 have a current supply capability that prevents the information charges accumulated in the gate capacitance (not shown) of the MOSFET Q2 from being discharged.

According to this embodiment, the RAM is a CMOS-
Although manufactured by the IC technique, the memory cell MC is composed of the N-channel MOSFET and the polysilicon resistance element as described above. Static type R
As the AM memory cell, a P-channel MOSFET may be used instead of the polysilicon resistance element. The size of the memory cell can be reduced as compared with the case of using a P-channel MOSFET. That is, when a polysilicon resistor is used, it can be formed on the gate electrode of the drive MOSFET Q1 or Q2, and the size of itself can be reduced. And P channel MOS
As when using the FET, the drive MOSFET Q1,
High integration is achieved because there is no need to keep a relatively large distance from Q2.

In the figure, although not particularly limited, between the complementary data lines D0 and D0B and the ground potential of the circuit,
P-channel type load MOSFETs Q9 and Q10 are provided which act as resistance elements when the power supply voltage VEE is constantly supplied to their gates. These load MOSFETs Q9 and Q10 are formed to have a relatively small size so as to have a small conductance. These load MOSFETs Q9, Q1
0 is a P-channel type load MO in parallel form.
SFETs Q11 and Q12 are provided. These loads M
The OSFETs Q11 and Q12 are formed to have a relatively large size so that they have a relatively large conductance.

The ratio of the combined conductance when the MOSFETs Q9 to Q12 are in the ON state and the combined conductance of the transmission gate MOSFET and the storage MOSFET of the memory cell MC is the same as that of the complementary data lines D0 and D0B in the read operation of the memory cell MC. , A value having a desired potential difference according to the stored information. An internal write signal WE, which is set to a high level such as the ground potential of the circuit during the write operation, is supplied to the gates of the load MOSFETs Q11 and Q12. As a result, during the write operation, the load MOSFET Q1
1, Q12 are turned off. Therefore, the load means of the complementary data line in the write operation is only the MOSFETs Q9 and Q10 having the small conductance.

In this embodiment, although not particularly limited, in order to make the signal amplitude of the read signal of the memory cell read through the column switch almost constant regardless of the address of the memory cell, the load MOSFET Q as described above is used.
9 to Q12 are not on the far end side of the complementary data lines D0 and D0B, in other words, on the side opposite to the end of the data line connected to the column switch side, but near the complementary data line and the column switch. Is provided. More specifically, the load MOSFETs Q9 to Q12 are arranged between the memory cell arranged closest to the column switch and the column switch.

In the figure, the word line W0 is selected by the X decoder circuit XD and the word driver WD, but in order to prevent the drawing from being complicated in the figure, an AND gate circuit G1 is used. It also serves as a predecoder, a subword driver, and a word driver, which will be described later. The same applies to the word line Wn shown as another representative. These decoders and word drivers are composed of AND gate circuits G1 and G2 which are similar to each other.

The input terminals of these AND gate circuits G1, G2, etc. are internally complementary formed by an address buffer XB which receives an X-system external address signal AX (AX0 to AXi) consisting of a plurality of bits supplied from the outside. Address signals are applied in a predetermined combination.

Although not particularly limited, a P-channel MOSFET Q5 is provided between the complementary data line D0 and the read common complementary data line RCD in the memory array.
A corresponding column switch is provided. Other data line D
A column switch composed of a P-channel MOSFET Q6 is also provided between 0B and the read common complementary data line RCDB. A column switch consisting of an N-channel MOSFET Q7 is provided between the complementary data line D0 and the write common complementary data line WCD in the memory array. A column switch composed of an N-channel MOSFET Q8 is also provided between the other data line D0B and the common complementary data line WCDB for writing.

The N-channel type MOSFETs Q7 and Q
The column selection signal Y0 is supplied to the gate of the column 8, and the column selection signal Y0 inverted by the inverter circuit N1 is supplied to the gates of the P-channel MOSFETs Q5 and Q6.
B is supplied. As a result, when the column selection signal Y0 is set to the high selection level, the N-channel MOSFETs Q7 and Q8 and the P-channel MOSFET are
Q5 and Q6 are turned on. The column selection signal Y
0 is formed by a Y decoding circuit configured by a circuit similar to the above X decoding circuit.

In the read operation, the voltage drop caused by the memory current flowing through the data line load resistance or the like with respect to the ground potential of the circuit is output as a read signal. Therefore, as described above, the P-channel MOSFET
Is used as a column switch, the read signal of the memory cell on the data line can be directly transmitted to the common complementary data lines RCD and RCDB without causing level loss due to the threshold voltage of the MOSFET. In the write operation, the complementary data line D
One of 0 and D0B is set to a low level such as the ground potential of the circuit, and the memory MO of the memory cell connected thereto is
By turning off the SFET, the other memory MO
Switch the SFET on. Therefore, by using the N-channel MOSFET as a column switch as described above, the low level of the ground potential of the circuit can be directly transmitted to the data line D0 or D0B.

In this embodiment, the common complementary data lines RCD and RCD for reading are loaded with a P-channel type load MO for supplying power to the common complementary data line for reading.
SFETs Q13 and Q14 are provided. These loads M
The power supply voltage VE is applied to the gates of the OSFETs Q13 and Q14.
When a low level such as E is constantly supplied, it functions as a resistance element. This load MOSFET Q1
The resistance values of Q3 and Q14 are set to have sufficiently large resistance values with respect to the load MOSFETs Q11 and Q12 provided on the data lines D0 and D0B.

Common complementary data line RC for reading
D and RCDB are coupled to the input terminal of the sense amplifier SA. The output signal of the sense amplifier SA is transmitted to the input terminal of the data output circuit OB which outputs the output signal from the external terminal. Common complementary data lines WCD, W for writing
The CDB is coupled to the output terminal of the write amplifier WA. The output signal of the data input circuit IB which receives the write data supplied from the external terminal is supplied to the input terminal of the write amplifier WA. By thus separating the common data line for reading and for writing, the load condition of the common complementary data line can be optimally set for the operations of the sense amplifier SA and the write amplifier WA.

A P-channel MOSFET Q13 for equalization is provided between the common complementary data lines RCD and RCDB for reading for high-speed reading. This MO
The equalizing pulse EQ is supplied to the gate of the SFET Q13. The equalize pulse EQ is generated when a 1-bit address signal of X system or Y system changes, and turns on the MOSFET Q13 to short-circuit the common complementary data lines RCD and RCDB.

The read operation from the memory cell of the static RAM of the above embodiment is as follows. The storage MOSFET in which the memory cell is turned on can be regarded as a constant current source. Therefore, the read low level from the memory cell is the data line load MOSFET in the memory cell MCn closest to the load MOSFETs Q11 and Q12.
A voltage drop occurs due to the memory current Io flowing through the resistance component RL of Q11 and Q12. The memory current Io
Is the resistance RY of the column switch provided in parallel with the resistor RL and the common data line load MOSFET Q1.
Although it also shunts to the resistance component RP of 3 and Q14, the series combined resistance of these resistors RY and RP is sufficiently larger than the resistance RL and can be substantially ignored.

On the other hand, in the memory cell MC0 arranged farthest from the load MOSFET,
The memory current Io is applied to the resistor RL and the data line resistance RD.
Will flow. Therefore, at the input / output node of the memory cell, a large signal amplitude is set by the resistance RL + RD, but on the column switch side, only the voltage drop caused by the memory current Io flowing through the resistance RL is the same as the above. Therefore, the common complementary data line RD for reading
The read signal of the memory cell transmitted to the input of the sense amplifier SA through C and RCDB can be made substantially constant regardless of the X-system address.

FIG. 5 shows the above ECL level as CMOS.
A circuit diagram of an embodiment of a level conversion circuit for converting to a level is shown. The input section of the level conversion circuit is basically composed of a unit ECL circuit. Therefore, the address buffer itself is provided as an input section. A transistor T1 that receives an ECL signal input from the outside and a transistor T2 that receives a reference voltage VBB are formed in a differential form, a constant current source Io is provided in a common emitter, and load resistors R1 and R2 are provided in a collector thereof. To be The collector outputs of the differential transistors T1 and T2 are input to the next level amplifier circuit section through an emitter follower output circuit composed of transistors T3 and T4 and a constant current source Io provided at the emitter.

The complementary output signal formed by the input section is supplied to the gates of P-channel MOSFETs Q1 and Q2. These P-channel MOSFETs Q1 and Q
The source of 2 is connected to the ground potential of the circuit and its drain is an N-channel MOSFET in the form of a current mirror.
Q3 and Q4 are provided. P-channel MOSFET Q1 whose gates are supplied with the complementary input signals.
And Q2 flow complementary drain currents according to their complementary input signal levels.

For example, when the current flowing through one MOSFET Q1 is made relatively large, the other MOSFET Q1.
The current flowing through 2 is made relatively small. In this case, a current mirror type N-channel MOSFET is formed according to the drain current formed by the MOSFET Q1.
A large current also flows through Q3 and Q4. Therefore, P
Channel MOSFET Q2 and N channel MOSFE
TQ4 is operated in a complementary manner, and a low level signal such as a substantially negative power supply voltage VEE corresponding to the conductance ratio is formed from the commonly connected drains.
Conversely, when the current flowing through the MOSFET Q2 is relatively increased and the current flowing through the MOSFET Q1 is relatively decreased, a high level such as the ground potential of the circuit is formed.

In this embodiment, in order to increase the output current, in other words, to rapidly drive a capacitive load having a relatively large capacitance value, the output signal of the level conversion circuit is , The collector is supplied to the base of the transistor T1 connected to the ground potential point of the circuit. The transistor T1 constitutes a totem pole type push-pull output circuit together with the transistor T2 connected in cascade. Although there is no particular limitation between the collector and the base of the output transistor T2 on the low level side, an N channel MOSFE for receiving the output signal on the preceding stage side is not particularly limited.
TQ5 is provided. An N-channel MOSFET Q6 for pulling out a low level for receiving an output signal is provided between the base and the emitter of the transistor T2.

Instead of this structure, the MOSFET Q5 may have the same structure as the MOSFETs Q1 to Q4 and receive the output signal of the level amplifying circuit whose input signal is inverted.

FIG. 6 shows a circuit diagram of one embodiment of the above preamplifier. As described above, the complementary data lines D0,
D0B and the like are connected to a pair of read common data lines RCD via a P-channel type switch MOSFET. The following preamplifier is provided on the read common data line RCD.

The signal read out to the read common complementary data line RCD is the emitter follower transistor T1.
2, T13, a differential transistor T1 via level-shifting diode type transistors T14 and T15.
6, It is transmitted to the base of T17. The emitter follower transistors T12 and T13 and the differential transistor T1
6, M on the emitter side of T17 operates as a current source
OSFETs Q19 to Q21 are provided. These MO
A selection signal is supplied to the gates of the SFETs Q19 to Q21. Depending on the selection signal, the MOSFETs Q19 to Q2
1 becomes an operating state and operates as a constant current source. On the other hand, when the non-selected state is set, the MOSFET Q19-
Q21 becomes inoperative and the operation of the preamplifier is stopped. The output signal of this preamplifier is input to the sense amplifier SA having a multiplexer function, and the selected one is output through the output circuit.

The complementary data lines D0 and D0B are N
It is connected to a pair of write common data lines WCD via a channel type switch MOSFET. In the write operation, write data is input to the write common data line WCD via the data input buffer and the write amplifier as described above.

FIG. 1 is a conceptual diagram showing the operation of one embodiment of the static RAM according to the present invention. In the figure, read access is shown as an example.
1A is an input buffer for receiving an address signal,
B is an input buffer for receiving clock pulses. The address buffer 1A takes in an ECL level address signal and converts it into a CMOS level.
The output portion of the address buffer 1A has a latch circuit 2
A is provided.

The output signal of the latch circuit 2A is supplied to the predecoder 3. The predecoder 3 decodes the address signal to form a word line selection signal. The decoder 3 which receives a column address signal forms a selection signal for the data line. The output signal of the predecoder 3 is input to the latch circuit 2B via the intermediate buffer 4A that also functions as a delay unit. The X-system selection signal of the latch circuit 2B is supplied to the main word driver 5 via the intermediate buffer 4B. The sub-word driver 6 receives the output signal of the main word driver 5 and the column-based decode signal and forms a sub-word line selection signal.

The memory cell 7 connected to the sub-word line selected by the sub-word driver is selected. The stored information held in the memory cell 7 is selected by the column-system selection operation, amplified by the preamplifier 8 and transmitted to the sense amplifier 9. This sense amplifier 9
A latch circuit 2C is provided at the output of. The output signal of the latch circuit 2C is output from the external terminal Do through the output circuit 10.

The input buffer 1B receives the ECL level clock pulse CLK, changes it to the CMOS level, and uses it as an internal clock pulse. In this embodiment, the delay circuits 11A, 11B and 11C having the delay time set according to the signal propagation delay time in the preceding circuit of each latch circuit as described above are provided. A clock pulse CLK1 supplied to the latch circuit 2A provided at the subsequent stage of the address buffer 1A through the delay circuit 11A.
Is formed. The delay circuit 11B forms a clock pulse CLK2 to be supplied to the latch circuit 2B provided in the subsequent stage of the predecoder. The delay circuit 11C
By the latch circuit 2 provided in the subsequent stage of the sense amplifier 9.
The clock pulse CLK3 supplied to C is formed.
The latch circuit 2C is composed of an ECL circuit in response to the sense amplifier SA forming an ECL level output signal.

Instead of this, the input buffer 1B to the EC
A function for outputting an L level output signal is provided, and the signal is delayed by the delay circuit 11C having an ECL structure to obtain the ECL.
The level clock pulse CLK3 may be formed. The delay circuits 11A to 11C are shown in the form of inverter circuits, but the number thereof represents a rough delay time. Therefore, for example, the latch circuit 2
A clock pulse CLK1 having the same phase as the clock pulse CLK is supplied to A by the two inverter circuits, and clock signals CLK2 having a phase opposite to the clock pulse CLK is supplied to the latch circuits 2B and 2C by the one and three inverter circuits. Note that this does not mean that CLK3 and CLK3 are supplied.

FIG. 2 is a timing chart for explaining the pipeline operation in the static RAM according to the present invention. The address signal ADD and the clock pulse CLK are input in one-to-one correspondence. Other control signals CEB and WEB (not shown) and input data in the write operation are also input corresponding to the address ADD.

In response to the address signal ADD and the clock pulse CLK as described above, the internal latch circuits 2A to 2C are delayed by the delay circuits 11A to 11C as described above as delay times TD1 to TD3. The pulses CLK1 to CLK3 are supplied.

A latch circuit (shown as a register in the figure) 2A provided in the next stage of the address buffer.
Takes in the first address signal A0 at a timing delayed by the delay time TD1. Then, the address signal A input in synchronization with the second clock pulse CLK
Prior to the capture of 1, the address signal A0 held in the latch circuit 2A is transmitted to the latch circuit 2B through the predecoder 3 and the intermediate buffer 4A, and is held by the clock pulse CLK2. As a result, the substantial cycle time of the preceding circuit of the latch circuit 2B is equal to the basic cycle time Tcyc + (TD2 of the clock pulse CLK.
-TD1), the time is smaller than the basic cycle time.

Then, prior to fetching the address signal A2 input in synchronization with the third clock pulse CLK, the address signal A1 held in the latch circuit 2A as described above is transferred to the predecoder 3 and the intermediate buffer 4A. Is transmitted to the latch circuit 2B through the latch circuit 2B and is held by the clock pulse CLK2. Further, although the address is switched by the change of the output signal of the latch circuit 2B,
At that time, the signal read by the previous address is transmitted to the input of the latch circuit 2C through the preamplifier 8 to the sense amplifier 9, and is held by the clock pulse CLK3. The substantial cycle time of the preceding circuit of the latch circuit 2C is set to be longer than the basic cycle time, such as the basic cycle time Tcyc + (TD3-TD2) of the clock pulse CLK.

Due to the delay of the clock pulse CLK by such a delay circuit 11A or 11C, the allowable signal propagation delay time of each stage focusing on the address signal A0 is Tcyc + in the signal transmission path from the latch circuits 2A to 2B.
It is made shorter than the basic cycle time like (TD2-TD1) and can be made longer than the basic cycle like Tcyc + (TD3-TD2) in the signal transmission path from the latch circuits 2B to 2C. That is, in the circuits from the latch circuits 2A to 2B, the allowable time is shortened in response to the small number of circuit stages such as the predecoder 3 and the intermediate buffer.
In the circuits from the latch circuits 2B to 2C, the permissible time can be lengthened in response to the time-consuming operations such as the memory cell selection operation by the main word driver and the sub word driver and the read operation of the stored information from the memory cell. .

With such a configuration, even if the basic cycle is 4 ns, for example, the cycle time T2 in the circuits from the latch circuits 2A to 2B is shortened to 2 ns, and the circuit from the latch circuits 2B to 2C is correspondingly shortened. The cycle time T3 can be increased to 6 ns. As a result, memory access can be realized from the outside by a pipeline operation in 4 ns.

In the write operation, one dummy latch circuit corresponding to the above-mentioned address signal transmission path is provided in the write-data transmission path, and two dummy latch circuits are provided after input.
Write data is transmitted in synchronization with the memory cell selection operation performed in response to the second clock pulse.

The operation and effect obtained from the above embodiment are as follows. That is, (1) the circuit from the start to the end of the memory access is divided into a plurality of stages, and a latch circuit that takes in the output signal of the preceding stage circuit at the edge of the clock pulse is provided, and the signal propagation delay time in the preceding stage circuit is dealt with. By delaying the clock pulse supplied to the latch circuit,
The signal propagation delay time between the respective circuits can be set substantially according to each circuit stage, and the operation speed can be increased without sacrificing the degree of integration and power consumption.

(2) Input / output interface is ECL
By applying it to a compatible high-speed static RAM having a Bi-CMOS configuration, it is possible to achieve an ultra-high speed without sacrificing the degree of integration and power consumption.

(3) In the pipeline operation control method in which the allowable signal propagation delay time between the latch circuits is performed by delaying the clock pulse as in the above (1), the latch circuit is inserted in the signal transmission path. Since the location is flexible, the effect of facilitating the circuit design and layout design can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
In the above, the selection operation of the memory cell may be performed not only by the main word driver and the sub word driver but also by the word driver only. A circuit for converting from the ECL level to the CMOS level can adopt various embodiments. Alternatively, the circuit may be configured by only the ECL configuration or only the CMOS configuration. Further, in the static RAM, an additional circuit such as a write recovery circuit may be provided on the common data line or the common complementary data line in order to perform high-speed reading after the write operation. The latch circuit may be anything as long as it performs an operation of fetching and holding data in synchronization with an edge of a clock pulse, such as a register or a flip-flop.

The present invention may use a dynamic memory cell as a memory cell in addition to the static RAM. Instead of such a RAM,
It may be applied to a ROM. The ROM is suitable only for the above-described pineline operation since the ROM only has a read operation, and a plurality of pieces of data are normally read continuously.

[0061]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the circuit from the start to the end of the memory access is divided into a plurality of stages, and a latch circuit for taking in the output signal of the preceding circuit at the edge of the clock pulse is provided, and the above latch circuit is provided corresponding to the signal propagation delay time in the preceding circuit. By delaying the clock pulse that is supplied to each circuit, the signal propagation delay time between each circuit can be set by distributing it to each circuit stage, and high-speed operation can be achieved without sacrificing the degree of integration and power consumption. Can be realized.

[Brief description of drawings]

FIG. 1 is an operation conceptual diagram showing an embodiment of a static RAM according to the present invention.

FIG. 2 is a timing diagram for explaining a pipeline operation in the static RAM according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

FIG. 4 is a specific circuit diagram showing an embodiment of a memory array section of the static RAM of FIG. 3 and its peripheral circuits.

FIG. 5 is a circuit diagram showing an embodiment of a level conversion circuit for converting an ECL level into a CMOS level.

FIG. 6 is a circuit diagram showing an embodiment of the preamplifier.

FIG. 7 is an operation conceptual diagram showing one embodiment of a static RAM examined prior to the present invention.

[Explanation of symbols]

1A ... address buffer, 1B ... input buffer, 2A ...
2C ... Latch circuit, 3 ... Decoder, 4A, 4B ... Intermediate buffer, 5 ... Main word driver, 6 ... Subword driver, 7 ... Memory cell, 8 ... Preamplifier, 9 ... Sense amplifier, 10 ... Output circuit, 11A to 11C ... Delay circuit.
XB ... X system address buffer, YB ... Y system address buffer, XD ... X system decoder circuit, YD ... Y system decoder circuit, WD ... Word driver, YS ... Column switch (Y
Selector), MARY ... memory array, SA ... sense amplifier, OB ... data output circuit, IB ... data input circuit,
WA ... Write amplifier, TG ... Timing control circuit, M
C ... Memory cell, W0, Wn ... Word line, D0, D0B
... Complementary data lines, RCD, RCDB ... Common complementary data lines for reading, WCD, WCDB ... Common complementary data lines for writing.

Claims (4)

[Claims] 1. A circuit from a memory access start to an end is divided into a plurality of stages, and a latch circuit for fetching an output signal of the preceding circuit at an edge of a clock pulse and a signal propagation delay time in the preceding circuit are provided in correspondence with the latch circuit. A semiconductor memory device comprising: a delay circuit for delaying a clock pulse supplied to a latch circuit, and performing memory access by a pipeline method. 2. The semiconductor memory device according to claim 1, wherein the latch circuit is provided in a subsequent stage of an address buffer, a subsequent stage of a predecoder, and a subsequent stage of a sense amplifier. 3. The address buffer has a level conversion circuit for converting an ECL level signal into a CMOS level, and a latch circuit for receiving the output signal is a CMO.
A signal which is composed of an S circuit and is read from a memory cell of CMOS structure is input to a sense amplifier through a preamplifier and converted to an ECL level, and a latch circuit which receives the output signal is a latch circuit of ECL structure. 3. The semiconductor memory device according to claim 2, wherein 4. A circuit from the start to the end of memory access is divided into a plurality of stages, and a latch circuit for fetching an output signal of the preceding circuit at the edge of a clock pulse is provided and a signal propagation delay time in the preceding circuit is reduced. A pipeline operation control method for a semiconductor memory device, characterized in that the clock pulse supplied to the latch circuit is delayed correspondingly.