JPH0659862A - Multiplier - Google Patents

Abstract

(57) [Summary] [Object] It is an object of the present invention to provide a multiplier that can reduce the number of gates and the delay time of data. [Composition] A multiplier for multiplying floating-point single-precision and double-precision data, which is output as it is when the input is exponent data of the multiplier and multiplicand of the double-precision data, and the digit when the input is single-precision data. A data conversion means 600 that outputs the data by aligning the number with the number of digits of double precision data, and an output that inputs the output of the data conversion means 600 and adds the both to output.
When the input is double precision data, it is output as it is, and when the input is single precision data, a fixed number of digits is input. Addition / subtraction of the correction means 900 for correcting and outputting, and the value of the predetermined upper digit number of the output of the first addition means and the value for normalizing the input data with the reference value when the double precision data is calculated. Second adding means 10 for processing and outputting
It consists of 0 and.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier capable of multiplying IEEE compliant floating point single precision and double precision data.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing an example of a floating point single precision data format. FIG. 9 is a diagram showing an example floating-point double-precision data format.

FIG. 10 shows a calculation processing time of exponential part data in the conventional example.
It is a block diagram which shows the structure of a road. First, IEEE-compliant floating
Format of moving point single precision data and double precision data
This will be described with reference to FIGS. 8 and 9. 8 and 9
At S₁, S₁', S ₂, S₂', S₃, S₃'Is 1
A mark consisting of a dot and indicated by "0" for positive and "1" for negative
Represents an issue. e₁, E₁', E₂, E₂', E₃, E₃'Is the index
Represents partial data, single precision (e₁, E₁', E₂, E₂')of
Time consists of 8 bits and double precision (e₃, E₃') When 11
It consists of bits. Also, f₁, F₁', F₂, F₂', F₃,
f₃'Represents mantissa data, single precision (f₁, F₁',
f₂, F₂') Consists of 23 bits and double precision (f₃,
f₃') Consists of 52 bits. Also, in FIG.
0 to 31 bits are lower floating bits, 32 to 63 bits are upper floating bits
Represents the decimal point single precision data format. In Figure 9, 0
63-bit floating point double precision data format
Represents

Next, when these data are expressed by equations, (-1) ^S x 2 ^e-127 x (1.f) ... floating point single precision data (-1) ^S x 2 ^e-1023 x (1.f) Floating-point double precision data The exponent data of the multiplier and the multiplicand of the above equation are added to the data selector 1 and the data selector 2 shown in FIG. 10, respectively. Since only the arithmetic processing of the exponent part data is described here, the data selectors 1 and 2 respectively select and output the upper 8-digit exponent part data e ₁ and e ₁ ′ in the case of the floating point single precision operation. To do. Adder (hereinafter ADD
3), these outputs are added (e ₁ + e ₁ ′), and the output is added to a subtracter (hereinafter referred to as SUB) 5.

On the other hand, since the data selector 1 and 2 data e ₁ -127, which is input in the form of e ₁ '-127, AD
It is necessary to subtract 127 (this value is called a bias value) from the addition result in D3. For this reason, the bias value selector 4 selects and outputs binary number data corresponding to 127 preset in the case of single precision, and outputs the binary number data to the SUB5. SUB5
Then, 127 is subtracted from the addition result input from ADD3 and output.

In the case of floating point double precision arithmetic, data
11 digit exponent data e with selectors 1 and 2₃, E₃'
Select and output. Add these outputs with ADD3 (e₃
+ E ₃') And add the output to SUB5. On the other hand, buy
1023 preset for double precision with ass selector 4
Select and output binary data corresponding to (bias value)
In addition to SUB5, input from ADD3 with SUB5
1023 is subtracted from the addition result and output. In this way
The calculation processing of the exponent part data was performed.

[0007]

However, in the conventional circuit configuration, since the arithmetic processing of the floating point single precision data and the double precision data is performed using the same adder (ADD), the double precision data Adder that can add in the number of digits (11 digits) and subtracter that can subtract the bias value (SUB)
Was needed. For this reason, two stages of multiple bits (11, 13
According to the configuration using the (bit) adder and the selector, there is a problem that the number of gates and the data delay time increase.

Therefore, an object of the present invention is to provide a multiplier that can reduce the number of gates and the delay time of data.

[0009]

The above problems can be solved by the circuit configuration shown in FIG. That is, in FIG. 1, 60
0 is output as it is when the input is the exponent data of the floating-point double-precision data and the multiplicand, and when the input is the exponent data of the floating-point single-precision data and the multiplicand, the number of digits is multiplied by the floating-point number. It is a data conversion unit that outputs the data by aligning it with the number of digits of the exponent part data of the precision data and the multiplicand.

Reference numeral 800 is a first adding means for inputting the output of the data converting means 600, adding the two, and outputting them. 90
0 inputs the data of a predetermined lower digit of the output of the first adding means and outputs it as it is when the input is the exponent part data of the floating point double precision data, and outputs the exponent of the floating point single precision data. When it is partial data, it is a correction means for correcting and outputting a certain number of digits of data.

Reference numeral 100 denotes a summation / addition of a predetermined number of high-order data of the output of the first addition means and a value for standardizing the input data with a reference value during the calculation of the floating-point double-precision data.
It is a second addition means for performing subtraction processing and outputting.

[0012]

In FIG. 1, when the input is the exponent part data of the multiplier and multiplicand of the floating point double precision data, it is output as it is, and the input is the exponent part data of the floating point single precision data and the multiplicand. , The number of digits is aligned with the number of digits of the exponent part data of the multiplicand and the multiplicand of the floating-point double-precision data and output.

Next, the first adding means 800 inputs the output of the data converting means 600, adds the exponent data of the multiplier and the multiplicand, and outputs the result. When the floating point single precision data is calculated, the correcting means 900 corrects and outputs a fixed number of digits of the output data of the first adding means.

Further, at the time of calculation of the floating point double precision data, the second addition means combines the data of a predetermined number of upper digits of the output of the first addition means and the value for standardizing the input data with the reference value. Add / subtract and output.

As a result, when the floating point single precision data is calculated by the data converting means 600, the digit number of the exponent part data is aligned with the digit number of the exponent part data of the floating point double precision data and output. It becomes easier and the number of gates can be reduced.

Further, at the time of calculation of the floating point double precision data, the data of a predetermined number of upper digits of the output of the first adding means and the value for standardizing the input data with the reference value by the second adding means. Since the addition / subtraction processing is performed and the output is performed, the circuit can be downsized. Therefore, the number of gates and the data delay time can be reduced.

[0017]

FIG. 2 is a block diagram showing the configuration of an arithmetic processing circuit for exponent part data according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of the data converter circuit of the embodiment. FIG. 4 is an operation explanatory diagram of the adder (ADD) of the embodiment. FIG. 5 is a diagram showing the expression of FIG. 4 in a simplified manner.

FIG. 6 is a circuit diagram based on FIG.
FIG. 7 is a diagram showing a data processing method of the correction circuit of the embodiment. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, 6 and 7 are data conversion circuits for aligning the data formats of the multiplier and the multiplicand, respectively, 8 is an adder (ADD) for adding data and a part of the 2's complement value of the bias value, Reference numeral 9 is a correction circuit for single precision calculation, and 10 is an adder (ADD) for adding a part of the 2's complement value of the bias value during double precision calculation.

In the data conversion circuits 6 and 7,
When inputting floating-point single precision data, align the number of digits with the number of digits of double precision data, and then set the same bias value (= 102
3) Try to pull. Actually, a process of adding "896" (which is represented by a binary number "1110000000"), which is the difference (1023-127) between the two bias values, to the single precision data.

Specifically, the exponent part data of 8-bit single precision data is, for example, e ₇ e ₆ e ₅ e ₄ e ₃ e ₂ e
_{As 1} e ₀ , the most significant bit (M
When SB, e ₇ ) = 0, the value “e ₇ 111” is added to the upper 7 bits of the lower 7 bits (e _{6 to} e ₀ ) and output. When MSB = 1 as shown in FIG. 3 (2). "e ₇ 000"
Lower 7 bits of the exponent section data a value of (e ₆ ~e ₀₎
Is added to the upper part of and output. In the case of floating-point double-precision data, assuming that 11-digit data is e ₁₀ to e ₀ , for example, as shown in FIG.
As shown in (3), the data conversion circuits 6 and 7 output without processing.

The outputs of the data conversion circuits 6 and 7 are added to the ADD 8 and both are added. The outputs of the data conversion circuits 6 and 7 are respectively e ₁₀ to e ₀ and e ₁₀ 'to e.
_{When set to 0} ', the maximum addition result of 11 bits + 11 bits is
Will be 12 bits. Although this value has no sign, a sign is required when considering subtraction of the bias value, so "0" indicating a positive sign is added to the most significant side. As a result,
Are shown _{(0) e 11 '' ~e} 0 '' is obtained. The subtraction of the bias value 1023 can be realized by adding the 2's complement value of 1023.

FIG. 5 is a simplified representation of the equation of the arithmetic processing transition shown in FIG. The calculation of FIG. 5A is the AD of FIG.
D8 is performed, and the operation of (B) is performed by ADD10 in FIG. Figure 6
FIG. 6 is a circuit diagram constructed based on the equation of FIG. 2A shows the ADD 8 of FIG. 2, and FIG. 2B shows the ADD 10 of FIG. The input / output data matches the data name in FIG. Figure 5 (A)
The operation of adding "1" to the least significant bit is realized by inputting "1" to the carry-in (CI) terminal in FIG. 6 (a).

In the operation (B), the data (e ₁₀ ″ in FIG. 5) output from the X11 (most significant bit) terminal in FIG. 6A and the carry out (CO) terminal are output. Data (e ₁₁ ″ in FIG. 5), respectively, for A ₁ and A _{2 in} (b)
To enter. In addition to the A ₃ to enter a "0". Also, the other input data of the adder of (b) B ₁ , B ₂ , B ₃
"1" is input to and the carry-in (CI) terminal of (b) is input "0". Thus, from (a) to e ₀ '''~ e
'Outputs, (b) e ₁₀ from' ₉ '' to output a 'to e _12' ''.

FIG. 7 shows a processing method in the correction circuit 9. Since the format conversion was not performed in the data conversion circuits 6 and 7 during the floating point double precision calculation,
Data correction processing is not necessary, and e ₁₂ ′ ″ to e ₀ ′ ″ are output as they are. (However, e ₁₀ ′ ″ to e ₀ ′ ″ are used as exponential data).

Data conversion circuit 6 for single precision calculation
89 because 896 was added to the multiplier and the multiplicand in 7 and 7, respectively.
Since 6 is doubly added, it is necessary to subtract 896, and the correction circuit 9 performs the process of subtracting 896 from e ₁₂ ′ ″ to e ₀ ′ ″ in FIG. 7. In this circuit, the process of subtracting 896 is replaced by the process of adding 2's complement value of 896. However, since the significant digit of single precision data is 8 bits, the upper 3 bits "1" becomes invalid and this value is Do not add.

Since the overflow and underflow judgments are made using e ₈ '"and e ₉ '", the correction is 8,
Only 9 and 10 bits need to be performed.

[0029]

[Table 1]

Table 1 shows data (correction-related bits) before and after being input to the correction circuit during single-precision calculation. In order to realize this, a configuration using a random logic is used instead of an adder.

In this way, the single-precision operation data outputs e ₇ ″ ″ and e ₆ ″ ″ to e ₀ ″ ″ as exponents. As a result, when the floating-point single precision data is calculated in the data conversion circuits 6 and 7, the number of digits of the exponent part data is aligned with the number of digits of the double precision data and is output. Since the fixed data to be added to the exponent part data is determined by the value of MSB, e ₇ ), the circuit configuration is simplified and the number of gates can be reduced.

In addition, when the floating point double precision data is calculated, the adder (ADD) 10 adds a part of the 2's complement value of the bias value (1023) to the upper 2 bits of the output of the ADD 8. The circuit can be miniaturized. Therefore, the data selector included in the conventional circuit is not provided and the multi-bit adder is not configured in two stages.
The number of gates and data delay time can be reduced.

[0033]

As described above, according to the present invention, the data selector included in the conventional circuit is not provided and the multi-bit adder is not configured in two stages.
This has the effect of reducing the number of gates and data delay time.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention,

FIG. 2 is a block diagram showing a configuration of an arithmetic processing circuit for exponent part data according to an embodiment of the present invention.

FIG. 3 is an operation explanatory view of the data converter circuit of the embodiment,

FIG. 4 is an operation explanatory diagram of an adder (ADD) of the embodiment,

5 is a simplified diagram of the equation of FIG. 4,

6 is a circuit diagram based on FIG. 5,

FIG. 7 is a diagram showing a data processing method of the correction circuit of the embodiment,

FIG. 8 is a diagram showing an example of floating point single precision data format;

FIG. 9 is a diagram showing an example floating-point double-precision data format,

FIG. 10 is a block diagram showing a configuration of an arithmetic processing circuit for exponent part data of a conventional example.

[Explanation of symbols]

 100 is the second adding means, 600 is the data converting means, 800 is the first adding means, and 900 is the correcting means.

Claims (1)

[Claims] 1. A multiplier for multiplying floating-point single-precision and double-precision data, which is output as it is when the input is exponent data of the multiplier and multiplicand of the floating-point double-precision data, and the input is the floating-point data. When it is exponent part data of the multiplier and multiplicand of the decimal point single precision data, the number of digits thereof is aligned with the number of digits of the exponent part data of the multiplier and multiplicand of the floating point double precision data, and the data conversion means (600), A first adding means (800) for inputting the output of the data converting means (600) and adding and outputting the both, and a predetermined number of lower digits of data of the output of the first adding means are inputted, When the input is exponent part data of the floating point double precision data, it is output as it is, and when the input is exponent part data of the floating point single precision data, a correction means for correcting and outputting a fixed number of digits of data ( 900), When calculating the floating-point double-precision data, an addition / subtraction process is performed between the data of a predetermined upper digit number of the output of the first adding means and a value for normalizing the input data with a reference value, and the result is output. A multiplier having two adding means (100).