JPH0686247A - Receiver/reproducer for digital picture signal - Google Patents

Abstract

(57) [Abstract] [Purpose] To correct errors in received or reproduced image data without using error correction codes. [Structure] The reproduced and DCT-decoded input data is supplied and converted into a 3 × 3 block structure by a 3-line memory 22 and a blocking circuit 23. ADRC
The encoding circuit 24 generates the encoded value DTx of the central pixel data and the data DT generated from the peripheral 8 pixel data. The synchronization circuit 25 generates class information consisting of 8 pixel data and supplies it to the memory 29a as a read address. The existence range data and the prediction data DTx∧ are stored in advance in the memory 29a by training.
An error is detected by comparing the existence range with the reproduction data DTx, and when there is an error, the prediction data DTx∧
Is selected by the selector 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal receiving / reproducing apparatus, and more particularly to an apparatus capable of correcting error data without using an error correction code.

[0002]

2. Description of the Related Art When recording / reproducing a digital image signal with a VTR, for example, error correction coding is usually performed as a countermeasure against an error. As the error correction code, simple parity, Reed-Solomon code, a combination of these with interleaving, etc. have been put to practical use.

[0003]

However, in the case of the error correction code, if the error correction capability is attempted to be improved, the number of parity increases and the redundancy increases. Also,
If the error cannot be corrected, a conceal circuit that interpolates the erroneous pixel with the correct pixel data in the periphery is required. Data such as computer software is generally non-correlated. However, in the case of image signals, there are spatial and temporal correlations.

Therefore, it is an object of the present invention to pay attention to the existence of spatial correlation of image signals, and to receive / receive a digital image signal capable of correcting an error without using an error correction code.
It is to provide a reproducing apparatus.

[0005]

According to a first aspect of the present invention, there is provided a digital image signal receiving / reproducing apparatus including an error detecting circuit for detecting an error in a received or reproduced digital image signal. A classifying circuit that classifies the target pixel based on a plurality of pixel signals that are temporally or spatially adjacent to each other, a memory circuit that stores existing area data for each class prepared by training, and a class. The output of the comparison circuit has a read circuit for reading the existing area data of the corresponding class of the memory circuit using the output of the division circuit as address information, and a comparison circuit for comparing the output of the read circuit with the pixel data of the target pixel. The digital image signal receiving / reproducing apparatus is adapted to detect the presence or absence of an error based on the above.

According to a second aspect of the present invention, in the above-described digital image signal receiving / reproducing apparatus, the memory circuit further stores representative value related information for each class, and it is determined that there is an error based on the output of the comparison circuit. A digital image signal receiving / reproducing apparatus characterized in that, when detected, the pixel data of interest is replaced with a representative value formed based on representative value related information.

According to a third aspect of the present invention, in the above-mentioned digital image signal receiving / reproducing apparatus, the received or reproducing digital image signal is an encoded signal, and the digital image signal receiving / reproducing apparatus is A digital image signal having a decoding circuit for decoding an encoded image signal, wherein the classification circuit is configured to perform classification based on the decoded output of a plurality of pixel signals close to the pixel of interest. Is a receiving / reproducing device of.

According to a fourth aspect of the present invention, in the above-mentioned digital image signal receiving / reproducing apparatus, the encoded image signal is D
It is an apparatus for receiving / reproducing a digital image signal, wherein the CT coefficient data is a variable-length encoded signal.

According to a fifth aspect of the present invention, in the above-mentioned digital image signal receiving / reproducing apparatus, the classification circuit is A
It has a DRC encoding circuit, is supplied with the target pixel data and a plurality of adjacent pixel data, and among the encoded data, the encoded data of a plurality of adjacent pixels is used as class information. It is a device for receiving / reproducing a digital image signal.

According to a sixth aspect of the present invention, in the digital image signal receiving / reproducing apparatus described above, the presence area data has a maximum value and a minimum value that are true values detected for each class. It is a signal receiving / reproducing device.

According to a seventh aspect of the present invention, in the above-mentioned digital image signal receiving / reproducing apparatus, the representative value related information is an average value of true values detected for each class. It is a receiving / reproducing device.

According to an eighth aspect of the present invention, in the above-described digital image signal receiving / reproducing apparatus, the existence area data is coefficient data calculated with adjacent plural pixel data and allowable error range information. A characteristic digital image signal receiving / reproducing apparatus.

According to a ninth aspect of the present invention, in the above-mentioned digital image signal receiving / reproducing apparatus, the representative value related information is coefficient data calculated as a plurality of adjacent pixel data, and the coefficient data and the adjacent plural pixel data. Is a receiver / reproducer of a digital image signal, wherein a representative value is obtained by calculating

According to a tenth aspect of the present invention, in the above-described digital image signal receiving / reproducing apparatus, a counter circuit for counting the number of pixels detected as having an error in a predetermined period, and an error based on the output of the counter circuit. Is a device for receiving / reproducing a digital image signal, characterized in that the range information is variable.

[0015]

[Function] By classifying data from the data adjacent to the pixel of interest, and comparing the signal level existence area of the current pixel prepared in each class with the actual level, an error is detected probabilistically. Also, the error can be corrected by replacing the predicted value prepared for each class.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below. FIG. 1 shows a schematic configuration of signal processing of this embodiment, that is, a digital VTR. A digital video signal, for example, a signal in which one sample is quantized into 8 bits, is supplied from an input terminal indicated by 1. This digital video signal is supplied to the blocking circuit 2. In this embodiment, in the blocking circuit 2, the effective area of one field or one frame is a DC with a size of (8 × 8) pixels.
It is divided into T blocks.

The digital video signal scan-converted in the order of blocks from the blocking circuit 3 is converted into DCT (Discrete).
te Cosine Transform) circuit 3. From the DCT circuit 3, coefficient data composed of one DC component and 63 AC components is generated. This coefficient data is the quantization circuit 4
Is supplied to. In the quantization circuit 4, the coefficient data is requantized with a desired quantization step width, and the number of bits of data is reduced. The output of the quantizing circuit 4 is supplied to a VLC (variable length code) encoding circuit 5, subjected to variable length encoding processing such as run length code and Huffman code, and further compressed.

The data of the DC component generated in the DCT circuit 3 is transmitted as it is without being processed by the quantization circuit 4 and the VLC coding circuit 5 because it is highly important for the image restoration of the block. The framing circuit 6 composes the DC component, the variable length coded data from the VLC coding circuit 5 and other control and ID data into continuous data of the sync block. In the past, error correction coding was performed at the time of framing, but in the present invention, error correction coding is unnecessary.

The output of the framing circuit 6 is supplied to the rotary head H via the recording circuit 7 and recorded on the magnetic tape T as an oblique track. The recording circuit 7 includes a channel encoding circuit, a recording amplifier and the like. Channel encoding is a process for reducing the DC component of recorded data. Usually two or more rotary heads are used, but for simplicity only one head is shown.

The reproduced data taken out from the magnetic tape T by the rotary head H is supplied to a reproducing circuit 11 including a reproducing amplifier, a channel decoding circuit and the like, and is subjected to channel coding decoding. The output data of the reproducing circuit 11 is supplied to the frame disassembling circuit 12, and various data is separated from the recorded data. The output data of the frame decomposing circuit 12 is supplied to the VLC decoding circuit 13. The VLC decoding circuit 13 performs variable length coding decoding.

The VLC decoding circuit 13 includes an inverse quantization circuit 1
4 is connected. The inverse quantization circuit 14 performs a process reverse to the quantization performed by the recording side quantization circuit 4. The output data of the inverse quantization circuit 14 is supplied to the inverse DCT circuit 15. Inverse DCT
The circuit 15 decodes the coefficient data into pixel data of an (8 × 8) block. The output data of the inverse DCT circuit 15 is supplied to the block decomposition circuit 16. The block decomposition circuit 16 restores the data order from the block order to the raster scan order. Block decomposition circuit 1
The output data of 6 are supplied to the correction circuit 17 according to the present invention. Output data is obtained at the output terminal 18 of the correction circuit 17.

An example of the correction circuit 17 according to the present invention is shown in FIG.
Shown in. The reproduced data from the block decomposition circuit 16 is supplied to the input terminal 21. The reproduction data is supplied to the 3-line memory 22, and the output data of the 3-line memory 22 is supplied to the blocking circuit 23. Blocking circuit 23
Output data is supplied to the ADRC encoding circuit 24.

As shown in FIG. 4, the blocking circuit 43 forms the block x1, then forms the block x2, and then forms the block x3. That is, blocks that are shifted by one pixel in the horizontal direction are sequentially formed. A 3-line memory 22 is provided for forming overlapping blocks. In addition, when the formation of a block is completed for one line period and a new block is formed under the block, a block shifted by one line is formed. One pixel in the center of each block is a pixel for error detection and error correction.

The ADRC encoding 24 is performed by the maximum value MAX, the minimum value MIN, MAX and M of the pixel value for each block of 9 pixels.
The dynamic range DR which is the difference of IN is detected, and the pixel value is quantized by adapting to the dynamic range DR. The ADRC encoding circuit 24 is an encoding circuit that generates 1-bit quantized data.

An example of the ADRC encoding circuit 24 is shown in FIG. In FIG. 5, with respect to the data from the input terminal 51, the detection circuit 52 detects the maximum value MAX and the minimum value MIN for each block. MAX and MIN are supplied to the subtraction circuit 53, and its output has a dynamic range DR.
Occurs. The input data and MIN are supplied to the subtraction circuit 54, and the minimum value is removed from the subtraction circuit 54, so that normalized pixel data is generated.

The dynamic range DR is supplied to the division circuit 55, the normalized pixel data is divided by the dynamic range DR, and the quantized data DTx is output to the output terminal 58.
(For example, data up to 3 digits of decimal point) is extracted. In FIG. 4, DTx1, DTx2, and DTx3 represent the quantized data of the blocks x1, x2, and x3. Further, the output data of the division circuit 55 is supplied to the comparison circuit 56.
The comparison circuit 56 determines whether the division calculation power of the eight pixels other than the central pixel is larger or smaller than 0.5 with reference to 0.5. According to this result, the data DT of "0" or "1" is generated. This comparison output DT is output terminal 57.
Taken out.

Returning to FIG. 2, DT in the output data of the above-mentioned 1-bit ADRC encoding circuit 24 is supplied to the synchronization circuit 25, and the quantized data DTx is supplied to the selector 26 and the comparison circuits 30 and 31. Supplied. As described above, the synchronization circuit 25 synchronizes the comparison result DT of the eight pixels in the block excluding the pixel at the center position. The output data (8 bits) of the synchronizing circuit 25, that is, the class information is supplied to the memory 29a as a read address signal.

The memory 29a stores existence area data (MAX∧ and MIN∧) for each class formed in advance by training and a representative value (DTx∧) predicted for each class as described later. . Synchronization circuit 2
When the class information from 5 is given, the above-mentioned representative value corresponding to the class information is read from the memory 29a.

The representative value DTx∧ read out is the selector 26.
Is supplied to. The read MAX ∧ is supplied to the comparison circuit 30, and MIN ∧ is supplied to the comparison circuit 31. The outputs of the comparison circuits 30 and 31 are supplied to the logic 32, and the logic 32 generates a control signal for controlling the selector 26. The comparison circuits 30 and 31 and the logic 32 function as a window comparator. That is, MAX
When ∧ <DTx <MIN∧, the quantized data DTx exists in the existence area, so it is determined that the data DTx is not an error, and other DTx <MIN∧, DTx> M.
When AX∧, the data DTx is judged to be an error.

If there is no error, the selector 26 outputs A
If the output data DTx of the DRC encoding circuit 24 is selected and it is determined that there is an error, the selector 26 causes the memory 29 to operate.
The read data DTx∧ from a is selected. Therefore, instead of the data determined to be in error, the data DTx
∧ is selected. The selected output of the selector 26 and the DR and MIN from the ADRC encoding circuit 24 are the ADRC decoding circuit 2
7 is supplied.

The ADRC decoding circuit 27, contrary to the above-mentioned encoding, multiplies the dynamic range DR and the output data of the selector 26 and adds the minimum value MIN to the multiplication result. The output data with the error corrected is taken out to the output terminal 28 of the ADRC decoding circuit 27. In this way, the pixel data in error can be corrected without using error correction coding.

The memory 29a stores existing area data created in advance by training and representative data predicted for each class. FIG. 3 shows a configuration during training. In FIG. 3, a digital video signal is supplied to 41, and this is supplied to the blocking circuit 43 via the 3-line memory 42. The output of the blocking circuit 43 is supplied to the ADRC encoding circuit 44.

The three-line memory 42, the blocking circuit 43, and the ADRC encoding circuit 44 are the three-line memory 22, the blocking circuit 23, and the A circuit of the correction circuit 17 described above.
It is similar to the DRC encoding circuit 24. However, the input data is preferably standard video data for training, and for example, a signal composed of still images of various patterns can be adopted. The comparison output DT being output from the ADRC encoding circuit 44 is supplied to the synchronization circuit 45, and its quantized data DTx is supplied to the memory 46a as its data input. The synchronization circuit 45 is the synchronization circuit 2 described above.
Similar to 5, the comparison outputs of the other 8 pixels except the central pixel of the 3 × 3 block are parallelized.

8 bits from the synchronization circuit 45 are stored in the memory 4
6a is supplied as its write address. Memory 4
The read address of 6a is formed by the address counter 47. The write address for the memory 46a is 8-bit class information from the synchronization circuit 46, and the actually obtained quantized data DTx of the central pixel is written in the memory 46a for each of the 256 classes. Get caught.

When the writing is completed, the data at each address (that is, each class) of the memory 46a is read from the memory 46a by the read address from the address counter 47. Read addresses from 0 to 255,
Increment. The read data is the averaging circuit 4
8 and the detection circuit 49. Averaging circuit 48
Predicts the representative value DTx∧ of each class, and the detection circuit 49
Is the maximum value MAX ∧ and M of the quantized data of each class.
Detect IN∧.

Output of averaging circuit 48 and detection circuit 49
Is supplied to the memory 29a as a data input, and is written in the address defined by the output of the address counter 47. As a result of training in this way,
In the memory 29a, 8 adjacent to each other in a 3 × 3 area
A class specified by a pixel, representative quantized data of that class (DTx ∧), and existence area data of that class (M
AX∧ and MIN∧) are stored. This memory 29a
Are used in the correction circuit 17 as described above.

FIG. 3 is for illustrating the principle of training in an easy-to-understand manner. Each address data area (depth) of the memory 29a is infinitely necessary, which is not practical. Therefore, the configuration shown in FIG. 6 is used. The 8-bit class information from the synchronization circuit 45 is supplied to the switching circuit 61. Further, the quantized data DTx is supplied to the comparison and selection circuits 65 and 66 and the addition circuit 67.

The switching circuit 61 selects the output terminal b in the first half (readout period) of one block period and selects the output terminal a in the latter half (write period). The write address from the output terminal a of the switching circuit 61 is supplied to the memory 46b. The output terminal b is supplied to the input terminal d of the switching circuit 63. Switching circuit 63
The output of the address counter 62 is supplied to the input terminal c of. The address counter 62 corresponds to the address counter 47 of FIG. Switching circuit 63
Selects the read address from the input terminal d during training, and selects the read address from the input terminal c after training.

The memory 46b has a cumulative value Σ, a maximum value, a minimum value, and a count value CNT as data input / output. The accumulated value output of the memory 46b is supplied to the adding circuit 67 and the dividing circuit 68. The addition output of the addition circuit 67 is used as the data input of the memory 46b. Therefore, the accumulated value of the quantized data of each class is input to the memory 46b.

The comparison and selection circuit 65 is supplied with the quantized data DTx and the minimum value output from the memory 46b,
The smaller data is selected and provided to memory 46b. The comparison and selection circuit 66 uses the quantized data DTx.
And the maximum value output from memory 46b are provided to select the larger data and provide it to memory 46b.
The count value output is supplied to the adding circuit 64, and the +1 added output is input to the memory 46b.

Since the memory 46b performs reading and then writing, the above-described configuration causes the memory 46b to store the accumulated value, the maximum value, the minimum value, and the generated value of the quantized data at the end of the training period. Frequency is stored for each class. After the training is completed, the switching circuit 63 is switched and the incrementing address from the address counter 62 is supplied as the read address for the memory 46b and the write address for the memory 29b.

The accumulated value from the memory 46b is the division circuit 68.
, The average value, that is, the predicted quantized data DTx∧ is generated at the output of the division by the frequency count value, and this is written in the memory 29b. Memory 46b
The maximum value and the minimum value from are stored in the memory 29b as the existence area data MAX∧ and MIN∧. The configuration of FIG. 6 can prevent the infinite depth direction of the data area of each address of the memory 46b from being infinite.

Next, another embodiment of the present invention will be described. The overall configurations of the recording circuit and the reproducing circuit of the other embodiment are the same as those in FIG. Another example of the correction circuit 17 is shown in FIG. Circuit blocks corresponding to the example of the correction circuit 17 (FIG. 2) described above are denoted by the same reference numerals. The weight coefficient data ω1 to ω8 and the allowable error range data σ are stored in the memory 29c by the training described later.

The blocking circuit 23 sequentially forms 3 × 3 blocks (pixel values in the blocks are represented by a to i),
The actual data e of the central pixel is supplied to the comparison operation circuit 71 and the selector 75. Eight pixel data other than the central pixel are the ADRC encoding circuit 24 and the arithmetic circuit 7.
2 is supplied. The ADRC encoding circuit 24 has the same structure as that of FIG. 5, but generates only the comparison output DT of 8 pixels. The synchronization circuit 25 connected to the ADRC encoding circuit 24 forms 8-bit class data, which is supplied as a read address of the memory 29c.

Weighting coefficient data ω1 to ω1 from the memory 29c
ω8 is supplied to the arithmetic circuit 72, and from the arithmetic circuit 72,
A predicted value e∧ of the central pixel e represented by the following equation is generated. e∧ = ω1a + ω2b + ω3c + ... + ω8i The estimated value e∧ from the arithmetic circuit 72 and the error range data σ are supplied to the adder circuit 73 to generate e∧ + σ. The predicted value e∧ and the error range data σ from the arithmetic circuit 72 are supplied to the subtraction circuit 74, and e∧−σ is generated. The output data of the adder circuit 73 and the subtractor circuit 74 are supplied to the comparison operation circuit 71.

The comparison operation circuit 71 determines that there is no error when the existence area, that is, e∧-σ <e <e∧ + σ is satisfied, and otherwise determines that there is an error. This comparison operation circuit 71 generates a control signal for the selector 75, and the selector 75 selects the actual data e when there is no error, and selects the predicted value e∧ when there is an error. Corrected output data is generated at the output terminal 76 of the selector 75.

FIG. 8 shows a training configuration for storing necessary data in the memory 29c. For training, a digital image signal with a standard picture is supplied to the input terminal 41. Circuit blocks corresponding to those in the configuration of FIG. 3 are designated by the same reference numerals. As shown in FIG. 8, the block formed by the blocking circuit 43 is composed of pixel value data of reference symbols a to i. The data of each block is supplied to the ADRC encoding circuit 44, the identification circuit 77, and the error calculation circuit 78. The 8-bit class information from the synchronization circuit 45 and the sequential address from the address counter 47 are supplied to the identification circuit 77.

The identification circuit 77 identifies the weighting factors ω1 to ω8 by which the sum of squared errors is minimized by the least squares method. The identification circuit 77 is provided with a data memory. In this data memory, the value of the pixel data in the block is written at the address that is the class information. For example, the addresses corresponding to a certain class include pixel data a (a1, a2, ..., An), pixel data b (b1, b2, ..., Bn), and pixel data c (c1, c2). , ..., cn), ...
.. Regarding pixel data i (i1, i2, ..., i
n) is stored. Pixel data is similarly stored for addresses of other classes.

Next, coefficient data ω1 to ω8 that minimize the error are obtained by the least squares method using the accumulated data. Focusing on one class, for this class the following formula holds: e1 = ω1a1 + ω2b1 + ω3c1 + ... + ω8i1 e2 = ω1a2 + ω2b2 + ω3c2 + ... + ω8i2 ... En = ω1an + ω2bn + ω3cn + ... + ω8in

Here, a1 to an, b1 to bn, ...
.., i1 to in are known, so that the weighting factors .omega.1 to .omega.8 that minimize the error squared with respect to e1 to en (actual values) are obtained. The same applies to other classes. Ω1 to ω8 of each class obtained by the identification circuit 77
Are sequentially written in the memory 29c with respect to the address from the address counter 47.

The error calculation circuit 78 uses the identified coefficient ω1.
.About..omega.8 and the actual data excluding e in the block are calculated to generate the predicted value e.varies. The calculation for detecting this error is performed for each class. The following plural error data Ei are obtained for a certain class.

Output data E1 to En of the error calculation circuit 78
Are supplied to the detection circuit 79. The detection circuit 79 detects the maximum value MAX and the minimum value MIN of the error of each class. The output of the detection circuit 79 is supplied to the multiplication circuit 80. The multiplication circuit 80 is supplied with a predetermined coefficient N (where 0 <N <1) from the input terminal 81. Multiplication circuit 80
Performs the following calculation to generate allowable error range data σ. It is desirable that the value of σ = (MAX-MIN) × N / 2 N be variable.

The data σ generated by the multiplication circuit 80 is sequentially written in the data area of each address of the memory 29c.
As described above, the weighting factors ω1 to ω8 and the allowable range data σ are set in the data area of each address by training.
And are stored respectively. This memory 29c is used in the correction circuit of FIG. As described above, the memory 29
It is possible to detect the presence or absence of an error and correct the error using the data of c.

Next, still another embodiment of the present invention will be described with reference to FIG. The modified circuit of FIG. 7 above is
The allowable range data σ read from the memory 29c is fixed. Still another embodiment has a learning function of changing σ according to the error rate. In FIG. 9, circuit blocks corresponding to those in FIG. 7 are designated by the same reference numerals.

The permissible range data σ read from the memory 29c is supplied to the adding circuit 73 and the subtracting circuit 74 via the multiplying circuit 82. The multiplication circuit 82 is a circuit for changing σ. As described above, the comparison operation circuit 71 generates a 1-bit output signal indicating whether or not the reproduced pixel data e is in error. This output signal is supplied to the counter 83, and the output signal indicating an error (for example, "1") is counted. The counter 83
Although not shown, it is reset every line.

As shown in FIG. 10, 3 × 3 blocks are sequentially formed by the blocking circuit 23. The counter 83 counts the number of errors regarding a plurality of blocks configured by pixel data of 3 lines. Counter 8
The count value of 3 is held in the latch 84, and the output of the latch 84 is supplied to the ROM 85 as an address. ROM
83 generates a coefficient K (0 <K ≦ 1) for changing. This coefficient K is supplied to the multiplication circuit 82, and the multiplication circuit 8
2 generates Kσ, and this value is used for processing the next one line.

The table stored in the ROM 83 has a tendency that K is small when the number of errors is small and K is large when the number of errors is large. In other words, if the number of errors is small, the allowable range σ of the error is reduced to increase the ratio of using the reproduction data. On the other hand, if the number of errors is large, the allowable range σ of the error is increased to increase the correction ratio. increase. As a result, the quality of the reproduced image can be improved.

Note that, unlike the embodiment of the correction circuit described above,
The training may be performed with the DCT coefficient and the correction may be performed with the DCT coefficient. Further, as block encoding for compressing the recording data amount, A other than DCT is used.
DRC, vector quantization, etc. may be used.

[0059]

According to the present invention, it is possible to correct an error in received or reproduced image data without using an error correction code. Therefore, it is possible to prevent the redundancy of the transmission data from increasing. As shown in FIG. 11, within the range of the maximum value MAX and the minimum value MIN of each class formed by training, centering on the representative quantized data,
The probability of including the actual data of the class is extremely high, and the error can be corrected with high accuracy.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a recording / reproducing circuit of a digital VTR to which the present invention can be applied.

FIG. 2 is a block diagram of an example of a correction circuit according to the present invention.

FIG. 3 is a block diagram of an example of a configuration for creating correction data.

FIG. 4 is a schematic diagram for explaining blocking.

FIG. 5 is a block diagram of an example of a 1-bit ADRC encoding circuit.

FIG. 6 is a block diagram of an example of a practical configuration for creating correction data.

FIG. 7 is a block diagram of another example of the correction circuit according to the present invention.

FIG. 8 is a block diagram of another example of a configuration for creating correction data.

FIG. 9 is a block diagram of still another example of the correction circuit according to the present invention.

FIG. 10 is a schematic diagram for explaining still another example of the correction circuit according to the present invention.

FIG. 11 is a schematic diagram for explaining error correction of the present invention.

[Explanation of symbols]

17 Correction circuit 29a, 29b, 29c Memory storing correction data

Claims (10)

[Claims] 1. A digital image signal receiving / reproducing apparatus comprising error detecting means for detecting an error in a received or reproduced digital image signal, wherein the detecting means is temporal or spatial of a target pixel to be detected. A classifying means for classifying on the basis of a plurality of pixel signals adjacent to each other, a memory means for storing the existence area data for each class prepared in advance by training, and an output of the classifying means as address information It has a reading means for reading the existence area data of the corresponding class of the memory means, and a comparing means for comparing the output of the reading means with the pixel data of the pixel of interest. A digital image signal receiving / reproducing device adapted to detect the presence / absence. 2. Reception / receipt of a digital image signal according to claim 1.
In the reproducing device, the memory means further stores representative value related information for each class, and when it is detected that there is an error based on the output of the comparing means, the target pixel data is set to the representative value related information. A digital image signal receiving / reproducing apparatus characterized in that it is replaced with a representative value formed based on the above. 3. Reception / receipt of the digital image signal according to claim 1.
In the reproducing apparatus, the received or reproduced digital image signal is an encoded signal, and the reception / reception of the digital image signal is performed.
The reproducing apparatus has a decoding unit that decodes the coded image signal, and the classification unit performs the classification based on the decoded outputs of a plurality of pixel signals that are close to the pixel of interest. Characteristic digital image signal receiving / reproducing apparatus. 4. Reception / receipt of a digital image signal according to claim 1.
In the reproducing apparatus, the coded image signal is a signal in which DCT coefficient data is variable length coded, and the digital image signal receiving / reproducing apparatus is characterized. 5. Reception / receipt of a digital image signal according to claim 1.
In the reproducing apparatus, the classifying unit includes an ADRC encoding unit, is supplied with the pixel data of interest and a plurality of adjacent pixel data, and encodes the adjacent pixels of the encoded data. An apparatus for receiving / reproducing a digital image signal, wherein the data is class information. 6. Reception / receipt of a digital image signal according to claim 1.
In the reproducing apparatus, in the presence area data, a true value detected for each class is a maximum value and a minimum value, and the digital image signal receiving / reproducing apparatus is characterized. 7. Reception / receipt of a digital image signal according to claim 1.
In the reproducing apparatus, the representative value related information is an average value of true values detected for each class, and a digital image signal receiving / reproducing apparatus. 8. Reception / receipt of a digital image signal according to claim 1.
In the reproducing apparatus, the presence area data is coefficient data calculated with the adjacent plural pixel data and range information of an allowable error, and a digital image signal receiving / reproducing apparatus. 9. Reception / receipt of a digital image signal according to claim 2.
In the reproducing apparatus, the representative value related information is coefficient data calculated with the adjacent plural pixel data, and the representative value is obtained by calculating the coefficient data and the adjacent plural pixel data. An apparatus for receiving / reproducing a digital image signal characterized by: 10. The digital image signal receiving / reproducing apparatus according to claim 8, wherein a counter means for counting the number of pixels detected as having an error in a predetermined period, and the error range based on the output of the counter means. A digital image signal receiving / reproducing apparatus characterized in that information is made variable.