JPH0690876B2 - Semiconductor memory - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory suitable for high integration.

BACKGROUND OF THE INVENTION FIG. 5 shows a configuration of a sense circuit which is frequently used in a conventional bipolar random access memory. In the figure,
501 is a memory cell array 502, 503, 508, 509 is a bit line, 50
4, 505, 510 and 511 are read transistors, 506 and 507 are common hose wires, and 512 and 513 are read current sources. The common senses 506 and 507 are connected to the emitters of transistors 516 and 517, respectively, whose load resistors 514 and 515 are connected to their collectors. The base potential VB of the transistors 516 and 517 is set so that the common sense lines 506 and 507 have an appropriate potential. The read operation in this circuit is performed as follows. If the memory cell connected to the bit lines 502 and 503 is selected, a read current flows from either one of the read transistors 504 and 505 according to the cell information, for example, the read transistor 504 and the read transistor 505. Does not flow a read current. Accordingly, the sense output S has a high potential and the sense output S has a low potential. The potential difference between the sense outputs S and S is amplified by an output circuit (not shown) in the next stage to obtain a data output.

In the conventional sense circuit described above, as can be seen from FIG. 5, the common sense lines 506 and 507 are connected to the read transistors by the number of bit line pairs. Therefore, the capacitance C _S of the common sense line is C _S ≈ C _A l + n × (C _TC + C _TS ) (C _A l: wiring capacitance of the common sense line, C _TC , C _TS : capacitance between the base and collector of the read transistor, It can be expressed by the capacitance between collector substrates, n: the number of bit line pairs. As can be seen from the above equation, the capacitance C _S of the common sense line increases with higher integration, that is, as the number n of bit line pairs increases. For this reason, the charging / discharging time of the sense line is increased and the access time is increased, which makes it difficult to achieve high integration.

It should be noted that the related technology of the sense circuit is disclosed in
-137185 and JP-A-59-178683.

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory having a sense circuit suitable for high integration.

[Outline of Invention]

In order to achieve the above object, in the present invention, the common sense line is divided into a plurality of parts to reduce the capacitance thereof. For this reason, the capacitance of the common sense line can be suppressed to a small level even with high integration, and it is possible to avoid an increase in access time due to charging and discharging of the common sense line.

Example of Invention

 Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 shows an embodiment of the present invention, in which two common sense lines are provided.
An example of division is shown. 101 is a memory cell array, 10
2, 103, 110, 111 are bit lines, 104, 105, 112, 113 are read transistors, 106, 107, 108, 109 are common sense lines, 1
The read current sources V _{B and B} are the bias potentials of the common sense lines. The common sense line is divided into 106 and 108 and 107 and 109, which are connected to the emitters of the multi-emitter transistors 118 and 119 in which the load resistors 116 and 117 are connected to the collectors. In the same figure, the read operation is as follows. Done. If the memory cell connected to the bit lines 102 and 103 is selected now, according to the information of the cell,
Either one of the read transistors 104 and 105,
For example, a read current flows from the read transistor 104, a read current does not flow from the read transistor 105, and another read transistor (for example, 11
2,113) do not flow the read current because they share the read currents 114 and 115. Therefore, the four common sense lines
Of the 106, 107, 108, and 109, the read current flows only in the common sense line 106, and the sense output S has a high potential and a low potential. The potential difference between the sense output S and the sense output S is amplified by the output circuit of the next stage (not shown) to obtain the data output.

As can be seen from Figure 1, in the present embodiment because it is common sense line is divided into two, is connected to and the common sense line (C _A l above) wiring capacitance of the common sense line. The number of read transistors (corresponding to n mentioned above) is 1 /
It becomes 2. Therefore, the capacitance of the common sense line (C _S described above) is half that of the conventional one, and the charge / discharge time of the common sense line can be reduced to about half that of the conventional one.

FIG. 2 is another embodiment of the present invention and shows an example in which the present invention is applied to a sense circuit of a method of detecting a potential difference between bit lines. Read transistor (eg 10
4, 105) are connected to a common power source 201, and constitute a current switch, the bases are connected to bit lines (102, 103), and the collectors are common sense lines (106, the same).
107). The same parts as those in FIG. 1 are designated by the same reference numerals. The read operation is the same as that of the embodiment shown in FIG. 1 except that the potential difference of the selected bit line is detected by the current switch.

FIG. 3 shows another embodiment of the present invention, in which the common sense line is divided into four parts. 303 is a memory cell array, 316 to 323 are bit lines, 304 to 307 are read transistors, and 308 to 311 are common sense lines. The common sense line is divided into 308 to 311, and the common sense lines 308 and 30
9 are connected to the emitters of the multi-emitter transistor 312, and the common sense lines 310 and 311 are connected to the emitters of the multi-emitter transistor 313. The collectors of the multi-emitter transistors 312 and 313 are connected to the respective emitters of the other multi-emitter transistor 314 having a load resistor 315 connected to the collector. Note that V _B , V _B ′
Is the bias potential.

The above circuit 301 (indicated by a broken line in the figure) is connected to the bit line (eg, 316) on the left side of the bit line pair, and the circuit 301
A circuit 302 of the same type as is connected to the right bit line (eg, 317) of the bit line pair.

The read operation is almost the same as the above-described two embodiments. For example, when a read current flows through the read transistor 304, the multi-emitter transistors 312 and 314 are used.
Since the read current flows through it, the sense output has a low potential. On the other hand, the sense output S of the circuit 302 has a high potential. The potential difference between the sense outputs S, is amplified by a next stage output circuit (not shown) to obtain a data output.

As can be seen from FIG. 3, since the common sense line is divided into four in this embodiment, the capacitance of the common sense line (described above)
C _S ) becomes 1/4 of the conventional one, and the charge / discharge time of the common sense line can be reduced to about 1/4 of the conventional one.

Further, in the above embodiment, an example in which the common sense line is divided into two and four is shown, but the same idea as in FIG. 3 is divided into eight and sixteen.
Division or more divisions are possible.

FIG. 4 shows another embodiment of the present invention, in which the sense output S directly drives an output transistor for data output. The sense circuit on the side of the sense output S is unnecessary and is therefore removed. The collector of the read transistor (for example, 104) connected to the left bit line is connected to the positive side of the power supply voltage. Conventionally, in the sense output circuit for driving the sense direct output transistor as described above, a high level level drop of the data output D _O is appropriate due to the voltage drop caused by the bias current of the common sense line (current due to the currents 518 and 519 in FIG. There was a problem that the logical level could not be obtained. However, in the circuit of FIG. 4, the common sense line is divided to reduce the capacitance thereof, so that the bias current (currents from the current sources 402 and 403) can be significantly reduced, and the high data output D ₀ . It is possible to make the level drop small enough not to be a problem. By directly driving the output transistor with the sense output in this way, the delay time in the output circuit can be significantly reduced and the access time can be shortened.

〔The invention's effect〕

According to the present invention, since the common sense line can be divided into a plurality of parts and the capacitance thereof can be reduced, a semiconductor memory having a sense circuit suitable for high integration can be provided.

[Brief description of drawings]

1, FIG. 2, FIG. 3, and FIG. 4 are main circuits showing an embodiment of the present invention. FIG. 5 is a main circuit showing a configuration of a conventional sense circuit. 101,301,501 ... Memory cell array, 106,107,108,109,3
08,309,301,311,506,507 …… Common sense line, S, ……
Sense output, 114,115,512,513 ... Read current source.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noriyuki Honma 1-280 Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi Ltd. (72) Kazuo Kanaya 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory (72) Inventor Masaaki Matsumoto 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Central Research Laboratory (72) Inventor Hiroaki Minami 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Central Research Laboratory (72) Inventor Kazuhiko Tani, 3681 Hayano, Mobara-shi, Chiba, Hitachi Device Engineering Co., Ltd. (56) Reference JP-A-60-247891 (JP, A)

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit lines, a memory cell arranged at an intersection of the word lines and the bit lines, a read transistor having an emitter or a base connected to the bit lines, and a plurality of read transistors. In a semiconductor memory composed of a common sense line in which the collectors of the read transistors are commonly connected, the common sense line is divided into a plurality, and each divided common sense line is connected to a collector with a load. A semiconductor memory characterized by being connected to each emitter of a transistor.