JPH0697747A - Emitter follower circuit - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to reduce the power consumption of an emitter follower circuit. [Configuration] Drain of p-channel MOS transistor MP, base of pull-down transistor Q2, and discharge circuit CSW
Of the pMOSMP and the collector of the pull-down transistor Q2 are connected to the emitter of the emitter follower transistor Q1, and the base of the emitter follower transistor Q1 and the gate of the pMOSMP are driven by the same phase signal. [Effect] During the transition when the output OUT switches from H to L,
A large current flows through the pull-down transistor Q2, and a large current flows through the emitter follower transistor Q1 during the transition from L to H. However, in the steady state of H and L, only a small current flows. Therefore, low power consumption is achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emitter follower circuit, and more particularly to an emitter follower circuit with low power consumption.

[0002]

2. Description of the Related Art Conventional ECL (Emitter Coupled Logic)
The type logic circuit is shown in FIG. The output stage of the logic circuit of FIG. 6 is an emitter follower circuit using an npn transistor QE1 and a constant current source IEF. The current of the constant current source IEF is used to discharge the load capacitance CL when the output falls from H to L. Therefore, there is a problem that it is necessary to increase this current in order to accelerate the fall of the output, and it is difficult to reduce the power consumption because the output is constantly flowing even in the steady state of H or L. .

In order to reduce the power consumption, there has been proposed a logic circuit including an active pull-down type emitter follower described in Japanese Patent Laid-Open No. 58-43628 as shown in FIG. The present technology of FIG. 7 uses a multi-emitter transistor Q5 as an emitter follower transistor, one emitter of which is for emitter follower output,
The other one emitter is for controlling the pnp transistor Q6. According to the present technology, when the output falls, pn
The base potential of the p-transistor Q6 rapidly drops to p
Since the np transistor Q6 is strongly turned on, the load capacitance CL is discharged quickly. Moreover, when the output is in the steady state of H or L, the base potential of the pnp transistor Q6 also becomes H or L, and the voltage applied between the base and the emitter of the pnp transistor is small. Therefore, p
The np transistor Q6 is in an off state, and has a characteristic that a small amount of current flows and power consumption is small. But,
In addition to npn transistors, this technology has p characteristics with excellent characteristics.
There is a problem that an np transistor must be prepared. In the circuits of FIGS. 6 and 7, since the emitter follower transistor Q5 is in the low resistance state at the time of rising of the output, the load capacitance CL is quickly charged.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to reduce the power consumption of an emitter follower circuit without simultaneously using an npn transistor and a pnp transistor.

[0005]

The above object is to provide a p-channel insulated gate field effect transistor (hereinafter referred to as pMOS).
The drain of the npn bipolar transistor for pull-down and one end of the discharge circuit are connected, the source of the pMOS and the collector of the npn bipolar transistor for pull-down are connected to the emitter of the npn bipolar transistor for emitter follower output, and the emitter follower output By using the base of the npn bipolar transistor for use as a first input point, the gate of the pMOS as a second input point, and driving the first input point and the second input point with an ECL logic circuit output of the same phase, To be achieved.

[0006]

When the output switches from H to L, a current flows through the pull-down npn bipolar transistor, causing L
During the transition from H to H, a current flows through the emitter follower output npn bipolar transistor. However, when H and L are stationary, no current flows in any of the transistors. Therefore, power consumption is reduced.

[0007]

FIG. 1 shows the first embodiment of the present invention. In the figure, CS is an ECL logic circuit, and AEF is an emitter follower at the output stage of the logic circuit. The AEF circuit connects the drain of the pMOS transistor MP, the base of the pull-down bipolar transistor Q2 and one end of the discharge circuit CSW,
The source of the MOS and the collector of the pull-down bipolar transistor are connected to the emitter of the emitter follower output bipolar transistor Q1.
The gate of the pMOS and the base of the emitter follower output bipolar transistor are input points. When the input IN of the ECL logic circuit is H, the output VO of the logic circuit is H, the voltage applied between the source and gate of the pMOS is small, and the pMOS is off. When the input starts to fall, the voltage between the source and gate of the pMOS expands and the pMOS turns on. Most of the on-current is used as the base current of the pull-down bipolar transistor Q2, and a large current flows through the collector of the transistor Q2. As a result, the load capacitance CL of the output OUT is quickly discharged, and the output falls rapidly. When the output potential, which is also the source potential of the pMOS, reaches L, the voltage between the source and gate of the pMOS becomes small again. Therefore, the pMOS is turned off,
The pull-down bipolar transistor Q2 is also turned off, and the discharge current becomes a slight current. On the other hand, when the input rises, the emitter follower output bipolar transistor Q1 is in a low resistance state, so that the output load capacitance C
L is charged quickly, and the output rises rapidly.
Then, when the output reaches H, the voltage between the source and gate of the pMOS decreases again. Therefore, pMOS
Turns off, the transistor Q2 also turns off, and the discharge current becomes a slight current. As described above, according to the present invention, a large current flows through the pull-down bipolar transistor during the transition of the output switching from H to L, and a large current flows through the emitter follower output bipolar transistor during the transition of the switching from L to H. However, a small amount of current flows when H and L are stationary. Therefore, power consumption is reduced.

Next, as a second embodiment, FIG. 2 shows an example in which the operation of the AEF circuit is made faster than that of the first embodiment. AE
In order to speed up the operation of the F circuit, it is necessary to lower the gate potential of the pMOS more quickly than the source potential by Vth (threshold voltage) or more and speed up the timing when the pMOS switches from off to on. Therefore, in this embodiment, the level shift circuit LS is provided between the ECL logic circuit CS and the emitter follower circuit AEF of the first embodiment. The figure shows an example in which the level is shifted by a transistor and a resistor. This level shift circuit sets the gate potential of the pMOS to a potential that is lower than the source potential by about Vth (threshold voltage), and accelerates the timing at which the pMOS switches from off to on when the output signal OUT falls.

Next, an example in which the first embodiment is applied to a word driver of a semiconductor memory device is shown in FIG. 3 as a third embodiment. The ECL logic circuit is shown as a 2-input NOR word driver WDR for simplicity. Input IN1 now
And IN2 are both L, the word line potential OUT which is the output of the AEF circuit becomes H, and the memory cell MC is selected. On the other hand, either one of the two inputs, or both
When switching from L to H, the word line potential OUT becomes L, and the memory cell MC is deselected. Also in this case AEF
The circuit operates in the same manner as described above, and the transistor Q2 rapidly discharges the load capacitance CL of the word line, so that the word line potential falls rapidly. Further, when the word line potential is H or L in a steady state, only a slight current flows through the transistor Q2. Therefore, the power consumption required for discharging the word line is reduced as compared with the constant current source method. In the first to third embodiments, when the value of the load capacitance CL of the emitter follower circuit AEF is large, one stage of conventional emitter follower circuit as shown in FIG. 6 is provided at the output stage of the ECL logic circuit CS. It is desirable to drive the emitter follower circuit AEF of the present invention. In this case, since the AEF circuit is not a heavy load, an emitter follower current smaller than the conventional one is sufficient, and power consumption is reduced.

Next, an example in which the first embodiment is applied to the output stage of the wired OR decode circuit is shown in FIG. 4 as a fourth embodiment. For the sake of simplicity, the case of 4 decoding is shown. The outputs of the ECL logic circuits CS0 and CS1 are wired-OR by the decode lines DL11 to DL14. A current source IEF is connected to each decode line via a level shift circuit LS in which a diode and a resistor are connected. The decode line is connected to the base of the emitter follower output transistor Q1 of the AEF circuit, and the output of the level shift circuit LS is connected to the gate of the pMOS transistor MP of the AEF circuit. Decode line DL11
The load capacitances CL11 to CL14 of the DL to DL14 are the load capacitances C of the AEF circuit in the conventional wired OR decode circuit.
It is L. The relationship between these load capacities is the load capacity CL1.
The values 1 to CL14 are several times smaller than the load capacity CL. Therefore, the decode lines DL11 to DL according to this embodiment are
The current of the current source IEF of 14 is only a fraction of that of the conventional one. Therefore, since the AEF circuit consumes power only during the transition when the signal switches, the total power consumption is reduced to a fraction. Even if the level shift circuit LS is not provided in the second to fourth embodiments, there is no problem in circuit operation.

Next, referring to FIGS. 5A, 5B and 5C, A
The discharge circuit CSW for discharging the base charge of the transistor Q2 of the EF circuit will be described. FIG. 6A shows the case where a resistor is used. PM when input / output starts to fall
The OS starts to turn on, a current flows through the resistor RZ, and the base potential of the transistor Q2 changes from the power supply voltage VEE to VBE of Q2.
The voltage is raised to a potential higher than (forward voltage) and Q2 is turned on. Then, when the input / output becomes L and the pMOS turns off, Q
The electric charge of the base of 2 is discharged to the power supply voltage VEE through the resistor RZ, and the base potential of Q2 is stepped down to the power supply voltage VEE. Without the discharging means, the boosted base potential of Q2 is maintained as it is for a long time, resulting in malfunction. FIG. 6B shows the case where an nMOS is used. In the figure, nM
Although the gate of OS is connected to the output OUT, there is no problem in operation if it is connected to the base of the transistor Q1 or the gate of pMOS. NM when input / output starts to fall
OS starts to turn off, the base potential of the transistor Q2 is boosted, and Q2 turns on. Then, when the input / output starts to rise, the nMOS starts to turn on and the base charge of the transistor Q2 is discharged. Furthermore, Figure (c) shows nM
An example is shown in which the source potential of OS and the emitter potential of the transistor Q2 are not common and are connected to different power sources. In this case, the source potential V2 of the nMOS is changed to the transistor Q2.
Is set to a potential close to VBE (base-emitter voltage ≈ 0.8 V) from the emitter potential V1 of. As a result, the timing at which the collector current of the transistor Q2 starts to flow becomes faster, the load capacitance CL of the output OUT is quickly discharged, and the output falls rapidly. In the above discussion, pM
The case where the emitter follower circuit is configured by using the OS and the npn transistor has been described.
Even if the emitter follower circuit is configured by using the np transistor, the same effect as described above can be obtained.

[0012]

According to the present invention, the power consumption of the emitter follower circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing an AEF circuit of this embodiment.

FIG. 6 is a diagram showing a first conventional example.

FIG. 7 is a diagram showing a second conventional example.

[Explanation of symbols]

 AEF ………… Emitter follower circuit CS ………… Logic circuit LS ………… Level shift circuit

(72) Inventor Hiroaki Nanbu 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Yoji Haruka 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi Ltd. (72) Kenichi Ohata, 3681 Hayano, Mobara-shi, Chiba, Hitachi Device Engineering Co., Ltd. (72) Takeshi Kusunoki, 3681, Hayano, Mobara-shi, Chiba, Hitachi Device Engineering Co., Ltd.

Claims (8)

[Claims] 1. A drain and a pull-down np of a p-channel insulated gate field effect transistor (hereinafter referred to as pMOS).
The base of the n bipolar transistor is connected to one end of the discharge circuit, and the source of the pMOS and the pull-down n
The collector of the pn bipolar transistor is connected to the emitter of the emitter follower output npn bipolar transistor, and the base of the emitter follower output npn bipolar transistor is used as a first input point, and the pMOS is connected.
Is used as a second input point, and the first input point and the second input point are driven by signals of the same phase, an emitter follower circuit. 2. The first input point and the second input point are driven at the same potential, or a level shift circuit is provided so that the second input point is at a potential lower than that of the first input point. The emitter follower circuit according to claim 1, which is driven. 3. The emitter follower circuit according to claim 1, wherein the signal is an output of a wired or decode logic circuit of an ECL logic circuit or a word driver of a semiconductor memory. 4. The other end of the discharge circuit and the emitter of the pull-down npn bipolar transistor are connected to the same power source, or the other end of the discharge circuit is connected to the emitter of the pull-down npn bipolar transistor. The emitter follower circuit according to claim 1, wherein the emitter follower circuit is connected to a power source having a potential higher than the potential. 5. An n-channel insulated gate field effect transistor (hereinafter referred to as nMOS) drain and pull-up pn.
The base of the p bipolar transistor is connected to one end of the charging circuit, and the source of the nMOS and the pull-up p
The collector of the np bipolar transistor is connected to the emitter of the pnp bipolar transistor for emitter follower output, and the base of the pnp bipolar transistor for emitter follower output is used as a first input point, and the pMOS is connected.
Is used as a second input point, and the first input point and the second input point are driven by signals of the same phase, an emitter follower circuit. 6. The first input point and the second input point are driven at the same potential, or a level shift circuit is provided so that the first input point is at a potential lower than that of the second input point. The emitter follower circuit according to claim 5, which is driven. 7. The emitter follower circuit according to claim 5, wherein the signal is an output of a wired or decode logic circuit of an ECL logic circuit or a word driver of a semiconductor memory. 8. The other end of the charging circuit and the emitter of the pull-up pnp bipolar transistor are connected to the same power source, or the other end of the charging circuit is connected to the pull-up pnp bipolar transistor. The emitter follower circuit according to claim 5, wherein the emitter follower circuit is connected to a power source having a potential lower than the emitter potential.