JPH07212425A - Data receiver - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Even if a phase error θe of π / 4 ≦ | θe | occurs due to the frequency error Δf between the center frequency of the modulation signal and the local oscillation frequency, To compensate. [Structure] A local oscillator 4 used for quadrature detection, a baseband delay detection circuit 12 that outputs a modulation phase difference as an in-phase component and a quadrature component, an AFC circuit 15 that compensates θe generated in the in-phase component and the quadrature component, and an output. Judgment device 16, 17
In the data receiver of the π / 4 shift QPSK modulation system, the zero-cross determining means 13 for determining the range of the magnitude of θe in the output of the baseband differential detection circuit and its direction, and π / 4 ≦ | θe | When it is determined that the output data is πK / 4 (K is an integer) in the direction opposite to θe.
Data replacement means 18 for replacing the shifted data is provided. When θe is π / 4 or more, the AFC circuit performs the same phase compensation as in the conventional case, and the deciding unit outputs incorrect decision data, but the data replacing unit corrects it based on the detection result of the deciding unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus used for phase modulation digital radio communication, and more particularly to a data receiving apparatus which is capable of automatically correcting a wide range of phase errors in a synchronously detected received signal.

[0002]

2. Description of the Related Art In π / 4 shift QPSK, which is a four-valued phase modulation method, a transmitting side transmits any one of four symbols arranged at signal points on an I axis and a Q axis, and then It is said that any one of the four symbols arranged at signal points on the axis rotated by 45 ° from the I-axis and the Q-axis is transmitted, and then any one of the symbols on the I-axis and the Q-axis is transmitted again. The operation is repeated in sequence. The information to be transmitted is represented by the phase difference between the symbol and the next transmitted symbol. The phase difference is ± π / 4 and ± 3π /
4 can be taken, and the cosine and sine of each phase difference represent binary information of 0 or 1, respectively. Therefore, information of either (0,0) (1,0) (0,1) or (1,1) can be transmitted by one phase difference.

The signal point of this phase difference Δφ is the horizontal axis on the I axis,
In the phase diagram in which the Q axis is displayed on the vertical axis,
It is displayed in a position that overlaps the black circle of. The arrow attached to each signal point indicates the transition direction of the next signal. That is, when the current phase difference Δφ is π / 4, the next phase difference Δφ is
As a result, a larger value of 3π / 4 can be taken, or a smaller value of −π / 4 or −3π / 4 can be taken. On the other hand, when the current phase difference Δφ is 3π / 4, the next phase difference Δφ is π / 4, −π / 4 or −.
It can be set to 3π / 4, but a larger phase difference cannot be taken, and the current phase difference Δφ is −3π / 4.
In this case, as the next phase difference Δφ, −π / 4, π / 4 or 3π / 4 can be taken, but a smaller phase difference cannot be taken.

On the other hand, the receiving side obtains the modulation phase of the received signal by synchronous detection, detects the phase difference Δφ between the symbols of the modulation phase, and extracts the transmitted information. At this time, when there is a frequency error Δf between the center frequency of the received modulated signal and the oscillation frequency of the local oscillator used for synchronous detection, the detected phase difference includes the phase error θe. Therefore, the phase difference θe
Is provided, and the error rate in decoding is improved by this compensation.

As shown in FIG. 5, a conventional data receiving apparatus of this type includes an antenna 1 for receiving a π / 4 shift QPSK modulated wave signal and a receiving root Nyquist bandpass filter for shaping the waveform of the received signal. 2, a limiter amplifier 3 that limits the amplitude of the output of the root Nyquist bandpass filter 2, and a local oscillator 4 that constitutes a quadrature detection unit for detecting the in-phase component and the quadrature component of the baseband from the output of the limiter amplifier 3. a π / 2 phase shifter 5 and multipliers 6 and 7, and a low-pass filter 8 that removes a double carrier component included in the in-phase and quadrature outputs of the quadrature detection unit,
9, A / D converters 10 and 11 for converting the outputs of the low-pass filters 8 and 9 into digital signals, and A / D converters 10 and 11
From the outputs of the baseband delay detection circuit 12 and the output of the baseband delay detection circuit 12, the cosine and sine of the modulation phase difference between the symbols of the received signal are obtained based on the output of A timing reproduction circuit 14 for reproducing the bit timing and an automatic frequency control circuit 15 for removing the phase error θe component contained in the in-phase component I and the quadrature component Q of the modulation phase difference output from the baseband delay detection circuit 12 And determining devices 16 and 17 for determining binary information based on the in-phase output Ie or the quadrature output Qe output from the automatic frequency control circuit 15, and parallel-serial conversion for converting the outputs of the determining devices 16 and 17 into serial data. And a reception data output terminal 20 for outputting the output of the parallel-serial converter 19 as reception data.

Since the A / D converters 10 and 11 convert the outputs of the low-pass filters 8 and 9 into digital signals, they operate at a sampling frequency M times the symbol rate (M: a positive integer).

Further, the automatic frequency control circuit 15 takes in the in-phase component output I and the quadrature component output Q of the baseband delay detection circuit 12 in synchronization with the bit timing signal output from the timing reproduction circuit 14, While referring to the output, the center frequency of the received modulated signal and the local oscillator 4
The phase error θe occurring in each output of the baseband differential detection circuit 12 due to the frequency error Δf from the oscillation frequency of is compensated.

FIG. 6 shows a modulation phase difference Δφ between symbols obtained from the received π / 4 shift QPSK modulated wave signal.
2 is a phase diagram showing the case where the phase error θe is zero. Further, the phase diagram of FIG. 7 shows that when the phase error θe is generated due to the frequency error Δf between the center frequency of the received modulated signal and the oscillation frequency of the local oscillator 4 of the quadrature detection unit. It represents the phase difference.

This data receiving apparatus operates as follows. The quadrature detection unit frequency-converts the received π / 4 shift QPSK modulated wave signal into a baseband signal. This time,
The symbol rate of the modulated wave signal is f _R = 1 / T, and the sampling frequencies of the A / D converters 10 and 11 are f _S = 1 / T _S = M
If f _R (M: positive integer), the outputs X (kT _S ) and Y (kT _S ) of the A / D converters 10 and 11 are as shown in the following equations (1) and (2). X (kT _S ) = cos (φ (kT _S ) −2πΔfkT _S ) (1) Y (kT _S ) = sin (φ (kT _S ) −2πΔfkT _S ) (2) In equations (1) and (2), φ (kT _S ) is the received π /
It is the modulation phase of the 4-shift QPSK modulated wave signal, and Δf is the frequency error between the center frequency of this modulated signal and the oscillation frequency of the local oscillator 4.

The baseband differential detection circuit 12 outputs the outputs X (kT _S ) and Y (kT _S ) of the A / D converters 10 and 11 and the output X ((k−M) T _S ) one symbol before. , Y ((k−M) T _S ), the following equations (3) and (4) are calculated. I (kT _S ) = X (kT _S ) X ((k−M) T _S ) + Y (kT _S ) Y ((k−M) T _S ) (3) Q (kT _S ) = Y (kT _S ). X ((k−M) T _S ) −X (kT _S ) Y ((k−M) T _S ) (4) This equation (3) is located on the same circle of the phase diagram representing the modulation phase. Two points, that is, the point (X (kT _S ),
Y (kT _S )) and the point (X ((k−M) T _S ), Y ((k−M))
T _S )), the cosine of the phase difference between
Expression (4) calculates the sine of the phase difference.

As a result of this calculation, the baseband delay detection circuit 12 calculates the cosine and sine of the modulation phase difference of the received π / 4 shift QPSK modulation wave signal as shown in the following equations (5) and (6). , In-phase output I (kT _S ) and quadrature output Q (kT _S ), respectively.

I (kT _S ) = cos (Δφ (kT _S ) + θe) (5) Q (kT _S ) = sin (Δφ (kT _S ) + θe) (6) This Δφ (kT _S ) is obtained by the equation (7). ) Is the original modulation phase difference, and θe is the phase error due to Δf expressed by equation (8). Δφ (kT _S ) = φ (kT _S ) −φ ((k−M) T _S ) (7) θe = 2πΔfMT _S = 2πΔfT (8)

In the π / 4 shift QPSK modulation, the transmitting side has a modulation phase difference Δφ of ± π / 4 or ± 3π / 4.
Is transmitted, the modulation phase difference Δ at the time of identifying the received signal
From the equations (5) and (6), φ (kT _S ) is θe = 0 (Δf =
In the case of 0), it is shown on the I and Q planes of the phase diagram in FIG.
Is represented by a black dot signal point. Also, θe ≠ 0
When (Δf ≠ 0), as shown in FIG. 7, a constant phase error θe occurs with respect to the modulation phase difference on the phase diagram. As a result, the noise margin between the judgment boundary (I axis, Q axis) is reduced, and depending on the noise, the judgment boundary may be exceeded, and the error rate characteristic of the received data deteriorates.

The automatic frequency control circuit 15 compensates for the phase error θe caused by this Δf, and the baseband delay detection circuit
The output of 12 is the decision point of each quadrant (2n + 1) · π / 4
The operation of converting to (n: integer) signal points is performed. The automatic frequency control circuit 15 first synchronizes with the bit / timing signal reproduced by the timing reproduction circuit 14 and outputs I (nT) and Q of the baseband delay detection circuit 12 at the time of discrimination.
(nT) is taken in and the output Ie (n
T), Qe (nT) and outputs Id (nT), Q of the decision devices 16 and 17
The calculation for minimizing the mean square error with d (nT) is performed by the following equation.

WX (nT) = E [Id (nT) I (nT) + Qd (nT) Q (nT)] / E [I (nT) ² + Q (nT) ² ] (9) WY (nT) = E [Id (nT) Q (nT) -Qd (nT) I (nT)] / E [I (nT) ² + Q (nT) ² ] (10) Ie (nT) = I (nT) WX (nT) + Q (nT) WY (nT) (11) Qe (nT) = Q (nT) WX (nT) -I (nT) WY (nT) (12) However, E [.] in formulas (9) and (10) Indicates an average value calculation. WX (nT) in these equations is the phase error θ
The cosine of e, and WY (nT) corresponds to the sine of the phase error θe. In equations (11) and (12), the points (I (nT), Q (nT)) on the phase diagram This means that the in-phase component and the quadrature component are obtained when rotating by θe in the direction opposite to the error θe.

At this time, the frequency error Δf between the center frequency of the received modulated signal and the frequency of the local oscillator 4 is | Δf.
If | <f _R / 8, the phase error θe becomes | θe | <π / 4 from the equation (8).
With the I-axis and the Q-axis as the determination thresholds, Id (nT) or Qd (nT) can be output from the beginning without incurring a steady determination error. Therefore, equations (9) and (1
0), appropriate WX (nT) and WY (nT) can be obtained, and the automatic frequency control circuit 15 uses equations (11) and (12) to compensate the phase error θe for the in-phase component Ie ( nT) and the quadrature component Qe (nT) can be output. In addition, the determiner 18 can receive this and further output a determination result that does not include an error.

As described above, in the conventional data receiving apparatus including the automatic frequency control circuit 15, the frequency error Δf between the center frequency of the received modulated signal and the frequency of the local oscillator 4 is | Δf | <f _R / 8. Then, the influence of Δf can be compensated and the deterioration of the error rate characteristic of the received data can be improved.

[0018]

However, in the conventional data receiving apparatus, the frequency error Δf between the center frequency of the received modulated signal and the frequency of the local oscillator 4 is f _R / 8 ≦ |
When Δf | <f _R / 4 (f _R : symbol rate), the phase error θe in the output of the baseband differential detection circuit 12 is π / 4 ≦ | θe | <π / 2, and therefore FIG. On the I and Q planes, the quadrant in which the signal point at the time of identification exists moves from the quadrant in which the original signal point exists, and the deciding devices 16 and 17 that use the I axis and the Q axis as decision thresholds are A stationary judgment error will occur. Therefore, the automatic frequency control circuit 15 uses the W that corresponds to the cosine of the phase error θe.
WY (nT) corresponding to X (nT) or sine cannot be obtained correctly, and the phase is compensated in the wrong direction.
As a result, there is a problem that the error rate characteristic of the received data is significantly deteriorated.

The present invention solves the above-mentioned conventional problems, in which the output of the baseband differential detection circuit is caused by the frequency error Δf between the center frequency of the modulation signal and the frequency of the local oscillator 4. Phase error θ of π / 4 ≦ | θe |
It is an object of the present invention to provide a data receiving device having a wide automatic frequency control range, which can compensate for the occurrence of e.

[0020]

Therefore, according to the present invention, a local oscillator used for quadrature detection of a received modulated signal,
A baseband differential detection circuit that outputs cosine and sine in the modulation phase difference of the modulated signal as the in-phase component and the quadrature component, and due to the frequency difference between the center frequency of the modulated signal and the oscillation frequency of the local oscillator, In a π / 4 shift QPSK modulation type data receiver including an automatic frequency control circuit that compensates for a phase error θe generated in the in-phase component and the quadrature component, and a determiner that determines the output of the automatic frequency control circuit, Zero cross determination means for determining the range of the magnitude of the phase error θe occurring in the output of the circuit and its direction, and when the zero cross determination means determines the magnitude of the phase error θe as π / 4 ≦ | θe | The output data of the discriminator is π in the direction opposite to the direction of the phase error θe.
K / 4 (K is an integer) data replacement means for replacing the shifted data is provided.

Further, the zero-cross determining means determines, based on the number of signals crossing the I axis or Q axis of the phase diagram,
The range of the magnitude of the phase error θe and its direction are determined.

[0022]

Therefore, when the phase error θe is π / 4 or more, the automatic frequency control circuit performs the same phase compensation as that of the conventional device, and the deciding device outputs erroneous decision data. Is corrected by the data replacement unit using the determination result of the zero-cross determination unit.

The zero-cross determination means is a π / 4 shift QP
The magnitude and direction of the phase error are determined by using the property of the SK modulation method in the transition direction of the signal points. In other words, the occurrence of the phase error changes the frequency of signals that cross the positive or negative I axis or Q axis of the phase diagram.
By detecting it, the magnitude and direction of the phase error are determined.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data receiving apparatus according to an embodiment of the present invention is
As shown in FIG. 1, the in-phase component I and the quadrature component Q output from the baseband differential detection circuit 12 are taken in, and the magnitude of the phase error θe included in the modulation phase difference represented by these components and its positive / negative And a data replacement circuit 18 that replaces the output data of the determiners 16 and 17 according to the determination signal. Other configurations are the same as those of the conventional device (FIG. 5).

The zero-cross determination circuit 13 is a baseband differential detection circuit 12 on the I and Q planes of the phase diagram.
By counting the number of times the signal point representing the modulation phase difference output from the signal crosses the negative I axis, the number of times the positive Q axis is crossed, and the number of times the negative Q axis is crossed, the magnitude of the phase error θe and its positive / negative To determine.

This data receiving device operates as follows. The operations of the quadrature detection unit and the baseband delay detection circuit 12 are the same as those of the conventional device. Now, the symbol rate of the received π / 4 shift QPSK modulated wave signal is f _R = 1 /
The sampling frequency of the T and A / D converters 10 and 11 is f _S =
1 / T _S = Mf _R (M: positive integer), A / D converters 10 and 11
Let X (kT _S ) and Y (kT _S ) be the outputs of X (kT _S ) = cos (φ (kT _S ) −2πΔfkT _S ) (1) Y (kT _S ) = sin (φ (kT _{S), respectively.} ) −2πΔfkT _S ) (2) Here, φ (kT _S ) represents the modulation phase of the received π / 4 shift QPSK modulated wave signal, and Δf represents the frequency error between the center frequency of this modulated signal and the frequency of the local oscillator 4.

The baseband differential detection circuit 12 outputs I (kT _S ) = X (kT _S ) X ((k−M) T _S ) + Y (kT _S ) Y from the outputs of the A / D converters 10 and 11. ((k−M) T _S ) (3) Q (kT _S ) = Y (kT _S ) X ((k−M) T _S ) −X (kT _S ) Y ((k−M) T _S ) ( 4) is calculated, and the in-phase output I (kT _S ) and the quadrature output Q (k
Output as T _S ). This I (kT _S ) and Q (k
T _S ) is the received π as shown in equations (5) and (6).
It represents the cosine and sine of the modulation phase difference of the / 4 shift QPSK modulated wave signal.

I (kT _S ) = cos (Δφ (kT _S ) + θe) (5) Q (kT _S ) = sin (Δφ (kT _S ) + θe) (6) This Δφ (kT _S ) is obtained by the equation (7) ) Is the transmitted modulation phase difference, and θe is the phase error due to Δf expressed by equation (8). Δφ (kT _S ) = φ (kT _S ) −φ ((k−M) T _S ) (7) θe = 2πΔfMT _S = 2πΔfT (8)

Now, the modulation phase difference Δφ (kT _S ) at the time of identifying the received signal in the π / 4 shift QPSK modulation is θ
When e = 0 (Δf = 0), I of the phase diagram,
This is represented by the black circle signal points in FIG. 6 on the Q plane. As is clear from FIG. 6, in the case of θe = 0 (Δf = 0), the transition direction of the signal points in the second and third quadrants of the phase diagram is limited to the direction away from the negative I axis. ing. Therefore, the RF of the limiter amplifier 3 etc.
The signal point of the phase difference does not cross the negative I-axis except for the influence of noise by the receiving unit.

Further, the frequency error Δ of | Δf | <f _R / 8
When a phase error θe of | θe | <π / 4 is generated due to f, as shown in the phase diagram of FIG. 7, the difference between the reception signal point and the determination threshold (I axis, Q axis) is Noise margin is reduced. However, also in this case, except for the influence of noise, the signal point representing the phase difference between the received signals does not steadily cross the negative I axis.

However, the frequency error Δf is f _R / 8 ≦ | Δ
When f | <f _R / 4, π / 4 ≦ | due to Δf
A phase error θe of θe | <π / 2 occurs, but at this time, as shown in FIG. 2, the transition path of the signal point constantly crosses the negative I axis. At this time, π / 4
If ≦ θe <π / 2, the number of times the transition path of the signal point crosses the positive Q axis is larger than the number of times the transition path of the signal point crosses the negative Q axis. On the other hand, in the case of −π / 2 <θe ≦ −π / 4, conversely, the number of times the transition path of the signal point crosses the positive Q axis is smaller than the number of times the signal path transition path crosses the negative Q axis. .

The zero-cross determination circuit 13 takes in the in-phase component output signal I (kT _S ) and the quadrature component output signal Q (kT _S ) of the baseband delay detection circuit 12, and I, Q of the phase diagram represented by these signals. The number of times the signal point on the plane crosses the negative I axis, the number of times the positive Q axis is crossed, and the number of times the negative Q axis is crossed are respectively counted, and three kinds of determination signals DES (i) (i = 1,
2, 3) is output.

The zero-cross determination circuit 13 specifically performs this processing in the following procedure. First, I (kT _S ) and Q (k
N ₀ or a sample value of T _S) (N _0: positive integer) uptake, when the signal point I, across the Q-axis, using the fact that the sign inversion in accordance with its axis between each sample value occurs Then, the number CT1 of crossing the negative I-axis and the number of crossing CT2 of the positive Q-axis
And CT3, which is the number of times the negative Q axis is crossed, are respectively expressed by the formula (1
3) to (15). However, the sampling frequency f _S = 1 / T _S is sufficiently higher than the symbol rate f _R.

CT1 = [number of times I (kT _S ) <0: Q (kT _S ) Q ((k−1) T _S ) <0] (13) This CT1 has a negative I (kT _S ). Yes, and Q (k
It represents the number of times the sign of T _S ) is inverted. Similarly, CT2 = [Q (kT _S )> 0: I (kT _S ) I ((k−1) T _S ) <0 times] (14) CT3 = [Q (kT _S ) <0: I (kT _S ) I ((k−1) T _S ) <0]] (15) is calculated. At this time, a positive integer N ₁ that satisfies N ₁ <N ₀ is set as a threshold value, and if CT1 <N ₁ (16), the zero-cross determination circuit 13 determines that the phase error θe
Is determined to be | θe | <π / 4, and the determination signal DES
Output (1).

If [CT1 ≧ N ₁ ] ∩ [CT2> CT3] (17), that is, the number of times the signal point crosses the negative I axis is N ₁ or more, and the negative Q axis is If the number of crosses is less than the number of crosses on the positive Q axis, the zero-cross determination circuit 13
Determines that the phase error θe is π / 4 ≦ θe <π / 2, and outputs the determination signal DES (2).

If [CT1 ≧ N ₁ ] ∩ [CT2 <CT3] (18), that is, if the number of times the signal point crosses the negative I axis is N ₁ or more and the negative Q axis is If the number of times of crossing is greater than the number of times of crossing the positive Q axis, the zero cross determination circuit 13
Determines that the phase error θe is −π / 2 <θe ≦ −π / 4, and outputs the determination signal DES (3).

On the other hand, the automatic frequency control circuit 15 is, like the conventional apparatus, the signal at the time of identification outputted from the baseband differential detection circuit 12 as a decision point of the quadrant in which the signal exists (2n + 1).・ Perform the operation of converting to π / 4 (n: integer). Therefore, as shown in FIG. 3, the signal point of the output of the baseband differential detection circuit 12 is A on the I and Q planes.
When it is located at e, it is converted into the signal at the signal point B, and similarly, Be is converted into C, Ce is converted into D, and De is converted into A.

The conversion operation is specifically performed as follows. The automatic frequency control circuit 15 first synchronizes with the bit timing signal reproduced by the timing reproduction circuit 14,
The output I (n of the baseband differential detection circuit 12 at the time of identification
T) and Q (nT) are taken in, and the outputs Ie (nT) and Qe (nT) of the automatic frequency control circuit 15 and the outputs Id of the judging devices 16 and 17 are taken.
The calculation for minimizing the mean square error between (nT) and Qd (nT) is performed by the following equation.

WX (nT) = E [Id (nT) I (nT) + Qd (nT) Q (nT)] / E [I (nT) ² + Q (nT) ² ] (9) WY (nT) = E [Id (nT) Q (nT) -Qd (nT) I (nT)] / E [I (nT) ² + Q (nT) ² ] (10) Ie (nT) = I (nT) WX (nT) + Q (nT) WY (nT) (11) Qe (nT) = Q (nT) WX (nT) -I (nT) WY (nT) (12) However, E [.] in formulas (9) and (10) Indicates an average value calculation.

As a result, when the phase error θe at the output of the baseband delay detection circuit 12 is | θe | <π / 4, the automatic frequency control circuit 15 removes the data from the modulation phase difference of the received signal. However, when a phase error θe of π / 4 ≦ | θe | <π / 2 occurs in the output of the baseband differential detection circuit 12, the original modulation phase difference Δφ becomes π / 2 or −π /. Two-shifted data will be output. Since the automatic frequency control circuit 15 performs such compensation, a judging device for judging the output of the automatic frequency control circuit 15
16 and 17 output erroneous judgment data when the phase error θe is π / 4 ≦ | θe | <π / 2.
The data replacement circuit 18 corrects the judgment errors 6 and 17.

The data replacement circuit 18 is a zero cross determination circuit.
The judgment data is replaced according to the judgment signal sent from 13. The determination signal DES (1) from the zero-cross determination circuit 13
Since the phase error θe of | θe | <π / 4 has occurred in the output of the baseband differential detection circuit 12, the automatic frequency control circuit 15 performs normal phase compensation. Therefore, the data replacement circuit 18 is
Output 6 and 17 as they are without replacing them.

When the determination signal DES (2) is received from the zero-cross determination circuit 13, when the phase error θe of π / 4 ≦ θe <π / 2 occurs in the output of the baseband delay detection circuit 12. Therefore, the data replacement circuit 18 is
Replace the output of 16 and 17 with -π / 2 shifted data.
That is, as shown in FIG. 4, (determiner 16, 17 outputs Id, Qd) (data replacement circuit 18 outputs Ic, Qc) signal point A (π / 4) → signal point D (−π / 4) signal point B (3π / 4) → Signal point A (π / 4) Signal point C (−3π / 4) → Signal point B (3π / 4) Signal point D (−π / 4) → Signal point C (−3π / Replace the data in 4).

When the determination signal DES (3) is received from the zero-cross determination circuit 13, the output of the baseband delay detection circuit 12 has a phase error θe of −π / 2 <θe ≦ −π / 4.
Is occurring, the data replacement circuit 18 replaces the outputs of the determiners 16 and 17 with the data shifted by π / 2. That is, as shown in FIG. 4, (decision units 16 and 17 outputs Id and Qd) (data replacement circuit 18 outputs Ic and Qc) signal point A (π / 4) → signal point B (3π / 4) signal point B (3π / 4) → Signal point C (-3π / 4) Signal point C (-3π / 4) → Signal point D (-π / 4) Signal point D (-π / 4) → Signal point A (π / Replace the data in 4).

As a result of this replacement, the phase error θe is π / 4 ≦.
The determination error of the determiners 16 and 17 when | θe | <π / 2 is corrected, and the parallel-serial converter 19 and the reception data output terminal 20 are corrected.
The correct received data is output via.

As described above, in the apparatus of the embodiment, the frequency error Δf of f _R / 8 ≦ | Δf | <f _R / 4 exists between the center frequency of the received modulated signal and the frequency of the local oscillator 4. Then, the output of the baseband differential detection circuit 12 has π / 4 ≦ | θ
Even when the phase error θe of e | <π / 2 is generated, the zero-cross determination circuit 13 detects the range of the magnitude of the error and the direction (positive / negative), and the data replacement circuit 18 displays the detection result. Accordingly, the judgment data output from the judging devices 16 and 17 is
Correct data can be obtained by substituting the data shifted by π / 2 in the direction opposite to the phase error θe. Therefore, this device can equivalently perform automatic frequency control in the frequency range twice as large as that of the conventional device.

In the embodiment, the phase error θe is π / 4 ≦
The case of | θe | <π / 2 has been described in detail, but this idea can be extended to the case where the phase error θe is larger. The magnitude range and the direction of the phase error θe at that time can be obtained by focusing on the number of signals crossing either the positive or negative I axis or Q axis of the phase diagram. Is determined by the zero-cross determination circuit 13, and based on the determination result of the zero-cross determination circuit 13, the data replacement circuit 18 determines the determination data of the determination devices 16 and 17 by πK / 2.
(K is a positive or negative integer, and K is set according to the range and direction of the magnitude of the phase error θe) By replacing with the shifted data, correct received data can be obtained.

[0047]

As is apparent from the above description of the embodiments, the data receiving apparatus of the present invention has a frequency error Δf between the center frequency of the received modulated signal and the frequency of the local oscillator 4.
Causes the output of the baseband differential detection circuit 12 to be π / 4 ≦
Even if the phase error θe of | θe | occurs, the automatic frequency control can be accurately performed, and the deterioration of the error rate characteristic due to Δf can be widely improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data receiving apparatus of the present invention,

FIG. 2 is a phase diagram (π / 4 ≦ | representing a signal point of a signal output from a baseband differential detection circuit of the device.
(When θe | <π / 2)

FIG. 3 is a phase diagram showing compensating directions of signal points in an automatic frequency control circuit of the device,

FIG. 4 is a phase diagram showing a data replacement method in a data replacement circuit of the device;

FIG. 5 is a block diagram showing a configuration of a conventional data receiving device,

FIG. 6 is a phase diagram (in the case of θe = 0) showing a signal point of an output signal of a baseband differential detection circuit,

FIG. 7 is a phase diagram (in the case of θe <π / 4) showing the signal points of the output signal of the baseband differential detection circuit.

[Explanation of symbols]

 1 Antenna 2 Reception root Nyquist bandpass filter 3 Limiter amplifier 4 Local oscillator 5 π / 2 Phase shifter 6, 7 Multiplier 8, 9 Lowpass filter 10, 11 A / D converter 12 Baseband delay detection circuit 13 Zero cross Judgment circuit 14 Timing recovery circuit 15 Automatic frequency control circuit 16, 17 Judgment device 18 Data replacement circuit 19 Parallel-series converter 20 Received data output terminal

Claims (2)

[Claims] 1. A local oscillator used for quadrature detection of a received modulated signal, a baseband delay detection circuit for outputting cosine and sine of a modulation phase difference of the modulated signal as an in-phase component and a quadrature component, and An automatic frequency control circuit for compensating for a phase error θe generated in the in-phase component and the quadrature component due to a frequency difference between the center frequency of the modulation signal and the oscillation frequency of the local oscillator; and an output of the automatic frequency control circuit. In a π / 4 shift QPSK modulation type data receiving apparatus including a determining unit for determining, a zero cross determination for determining a range of the magnitude of the phase error θe occurring in the output of the baseband differential detection circuit and its direction Means and the zero-cross determination means determines the magnitude of the phase error θe as π / 4 ≦ | θe | , (K-integer)? K / 4 in the direction opposite to the direction of the phase error θe data receiving apparatus characterized in that a data replacement means for replacing the data shifted. 2. The zero-cross determination means is based on the number of signals crossing the I axis or the Q axis of the phase diagram,
The data receiving apparatus according to claim 1, wherein a range of magnitude of the phase error θe and a direction thereof are determined.